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authorDavid Nieto <dmartineznie@nvidia.com>2017-08-04 00:43:50 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-08-11 14:07:17 -0400
commitde8e057f7eebcfe676278826ab457bf86b1b36fd (patch)
tree1e49d8ca9858406296c12ebcee8e9da2ea9969c2
parent026d1f8efec6f88a6a910820b761ba1b335edc72 (diff)
gpu: nvgpu: GV100 support
Adds support of GV100 up to devinit. JIRA: EVLR-1693 Change-Id: Ic7aa5f1c20714e05954139f143abb6a3459858fc Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1532747 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat
-rw-r--r--drivers/gpu/nvgpu/Makefile6
-rw-r--r--drivers/gpu/nvgpu/gv100/fb_gv100.c58
-rw-r--r--drivers/gpu/nvgpu/gv100/fb_gv100.h22
-rw-r--r--drivers/gpu/nvgpu/gv100/gr_ctx_gv100.c38
-rw-r--r--drivers/gpu/nvgpu/gv100/gr_ctx_gv100.h28
-rw-r--r--drivers/gpu/nvgpu/gv100/gv100.h26
-rw-r--r--drivers/gpu/nvgpu/gv100/hal_gv100.c441
-rw-r--r--drivers/gpu/nvgpu/gv100/hal_gv100.h21
-rw-r--r--drivers/gpu/nvgpu/gv100/mm_gv100.c41
-rw-r--r--drivers/gpu/nvgpu/gv100/mm_gv100.h23
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h217
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h133
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ce_gv100.h101
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h449
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h1469
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fifo_gv100.h545
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_flush_gv100.h181
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h137
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gmmu_gv100.h1281
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h3905
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ltc_gv100.h613
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h245
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h645
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h205
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pram_gv100.h57
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h161
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h73
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h85
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h161
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h929
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h761
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_therm_gv100.h293
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_timer_gv100.h109
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h229
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_usermode_gv100.h89
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xp_gv100.h137
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xve_gv100.h201
-rw-r--r--drivers/gpu/nvgpu/nvgpu_gpuid_t19x.h9
-rw-r--r--include/uapi/linux/nvgpu-t19x.h2
39 files changed, 14125 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile
index 1d2feba4..e91b4e69 100644
--- a/drivers/gpu/nvgpu/Makefile
+++ b/drivers/gpu/nvgpu/Makefile
@@ -16,7 +16,11 @@ nvgpu-y += \
16 $(nvgpu-t19x)/gv11b/gr_ctx_gv11b.o \ 16 $(nvgpu-t19x)/gv11b/gr_ctx_gv11b.o \
17 $(nvgpu-t19x)/gv11b/pmu_gv11b.o \ 17 $(nvgpu-t19x)/gv11b/pmu_gv11b.o \
18 $(nvgpu-t19x)/gv11b/subctx_gv11b.o \ 18 $(nvgpu-t19x)/gv11b/subctx_gv11b.o \
19 $(nvgpu-t19x)/gv11b/regops_gv11b.o 19 $(nvgpu-t19x)/gv11b/regops_gv11b.o \
20 $(nvgpu-t19x)/gv100/mm_gv100.o \
21 $(nvgpu-t19x)/gv100/gr_ctx_gv100.o \
22 $(nvgpu-t19x)/gv100/fb_gv100.o \
23 $(nvgpu-t19x)/gv100/hal_gv100.o
20 24
21nvgpu-$(CONFIG_TEGRA_GK20A) += $(nvgpu-t19x)/gv11b/platform_gv11b_tegra.o 25nvgpu-$(CONFIG_TEGRA_GK20A) += $(nvgpu-t19x)/gv11b/platform_gv11b_tegra.o
22nvgpu-$(CONFIG_TEGRA_GK20A_NVHOST) += $(nvgpu-t19x)/common/linux/nvhost_t19x.o 26nvgpu-$(CONFIG_TEGRA_GK20A_NVHOST) += $(nvgpu-t19x)/common/linux/nvhost_t19x.o
diff --git a/drivers/gpu/nvgpu/gv100/fb_gv100.c b/drivers/gpu/nvgpu/gv100/fb_gv100.c
new file mode 100644
index 00000000..a3785266
--- /dev/null
+++ b/drivers/gpu/nvgpu/gv100/fb_gv100.c
@@ -0,0 +1,58 @@
1/*
2 * GV100 FB
3 *
4 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#include <nvgpu/types.h>
17
18#include <nvgpu/dma.h>
19#include <nvgpu/log.h>
20#include <nvgpu/enabled.h>
21#include <nvgpu/gmmu.h>
22
23#include "gk20a/gk20a.h"
24#include "gv11b/fb_gv11b.h"
25#include "gv100/fb_gv100.h"
26
27#include <nvgpu/hw/gv100/hw_fb_gv100.h>
28
29#define HW_SCRUB_TIMEOUT_DEFAULT 100 /* usec */
30#define HW_SCRUB_TIMEOUT_MAX 2000000 /* usec */
31
32static void gv100_fb_reset(struct gk20a *g)
33{
34 u32 val;
35 int retries = HW_SCRUB_TIMEOUT_MAX / HW_SCRUB_TIMEOUT_DEFAULT;
36
37 nvgpu_info(g, "reset gv100 fb");
38
39 /* wait for memory to be accessible */
40 do {
41 u32 w = gk20a_readl(g, fb_niso_scrub_status_r());
42 if (fb_niso_scrub_status_flag_v(w)) {
43 nvgpu_info(g, "done");
44 break;
45 }
46 nvgpu_udelay(HW_SCRUB_TIMEOUT_DEFAULT);
47 } while (--retries);
48
49 val = gk20a_readl(g, fb_mmu_priv_level_mask_r());
50 val &= ~fb_mmu_priv_level_mask_write_violation_m();
51 gk20a_writel(g, fb_mmu_priv_level_mask_r(), val);
52}
53
54void gv100_init_fb(struct gpu_ops *gops)
55{
56 gv11b_init_fb(gops);
57 gops->fb.reset = gv100_fb_reset;
58}
diff --git a/drivers/gpu/nvgpu/gv100/fb_gv100.h b/drivers/gpu/nvgpu/gv100/fb_gv100.h
new file mode 100644
index 00000000..b234fa13
--- /dev/null
+++ b/drivers/gpu/nvgpu/gv100/fb_gv100.h
@@ -0,0 +1,22 @@
1/*
2 * GV100 FB
3 *
4 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#ifndef _NVGPU_GV100_FB
17#define _NVGPU_GV100_FB
18
19struct gpu_ops;
20
21void gv100_init_fb(struct gpu_ops *gops);
22#endif
diff --git a/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.c b/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.c
new file mode 100644
index 00000000..2e605cce
--- /dev/null
+++ b/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.c
@@ -0,0 +1,38 @@
1/*
2 * GV100 Graphics Context
3 *
4 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#include "gk20a/gk20a.h"
17#include "gr_ctx_gv100.h"
18
19int gr_gv100_get_netlist_name(struct gk20a *g, int index, char *name)
20{
21 u32 ver = g->gpu_characteristics.arch + g->gpu_characteristics.impl;
22
23 switch (ver) {
24 case NVGPU_GPUID_GV100:
25 sprintf(name, "%s/%s", "gv100",
26 GV100_NETLIST_IMAGE_FW_NAME);
27 break;
28 default:
29 nvgpu_err(g, "no support for GPUID %x", ver);
30 }
31
32 return 0;
33}
34
35bool gr_gv100_is_firmware_defined(void)
36{
37 return true;
38}
diff --git a/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.h b/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.h
new file mode 100644
index 00000000..122e750f
--- /dev/null
+++ b/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.h
@@ -0,0 +1,28 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16#ifndef __GR_CTX_GV100_H__
17#define __GR_CTX_GV100_H__
18
19#include "gk20a/gr_ctx_gk20a.h"
20#include "nvgpu_gpuid_t19x.h"
21
22/* production netlist, one and only one from below */
23#define GV100_NETLIST_IMAGE_FW_NAME GK20A_NETLIST_IMAGE_D
24
25int gr_gv100_get_netlist_name(struct gk20a *g, int index, char *name);
26bool gr_gv100_is_firmware_defined(void);
27
28#endif /*__GR_CTX_GV100_H__*/
diff --git a/drivers/gpu/nvgpu/gv100/gv100.h b/drivers/gpu/nvgpu/gv100/gv100.h
new file mode 100644
index 00000000..eeea64a4
--- /dev/null
+++ b/drivers/gpu/nvgpu/gv100/gv100.h
@@ -0,0 +1,26 @@
1/*
2 * GV100 Graphics
3 *
4 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#ifndef GV100_H
20#define GV100_H
21
22#include "gk20a/gk20a.h"
23
24int gv100_init_gpu_characteristics(struct gk20a *g);
25
26#endif /* GV11B_H */
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c
new file mode 100644
index 00000000..337c607f
--- /dev/null
+++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c
@@ -0,0 +1,441 @@
1/*
2 * GV100 Tegra HAL interface
3 *
4 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#include <linux/types.h>
17#include <linux/printk.h>
18
19#include <linux/types.h>
20#include <linux/tegra_gpu_t19x.h>
21
22#include "gk20a/gk20a.h"
23#include "gk20a/fifo_gk20a.h"
24#include "gk20a/ctxsw_trace_gk20a.h"
25#include "gk20a/fecs_trace_gk20a.h"
26#include "gk20a/css_gr_gk20a.h"
27#include "gk20a/mc_gk20a.h"
28#include "gk20a/dbg_gpu_gk20a.h"
29#include "gk20a/bus_gk20a.h"
30#include "gk20a/pramin_gk20a.h"
31#include "gk20a/flcn_gk20a.h"
32#include "gk20a/regops_gk20a.h"
33
34#include "gm20b/ltc_gm20b.h"
35#include "gm20b/gr_gm20b.h"
36#include "gm20b/fifo_gm20b.h"
37
38#include "gp106/clk_gp106.h"
39#include "gp106/clk_arb_gp106.h"
40#include "gp106/pmu_gp106.h"
41
42#include "gm206/bios_gm206.h"
43#include "gp106/therm_gp106.h"
44#include "gp106/xve_gp106.h"
45#include "gp106/clk_gp106.h"
46#include "gp106/flcn_gp106.h"
47#include "gp10b/ltc_gp10b.h"
48#include "gp10b/therm_gp10b.h"
49#include "gp10b/mc_gp10b.h"
50#include "gp10b/ce_gp10b.h"
51#include "gp10b/priv_ring_gp10b.h"
52#include "gp10b/fifo_gp10b.h"
53#include "gp10b/fecs_trace_gp10b.h"
54
55#include "gv11b/hal_gv11b.h"
56#include "gv11b/gr_gv11b.h"
57#include "gv11b/mc_gv11b.h"
58#include "gv11b/ltc_gv11b.h"
59#include "gv11b/gv11b.h"
60#include "gv11b/ce_gv11b.h"
61#include "gv100/gr_ctx_gv100.h"
62#include "gv100/mm_gv100.h"
63#include "gv11b/pmu_gv11b.h"
64#include "gv100/fb_gv100.h"
65#include "gv11b/fifo_gv11b.h"
66#include "gv11b/gv11b_gating_reglist.h"
67#include "gv11b/regops_gv11b.h"
68#include "gv11b/subctx_gv11b.h"
69
70#include "gv100.h"
71#include "hal_gv100.h"
72
73#include <nvgpu/debug.h>
74#include <nvgpu/enabled.h>
75
76#include <nvgpu/hw/gv100/hw_proj_gv100.h>
77#include <nvgpu/hw/gv100/hw_fifo_gv100.h>
78#include <nvgpu/hw/gv100/hw_ram_gv100.h>
79#include <nvgpu/hw/gv100/hw_top_gv100.h>
80#include <nvgpu/hw/gv100/hw_pram_gv100.h>
81
82static int gv100_get_litter_value(struct gk20a *g, int value)
83{
84 int ret = EINVAL;
85 switch (value) {
86 case GPU_LIT_NUM_GPCS:
87 ret = proj_scal_litter_num_gpcs_v();
88 break;
89 case GPU_LIT_NUM_PES_PER_GPC:
90 ret = proj_scal_litter_num_pes_per_gpc_v();
91 break;
92 case GPU_LIT_NUM_ZCULL_BANKS:
93 ret = proj_scal_litter_num_zcull_banks_v();
94 break;
95 case GPU_LIT_NUM_TPC_PER_GPC:
96 ret = proj_scal_litter_num_tpc_per_gpc_v();
97 break;
98 case GPU_LIT_NUM_SM_PER_TPC:
99 ret = proj_scal_litter_num_sm_per_tpc_v();
100 break;
101 case GPU_LIT_NUM_FBPS:
102 ret = proj_scal_litter_num_fbps_v();
103 break;
104 case GPU_LIT_GPC_BASE:
105 ret = proj_gpc_base_v();
106 break;
107 case GPU_LIT_GPC_STRIDE:
108 ret = proj_gpc_stride_v();
109 break;
110 case GPU_LIT_GPC_SHARED_BASE:
111 ret = proj_gpc_shared_base_v();
112 break;
113 case GPU_LIT_TPC_IN_GPC_BASE:
114 ret = proj_tpc_in_gpc_base_v();
115 break;
116 case GPU_LIT_TPC_IN_GPC_STRIDE:
117 ret = proj_tpc_in_gpc_stride_v();
118 break;
119 case GPU_LIT_TPC_IN_GPC_SHARED_BASE:
120 ret = proj_tpc_in_gpc_shared_base_v();
121 break;
122 case GPU_LIT_PPC_IN_GPC_BASE:
123 ret = proj_ppc_in_gpc_base_v();
124 case GPU_LIT_PPC_IN_GPC_STRIDE:
125 ret = proj_ppc_in_gpc_stride_v();
126 break;
127 case GPU_LIT_ROP_BASE:
128 ret = proj_rop_base_v();
129 break;
130 case GPU_LIT_ROP_STRIDE:
131 ret = proj_rop_stride_v();
132 break;
133 case GPU_LIT_ROP_SHARED_BASE:
134 ret = proj_rop_shared_base_v();
135 break;
136 case GPU_LIT_HOST_NUM_ENGINES:
137 ret = proj_host_num_engines_v();
138 break;
139 case GPU_LIT_HOST_NUM_PBDMA:
140 ret = proj_host_num_pbdma_v();
141 break;
142 case GPU_LIT_LTC_STRIDE:
143 ret = proj_ltc_stride_v();
144 break;
145 case GPU_LIT_LTS_STRIDE:
146 ret = proj_lts_stride_v();
147 break;
148 case GPU_LIT_NUM_FBPAS:
149 ret = proj_scal_litter_num_fbpas_v();
150 break;
151 case GPU_LIT_FBPA_STRIDE:
152 ret = proj_fbpa_stride_v();
153 break;
154 case GPU_LIT_SM_PRI_STRIDE:
155 ret = proj_sm_stride_v();
156 break;
157
158 default:
159 break;
160 }
161
162 return ret;
163}
164
165int gv100_init_gpu_characteristics(struct gk20a *g)
166{
167 struct nvgpu_gpu_characteristics *gpu = &g->gpu_characteristics;
168
169 int err;
170
171 err = gk20a_init_gpu_characteristics(g);
172 if (err)
173 return err;
174
175 gpu->flags |=
176 NVGPU_GPU_FLAGS_SUPPORT_TSG_SUBCONTEXTS;
177
178 return 0;
179}
180
181
182
183static const struct gpu_ops gv100_ops = {
184 .ltc = {
185 .determine_L2_size_bytes = gp10b_determine_L2_size_bytes,
186 .set_zbc_s_entry = gv11b_ltc_set_zbc_stencil_entry,
187 .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry,
188 .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry,
189 .init_cbc = NULL,
190 .init_fs_state = gv11b_ltc_init_fs_state,
191 .init_comptags = gp10b_ltc_init_comptags,
192 .cbc_ctrl = gm20b_ltc_cbc_ctrl,
193 .isr = gv11b_ltc_isr,
194 .cbc_fix_config = gv11b_ltc_cbc_fix_config,
195 .flush = gm20b_flush_ltc,
196 .set_enabled = gp10b_ltc_set_enabled,
197 },
198 .ce2 = {
199 .isr_stall = gv11b_ce_isr,
200 .isr_nonstall = gp10b_ce_nonstall_isr,
201 .get_num_pce = gv11b_ce_get_num_pce,
202 },
203 .fifo = {
204 .init_fifo_setup_hw = gv11b_init_fifo_setup_hw,
205 .bind_channel = channel_gm20b_bind,
206 .unbind_channel = channel_gv11b_unbind,
207 .disable_channel = gk20a_fifo_disable_channel,
208 .enable_channel = gk20a_fifo_enable_channel,
209 .alloc_inst = gk20a_fifo_alloc_inst,
210 .free_inst = gk20a_fifo_free_inst,
211 .setup_ramfc = channel_gv11b_setup_ramfc,
212 .channel_set_priority = gk20a_fifo_set_priority,
213 .channel_set_timeslice = gk20a_fifo_set_timeslice,
214 .default_timeslice_us = gk20a_fifo_default_timeslice_us,
215 .setup_userd = gk20a_fifo_setup_userd,
216 .userd_gp_get = gv11b_userd_gp_get,
217 .userd_gp_put = gv11b_userd_gp_put,
218 .userd_pb_get = gv11b_userd_pb_get,
219 .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val,
220 .preempt_channel = gv11b_fifo_preempt_channel,
221 .preempt_tsg = gv11b_fifo_preempt_tsg,
222 .update_runlist = gk20a_fifo_update_runlist,
223 .trigger_mmu_fault = NULL,
224 .get_mmu_fault_info = NULL,
225 .wait_engine_idle = gk20a_fifo_wait_engine_idle,
226 .get_num_fifos = gv11b_fifo_get_num_fifos,
227 .get_pbdma_signature = gp10b_fifo_get_pbdma_signature,
228 .set_runlist_interleave = gk20a_fifo_set_runlist_interleave,
229 .tsg_set_timeslice = gk20a_fifo_tsg_set_timeslice,
230 .force_reset_ch = gk20a_fifo_force_reset_ch,
231 .engine_enum_from_type = gp10b_fifo_engine_enum_from_type,
232 .device_info_data_parse = gp10b_device_info_data_parse,
233 .eng_runlist_base_size = fifo_eng_runlist_base__size_1_v,
234 .init_engine_info = gk20a_fifo_init_engine_info,
235 .runlist_entry_size = ram_rl_entry_size_v,
236 .get_tsg_runlist_entry = gv11b_get_tsg_runlist_entry,
237 .get_ch_runlist_entry = gv11b_get_ch_runlist_entry,
238 .is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc,
239 .dump_pbdma_status = gk20a_dump_pbdma_status,
240 .dump_eng_status = gv11b_dump_eng_status,
241 .dump_channel_status_ramfc = gv11b_dump_channel_status_ramfc,
242 .intr_0_error_mask = gv11b_fifo_intr_0_error_mask,
243 .is_preempt_pending = gv11b_fifo_is_preempt_pending,
244 .init_pbdma_intr_descs = gv11b_fifo_init_pbdma_intr_descs,
245 .reset_enable_hw = gv11b_init_fifo_reset_enable_hw,
246 .teardown_ch_tsg = gv11b_fifo_teardown_ch_tsg,
247 .handle_sched_error = gv11b_fifo_handle_sched_error,
248 .handle_pbdma_intr_0 = gv11b_fifo_handle_pbdma_intr_0,
249 .handle_pbdma_intr_1 = gv11b_fifo_handle_pbdma_intr_1,
250 .init_eng_method_buffers = gv11b_fifo_init_eng_method_buffers,
251 .deinit_eng_method_buffers =
252 gv11b_fifo_deinit_eng_method_buffers,
253 .tsg_bind_channel = gk20a_tsg_bind_channel,
254 .tsg_unbind_channel = gk20a_tsg_unbind_channel,
255#ifdef CONFIG_TEGRA_GK20A_NVHOST
256 .alloc_syncpt_buf = gv11b_fifo_alloc_syncpt_buf,
257 .free_syncpt_buf = gv11b_fifo_free_syncpt_buf,
258 .add_syncpt_wait_cmd = gv11b_fifo_add_syncpt_wait_cmd,
259 .get_syncpt_wait_cmd_size = gv11b_fifo_get_syncpt_wait_cmd_size,
260 .add_syncpt_incr_cmd = gv11b_fifo_add_syncpt_incr_cmd,
261 .get_syncpt_incr_cmd_size = gv11b_fifo_get_syncpt_incr_cmd_size,
262#endif
263 .resetup_ramfc = NULL,
264 .device_info_fault_id = top_device_info_data_fault_id_enum_v,
265 .free_channel_ctx_header = gv11b_free_subctx_header,
266 .preempt_ch_tsg = gv11b_fifo_preempt_ch_tsg,
267 .handle_ctxsw_timeout = gv11b_fifo_handle_ctxsw_timeout,
268 },
269 .gr_ctx = {
270 .get_netlist_name = gr_gv100_get_netlist_name,
271 .is_fw_defined = gr_gv100_is_firmware_defined,
272 },
273#ifdef CONFIG_GK20A_CTXSW_TRACE
274 .fecs_trace = {
275 .alloc_user_buffer = gk20a_ctxsw_dev_ring_alloc,
276 .free_user_buffer = gk20a_ctxsw_dev_ring_free,
277 .mmap_user_buffer = gk20a_ctxsw_dev_mmap_buffer,
278 .init = gk20a_fecs_trace_init,
279 .deinit = gk20a_fecs_trace_deinit,
280 .enable = gk20a_fecs_trace_enable,
281 .disable = gk20a_fecs_trace_disable,
282 .is_enabled = gk20a_fecs_trace_is_enabled,
283 .reset = gk20a_fecs_trace_reset,
284 .flush = gp10b_fecs_trace_flush,
285 .poll = gk20a_fecs_trace_poll,
286 .bind_channel = gk20a_fecs_trace_bind_channel,
287 .unbind_channel = gk20a_fecs_trace_unbind_channel,
288 .max_entries = gk20a_gr_max_entries,
289 },
290#endif /* CONFIG_GK20A_CTXSW_TRACE */
291 .pramin = {
292 .enter = gk20a_pramin_enter,
293 .exit = gk20a_pramin_exit,
294 .data032_r = pram_data032_r,
295 },
296 .clk = {
297 .init_clk_support = gp106_init_clk_support,
298 .get_crystal_clk_hz = gp106_crystal_clk_hz,
299 .measure_freq = gp106_clk_measure_freq,
300 .suspend_clk_support = gp106_suspend_clk_support,
301 },
302 .clk_arb = {
303 .get_arbiter_clk_domains = gp106_get_arbiter_clk_domains,
304 .get_arbiter_clk_range = gp106_get_arbiter_clk_range,
305 .get_arbiter_clk_default = gp106_get_arbiter_clk_default,
306 .get_current_pstate = nvgpu_clk_arb_get_current_pstate,
307 },
308 .mc = {
309 .intr_enable = mc_gv11b_intr_enable,
310 .intr_unit_config = mc_gp10b_intr_unit_config,
311 .isr_stall = mc_gp10b_isr_stall,
312 .intr_stall = mc_gp10b_intr_stall,
313 .intr_stall_pause = mc_gp10b_intr_stall_pause,
314 .intr_stall_resume = mc_gp10b_intr_stall_resume,
315 .intr_nonstall = mc_gp10b_intr_nonstall,
316 .intr_nonstall_pause = mc_gp10b_intr_nonstall_pause,
317 .intr_nonstall_resume = mc_gp10b_intr_nonstall_resume,
318 .enable = gk20a_mc_enable,
319 .disable = gk20a_mc_disable,
320 .reset = gk20a_mc_reset,
321 .boot_0 = gk20a_mc_boot_0,
322 .is_intr1_pending = mc_gp10b_is_intr1_pending,
323 .is_intr_hub_pending = gv11b_mc_is_intr_hub_pending,
324 },
325 .debug = {
326 .show_dump = gk20a_debug_show_dump,
327 },
328 .dbg_session_ops = {
329 .exec_reg_ops = exec_regops_gk20a,
330 .dbg_set_powergate = dbg_set_powergate,
331 .check_and_set_global_reservation =
332 nvgpu_check_and_set_global_reservation,
333 .check_and_set_context_reservation =
334 nvgpu_check_and_set_context_reservation,
335 .release_profiler_reservation =
336 nvgpu_release_profiler_reservation,
337 .perfbuffer_enable = gk20a_perfbuf_enable_locked,
338 .perfbuffer_disable = gk20a_perfbuf_disable_locked,
339 },
340 .bus = {
341 .init_hw = gk20a_bus_init_hw,
342 .isr = gk20a_bus_isr,
343 .read_ptimer = gk20a_read_ptimer,
344 .bar1_bind = NULL,
345 },
346#if defined(CONFIG_GK20A_CYCLE_STATS)
347 .css = {
348 .enable_snapshot = css_hw_enable_snapshot,
349 .disable_snapshot = css_hw_disable_snapshot,
350 .check_data_available = css_hw_check_data_available,
351 .set_handled_snapshots = css_hw_set_handled_snapshots,
352 .allocate_perfmon_ids = css_gr_allocate_perfmon_ids,
353 .release_perfmon_ids = css_gr_release_perfmon_ids,
354 },
355#endif
356 .xve = {
357 .sw_init = xve_sw_init_gp106,
358 .get_speed = xve_get_speed_gp106,
359 .set_speed = xve_set_speed_gp106,
360 .available_speeds = xve_available_speeds_gp106,
361 .xve_readl = xve_xve_readl_gp106,
362 .xve_writel = xve_xve_writel_gp106,
363 .disable_aspm = xve_disable_aspm_gp106,
364 .reset_gpu = xve_reset_gpu_gp106,
365#if defined(CONFIG_PCI_MSI)
366 .rearm_msi = xve_rearm_msi_gp106,
367#endif
368 .enable_shadow_rom = xve_enable_shadow_rom_gp106,
369 .disable_shadow_rom = xve_disable_shadow_rom_gp106,
370 },
371 .falcon = {
372 .falcon_hal_sw_init = gp106_falcon_hal_sw_init,
373 },
374 .priv_ring = {
375 .isr = gp10b_priv_ring_isr,
376 },
377 .chip_init_gpu_characteristics = gv100_init_gpu_characteristics,
378 .get_litter_value = gv100_get_litter_value,
379 .bios_init = gm206_bios_init,
380};
381
382int gv100_init_hal(struct gk20a *g)
383{
384 struct gpu_ops *gops = &g->ops;
385 struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics;
386
387 gops->ltc = gv100_ops.ltc;
388 gops->ce2 = gv100_ops.ce2;
389 gops->clock_gating = gv100_ops.clock_gating;
390 gops->fifo = gv100_ops.fifo;
391 gops->gr_ctx = gv100_ops.gr_ctx;
392 gops->fecs_trace = gv100_ops.fecs_trace;
393 gops->pramin = gv100_ops.pramin;
394 gops->therm = gv100_ops.therm;
395 gops->mc = gv100_ops.mc;
396 gops->debug = gv100_ops.debug;
397 gops->dbg_session_ops = gv100_ops.dbg_session_ops;
398 gops->bus = gv100_ops.bus;
399#if defined(CONFIG_GK20A_CYCLE_STATS)
400 gops->css = gv100_ops.css;
401#endif
402 gops->xve = gv100_ops.xve;
403 gops->falcon = gv100_ops.falcon;
404 gops->priv_ring = gv100_ops.priv_ring;
405
406 /* clocks */
407 gops->clk.init_clk_support = gv100_ops.clk.init_clk_support;
408 gops->clk.get_crystal_clk_hz = gv100_ops.clk.get_crystal_clk_hz;
409 gops->clk.measure_freq = gv100_ops.clk.measure_freq;
410 gops->clk.suspend_clk_support = gv100_ops.clk.suspend_clk_support;
411
412 /* Lone functions */
413 gops->chip_init_gpu_characteristics =
414 gv100_ops.chip_init_gpu_characteristics;
415 gops->get_litter_value = gv100_ops.get_litter_value;
416 gops->bios_init = gv100_ops.bios_init;
417
418 __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true);
419 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
420 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
421 /* for now */
422 __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false);
423
424 g->bootstrap_owner = LSF_FALCON_ID_SEC2;
425
426 gv11b_init_gr(g);
427 gv100_init_fb(gops);
428 gv100_init_mm(gops);
429 gp106_init_pmu_ops(g);
430
431 g->name = "gv10x";
432
433 c->twod_class = FERMI_TWOD_A;
434 c->threed_class = VOLTA_A;
435 c->compute_class = VOLTA_COMPUTE_A;
436 c->gpfifo_class = VOLTA_CHANNEL_GPFIFO_A;
437 c->inline_to_memory_class = KEPLER_INLINE_TO_MEMORY_B;
438 c->dma_copy_class = VOLTA_DMA_COPY_A;
439
440 return 0;
441}
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.h b/drivers/gpu/nvgpu/gv100/hal_gv100.h
new file mode 100644
index 00000000..a7c74db0
--- /dev/null
+++ b/drivers/gpu/nvgpu/gv100/hal_gv100.h
@@ -0,0 +1,21 @@
1/*
2 * GV100 Tegra HAL interface
3 *
4 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#ifndef _NVGPU_HAL_GV11B_H
17#define _NVGPU_HAL_GV11B_H
18struct gk20a;
19
20int gv100_init_hal(struct gk20a *gops);
21#endif
diff --git a/drivers/gpu/nvgpu/gv100/mm_gv100.c b/drivers/gpu/nvgpu/gv100/mm_gv100.c
new file mode 100644
index 00000000..fbc5df79
--- /dev/null
+++ b/drivers/gpu/nvgpu/gv100/mm_gv100.c
@@ -0,0 +1,41 @@
1/*
2 * GV100 memory management
3 *
4 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#include "gk20a/gk20a.h"
17#include "gv11b/mm_gv11b.h"
18#include "gv100/mm_gv100.h"
19
20#include <nvgpu/hw/gv100/hw_fb_gv100.h>
21
22static size_t gv100_mm_get_vidmem_size(struct gk20a *g)
23{
24 u32 range = gk20a_readl(g, fb_mmu_local_memory_range_r());
25 u32 mag = fb_mmu_local_memory_range_lower_mag_v(range);
26 u32 scale = fb_mmu_local_memory_range_lower_scale_v(range);
27 u32 ecc = fb_mmu_local_memory_range_ecc_mode_v(range);
28 size_t bytes = ((size_t)mag << scale) * SZ_1M;
29
30 if (ecc)
31 bytes = bytes / 16 * 15;
32
33 return bytes;
34}
35
36void gv100_init_mm(struct gpu_ops *gops)
37{
38 gv11b_init_mm(gops);
39 gops->mm.get_vidmem_size = gv100_mm_get_vidmem_size;
40 gops->mm.get_physical_addr_bits = NULL;
41}
diff --git a/drivers/gpu/nvgpu/gv100/mm_gv100.h b/drivers/gpu/nvgpu/gv100/mm_gv100.h
new file mode 100644
index 00000000..ff1bc3df
--- /dev/null
+++ b/drivers/gpu/nvgpu/gv100/mm_gv100.h
@@ -0,0 +1,23 @@
1/*
2 * GV100 memory management
3 *
4 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#ifndef MM_GV100_H
17#define MM_GV100_H
18
19struct gpu_ops;
20
21void gv100_init_mm(struct gpu_ops *gops);
22
23#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h
new file mode 100644
index 00000000..c95d5af4
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h
@@ -0,0 +1,217 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_bus_gv100_h_
51#define _hw_bus_gv100_h_
52
53static inline u32 bus_bar0_window_r(void)
54{
55 return 0x00001700;
56}
57static inline u32 bus_bar0_window_base_f(u32 v)
58{
59 return (v & 0xffffff) << 0;
60}
61static inline u32 bus_bar0_window_target_vid_mem_f(void)
62{
63 return 0x0;
64}
65static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void)
66{
67 return 0x2000000;
68}
69static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void)
70{
71 return 0x3000000;
72}
73static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void)
74{
75 return 0x00000010;
76}
77static inline u32 bus_bar1_block_r(void)
78{
79 return 0x00001704;
80}
81static inline u32 bus_bar1_block_ptr_f(u32 v)
82{
83 return (v & 0xfffffff) << 0;
84}
85static inline u32 bus_bar1_block_target_vid_mem_f(void)
86{
87 return 0x0;
88}
89static inline u32 bus_bar1_block_target_sys_mem_coh_f(void)
90{
91 return 0x20000000;
92}
93static inline u32 bus_bar1_block_target_sys_mem_ncoh_f(void)
94{
95 return 0x30000000;
96}
97static inline u32 bus_bar1_block_mode_virtual_f(void)
98{
99 return 0x80000000;
100}
101static inline u32 bus_bar2_block_r(void)
102{
103 return 0x00001714;
104}
105static inline u32 bus_bar2_block_ptr_f(u32 v)
106{
107 return (v & 0xfffffff) << 0;
108}
109static inline u32 bus_bar2_block_target_vid_mem_f(void)
110{
111 return 0x0;
112}
113static inline u32 bus_bar2_block_target_sys_mem_coh_f(void)
114{
115 return 0x20000000;
116}
117static inline u32 bus_bar2_block_target_sys_mem_ncoh_f(void)
118{
119 return 0x30000000;
120}
121static inline u32 bus_bar2_block_mode_virtual_f(void)
122{
123 return 0x80000000;
124}
125static inline u32 bus_bar1_block_ptr_shift_v(void)
126{
127 return 0x0000000c;
128}
129static inline u32 bus_bar2_block_ptr_shift_v(void)
130{
131 return 0x0000000c;
132}
133static inline u32 bus_bind_status_r(void)
134{
135 return 0x00001710;
136}
137static inline u32 bus_bind_status_bar1_pending_v(u32 r)
138{
139 return (r >> 0) & 0x1;
140}
141static inline u32 bus_bind_status_bar1_pending_empty_f(void)
142{
143 return 0x0;
144}
145static inline u32 bus_bind_status_bar1_pending_busy_f(void)
146{
147 return 0x1;
148}
149static inline u32 bus_bind_status_bar1_outstanding_v(u32 r)
150{
151 return (r >> 1) & 0x1;
152}
153static inline u32 bus_bind_status_bar1_outstanding_false_f(void)
154{
155 return 0x0;
156}
157static inline u32 bus_bind_status_bar1_outstanding_true_f(void)
158{
159 return 0x2;
160}
161static inline u32 bus_bind_status_bar2_pending_v(u32 r)
162{
163 return (r >> 2) & 0x1;
164}
165static inline u32 bus_bind_status_bar2_pending_empty_f(void)
166{
167 return 0x0;
168}
169static inline u32 bus_bind_status_bar2_pending_busy_f(void)
170{
171 return 0x4;
172}
173static inline u32 bus_bind_status_bar2_outstanding_v(u32 r)
174{
175 return (r >> 3) & 0x1;
176}
177static inline u32 bus_bind_status_bar2_outstanding_false_f(void)
178{
179 return 0x0;
180}
181static inline u32 bus_bind_status_bar2_outstanding_true_f(void)
182{
183 return 0x8;
184}
185static inline u32 bus_intr_0_r(void)
186{
187 return 0x00001100;
188}
189static inline u32 bus_intr_0_pri_squash_m(void)
190{
191 return 0x1 << 1;
192}
193static inline u32 bus_intr_0_pri_fecserr_m(void)
194{
195 return 0x1 << 2;
196}
197static inline u32 bus_intr_0_pri_timeout_m(void)
198{
199 return 0x1 << 3;
200}
201static inline u32 bus_intr_en_0_r(void)
202{
203 return 0x00001140;
204}
205static inline u32 bus_intr_en_0_pri_squash_m(void)
206{
207 return 0x1 << 1;
208}
209static inline u32 bus_intr_en_0_pri_fecserr_m(void)
210{
211 return 0x1 << 2;
212}
213static inline u32 bus_intr_en_0_pri_timeout_m(void)
214{
215 return 0x1 << 3;
216}
217#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h
new file mode 100644
index 00000000..f64f542c
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h
@@ -0,0 +1,133 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_ccsr_gv100_h_
51#define _hw_ccsr_gv100_h_
52
53static inline u32 ccsr_channel_inst_r(u32 i)
54{
55 return 0x00800000 + i*8;
56}
57static inline u32 ccsr_channel_inst__size_1_v(void)
58{
59 return 0x00001000;
60}
61static inline u32 ccsr_channel_inst_ptr_f(u32 v)
62{
63 return (v & 0xfffffff) << 0;
64}
65static inline u32 ccsr_channel_inst_target_vid_mem_f(void)
66{
67 return 0x0;
68}
69static inline u32 ccsr_channel_inst_target_sys_mem_coh_f(void)
70{
71 return 0x20000000;
72}
73static inline u32 ccsr_channel_inst_target_sys_mem_ncoh_f(void)
74{
75 return 0x30000000;
76}
77static inline u32 ccsr_channel_inst_bind_false_f(void)
78{
79 return 0x0;
80}
81static inline u32 ccsr_channel_inst_bind_true_f(void)
82{
83 return 0x80000000;
84}
85static inline u32 ccsr_channel_r(u32 i)
86{
87 return 0x00800004 + i*8;
88}
89static inline u32 ccsr_channel__size_1_v(void)
90{
91 return 0x00001000;
92}
93static inline u32 ccsr_channel_enable_v(u32 r)
94{
95 return (r >> 0) & 0x1;
96}
97static inline u32 ccsr_channel_enable_set_f(u32 v)
98{
99 return (v & 0x1) << 10;
100}
101static inline u32 ccsr_channel_enable_set_true_f(void)
102{
103 return 0x400;
104}
105static inline u32 ccsr_channel_enable_clr_true_f(void)
106{
107 return 0x800;
108}
109static inline u32 ccsr_channel_status_v(u32 r)
110{
111 return (r >> 24) & 0xf;
112}
113static inline u32 ccsr_channel_pbdma_faulted_f(u32 v)
114{
115 return (v & 0x1) << 22;
116}
117static inline u32 ccsr_channel_pbdma_faulted_reset_f(void)
118{
119 return 0x400000;
120}
121static inline u32 ccsr_channel_eng_faulted_f(u32 v)
122{
123 return (v & 0x1) << 23;
124}
125static inline u32 ccsr_channel_eng_faulted_reset_f(void)
126{
127 return 0x800000;
128}
129static inline u32 ccsr_channel_busy_v(u32 r)
130{
131 return (r >> 28) & 0x1;
132}
133#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ce_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ce_gv100.h
new file mode 100644
index 00000000..26971f3f
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ce_gv100.h
@@ -0,0 +1,101 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_ce_gv100_h_
51#define _hw_ce_gv100_h_
52
53static inline u32 ce_intr_status_r(u32 i)
54{
55 return 0x00104410 + i*128;
56}
57static inline u32 ce_intr_status_blockpipe_pending_f(void)
58{
59 return 0x1;
60}
61static inline u32 ce_intr_status_blockpipe_reset_f(void)
62{
63 return 0x1;
64}
65static inline u32 ce_intr_status_nonblockpipe_pending_f(void)
66{
67 return 0x2;
68}
69static inline u32 ce_intr_status_nonblockpipe_reset_f(void)
70{
71 return 0x2;
72}
73static inline u32 ce_intr_status_launcherr_pending_f(void)
74{
75 return 0x4;
76}
77static inline u32 ce_intr_status_launcherr_reset_f(void)
78{
79 return 0x4;
80}
81static inline u32 ce_intr_status_invalid_config_pending_f(void)
82{
83 return 0x8;
84}
85static inline u32 ce_intr_status_invalid_config_reset_f(void)
86{
87 return 0x8;
88}
89static inline u32 ce_intr_status_mthd_buffer_fault_pending_f(void)
90{
91 return 0x10;
92}
93static inline u32 ce_intr_status_mthd_buffer_fault_reset_f(void)
94{
95 return 0x10;
96}
97static inline u32 ce_pce_map_r(void)
98{
99 return 0x00104028;
100}
101#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h
new file mode 100644
index 00000000..f5593095
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h
@@ -0,0 +1,449 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_ctxsw_prog_gv100_h_
51#define _hw_ctxsw_prog_gv100_h_
52
53static inline u32 ctxsw_prog_fecs_header_v(void)
54{
55 return 0x00000100;
56}
57static inline u32 ctxsw_prog_main_image_num_gpcs_o(void)
58{
59 return 0x00000008;
60}
61static inline u32 ctxsw_prog_main_image_ctl_o(void)
62{
63 return 0x0000000c;
64}
65static inline u32 ctxsw_prog_main_image_ctl_type_f(u32 v)
66{
67 return (v & 0x3f) << 0;
68}
69static inline u32 ctxsw_prog_main_image_ctl_type_undefined_v(void)
70{
71 return 0x00000000;
72}
73static inline u32 ctxsw_prog_main_image_ctl_type_opengl_v(void)
74{
75 return 0x00000008;
76}
77static inline u32 ctxsw_prog_main_image_ctl_type_dx9_v(void)
78{
79 return 0x00000010;
80}
81static inline u32 ctxsw_prog_main_image_ctl_type_dx10_v(void)
82{
83 return 0x00000011;
84}
85static inline u32 ctxsw_prog_main_image_ctl_type_dx11_v(void)
86{
87 return 0x00000012;
88}
89static inline u32 ctxsw_prog_main_image_ctl_type_compute_v(void)
90{
91 return 0x00000020;
92}
93static inline u32 ctxsw_prog_main_image_ctl_type_per_veid_header_v(void)
94{
95 return 0x00000021;
96}
97static inline u32 ctxsw_prog_main_image_patch_count_o(void)
98{
99 return 0x00000010;
100}
101static inline u32 ctxsw_prog_main_image_context_id_o(void)
102{
103 return 0x000000f0;
104}
105static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void)
106{
107 return 0x00000014;
108}
109static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void)
110{
111 return 0x00000018;
112}
113static inline u32 ctxsw_prog_main_image_zcull_o(void)
114{
115 return 0x0000001c;
116}
117static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void)
118{
119 return 0x00000001;
120}
121static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void)
122{
123 return 0x00000002;
124}
125static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void)
126{
127 return 0x00000020;
128}
129static inline u32 ctxsw_prog_main_image_pm_o(void)
130{
131 return 0x00000028;
132}
133static inline u32 ctxsw_prog_main_image_pm_mode_m(void)
134{
135 return 0x7 << 0;
136}
137static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void)
138{
139 return 0x0;
140}
141static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void)
142{
143 return 0x7 << 3;
144}
145static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void)
146{
147 return 0x8;
148}
149static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void)
150{
151 return 0x0;
152}
153static inline u32 ctxsw_prog_main_image_pm_ptr_o(void)
154{
155 return 0x0000002c;
156}
157static inline u32 ctxsw_prog_main_image_num_save_ops_o(void)
158{
159 return 0x000000f4;
160}
161static inline u32 ctxsw_prog_main_image_num_wfi_save_ops_o(void)
162{
163 return 0x000000d0;
164}
165static inline u32 ctxsw_prog_main_image_num_cta_save_ops_o(void)
166{
167 return 0x000000d4;
168}
169static inline u32 ctxsw_prog_main_image_num_gfxp_save_ops_o(void)
170{
171 return 0x000000d8;
172}
173static inline u32 ctxsw_prog_main_image_num_cilp_save_ops_o(void)
174{
175 return 0x000000dc;
176}
177static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void)
178{
179 return 0x000000f8;
180}
181static inline u32 ctxsw_prog_main_image_zcull_ptr_hi_o(void)
182{
183 return 0x00000060;
184}
185static inline u32 ctxsw_prog_main_image_zcull_ptr_hi_v_f(u32 v)
186{
187 return (v & 0x1ffff) << 0;
188}
189static inline u32 ctxsw_prog_main_image_pm_ptr_hi_o(void)
190{
191 return 0x00000094;
192}
193static inline u32 ctxsw_prog_main_image_full_preemption_ptr_hi_o(void)
194{
195 return 0x00000064;
196}
197static inline u32 ctxsw_prog_main_image_full_preemption_ptr_hi_v_f(u32 v)
198{
199 return (v & 0x1ffff) << 0;
200}
201static inline u32 ctxsw_prog_main_image_full_preemption_ptr_o(void)
202{
203 return 0x00000068;
204}
205static inline u32 ctxsw_prog_main_image_full_preemption_ptr_v_f(u32 v)
206{
207 return (v & 0xffffffff) << 0;
208}
209static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_o(void)
210{
211 return 0x00000070;
212}
213static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_v_f(u32 v)
214{
215 return (v & 0x1ffff) << 0;
216}
217static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_o(void)
218{
219 return 0x00000074;
220}
221static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_v_f(u32 v)
222{
223 return (v & 0xffffffff) << 0;
224}
225static inline u32 ctxsw_prog_main_image_context_buffer_ptr_hi_o(void)
226{
227 return 0x00000078;
228}
229static inline u32 ctxsw_prog_main_image_context_buffer_ptr_hi_v_f(u32 v)
230{
231 return (v & 0x1ffff) << 0;
232}
233static inline u32 ctxsw_prog_main_image_context_buffer_ptr_o(void)
234{
235 return 0x0000007c;
236}
237static inline u32 ctxsw_prog_main_image_context_buffer_ptr_v_f(u32 v)
238{
239 return (v & 0xffffffff) << 0;
240}
241static inline u32 ctxsw_prog_main_image_magic_value_o(void)
242{
243 return 0x000000fc;
244}
245static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void)
246{
247 return 0x600dc0de;
248}
249static inline u32 ctxsw_prog_local_priv_register_ctl_o(void)
250{
251 return 0x0000000c;
252}
253static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r)
254{
255 return (r >> 0) & 0xffff;
256}
257static inline u32 ctxsw_prog_main_image_global_cb_ptr_o(void)
258{
259 return 0x000000b8;
260}
261static inline u32 ctxsw_prog_main_image_global_cb_ptr_v_f(u32 v)
262{
263 return (v & 0xffffffff) << 0;
264}
265static inline u32 ctxsw_prog_main_image_global_cb_ptr_hi_o(void)
266{
267 return 0x000000bc;
268}
269static inline u32 ctxsw_prog_main_image_global_cb_ptr_hi_v_f(u32 v)
270{
271 return (v & 0x1ffff) << 0;
272}
273static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_o(void)
274{
275 return 0x000000c0;
276}
277static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_v_f(u32 v)
278{
279 return (v & 0xffffffff) << 0;
280}
281static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_hi_o(void)
282{
283 return 0x000000c4;
284}
285static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_hi_v_f(u32 v)
286{
287 return (v & 0x1ffff) << 0;
288}
289static inline u32 ctxsw_prog_main_image_control_block_ptr_o(void)
290{
291 return 0x000000c8;
292}
293static inline u32 ctxsw_prog_main_image_control_block_ptr_v_f(u32 v)
294{
295 return (v & 0xffffffff) << 0;
296}
297static inline u32 ctxsw_prog_main_image_control_block_ptr_hi_o(void)
298{
299 return 0x000000cc;
300}
301static inline u32 ctxsw_prog_main_image_control_block_ptr_hi_v_f(u32 v)
302{
303 return (v & 0x1ffff) << 0;
304}
305static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_lo_o(void)
306{
307 return 0x000000e0;
308}
309static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_lo_v_f(u32 v)
310{
311 return (v & 0xffffffff) << 0;
312}
313static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_hi_o(void)
314{
315 return 0x000000e4;
316}
317static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_hi_v_f(u32 v)
318{
319 return (v & 0x1ffff) << 0;
320}
321static inline u32 ctxsw_prog_local_image_ppc_info_o(void)
322{
323 return 0x000000f4;
324}
325static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r)
326{
327 return (r >> 0) & 0xffff;
328}
329static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r)
330{
331 return (r >> 16) & 0xffff;
332}
333static inline u32 ctxsw_prog_local_image_num_tpcs_o(void)
334{
335 return 0x000000f8;
336}
337static inline u32 ctxsw_prog_local_magic_value_o(void)
338{
339 return 0x000000fc;
340}
341static inline u32 ctxsw_prog_local_magic_value_v_value_v(void)
342{
343 return 0xad0becab;
344}
345static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void)
346{
347 return 0x000000ec;
348}
349static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r)
350{
351 return (r >> 0) & 0xffff;
352}
353static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r)
354{
355 return (r >> 16) & 0xff;
356}
357static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void)
358{
359 return 0x00000100;
360}
361static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void)
362{
363 return 0x00000004;
364}
365static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void)
366{
367 return 0x00000000;
368}
369static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void)
370{
371 return 0x00000002;
372}
373static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void)
374{
375 return 0x000000a0;
376}
377static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void)
378{
379 return 2;
380}
381static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v)
382{
383 return (v & 0x3) << 0;
384}
385static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void)
386{
387 return 0x3 << 0;
388}
389static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r)
390{
391 return (r >> 0) & 0x3;
392}
393static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void)
394{
395 return 0x0;
396}
397static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void)
398{
399 return 0x2;
400}
401static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void)
402{
403 return 0x000000a4;
404}
405static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void)
406{
407 return 0x000000a8;
408}
409static inline u32 ctxsw_prog_main_image_misc_options_o(void)
410{
411 return 0x0000003c;
412}
413static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void)
414{
415 return 0x1 << 3;
416}
417static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void)
418{
419 return 0x0;
420}
421static inline u32 ctxsw_prog_main_image_graphics_preemption_options_o(void)
422{
423 return 0x00000080;
424}
425static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_f(u32 v)
426{
427 return (v & 0x3) << 0;
428}
429static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f(void)
430{
431 return 0x1;
432}
433static inline u32 ctxsw_prog_main_image_compute_preemption_options_o(void)
434{
435 return 0x00000084;
436}
437static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_f(u32 v)
438{
439 return (v & 0x3) << 0;
440}
441static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cta_f(void)
442{
443 return 0x1;
444}
445static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cilp_f(void)
446{
447 return 0x2;
448}
449#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h
new file mode 100644
index 00000000..ce726633
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h
@@ -0,0 +1,1469 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_fb_gv100_h_
51#define _hw_fb_gv100_h_
52
53static inline u32 fb_fbhub_num_active_ltcs_r(void)
54{
55 return 0x00100800;
56}
57static inline u32 fb_mmu_ctrl_r(void)
58{
59 return 0x00100c80;
60}
61static inline u32 fb_mmu_ctrl_vm_pg_size_f(u32 v)
62{
63 return (v & 0x1) << 0;
64}
65static inline u32 fb_mmu_ctrl_vm_pg_size_128kb_f(void)
66{
67 return 0x0;
68}
69static inline u32 fb_mmu_ctrl_vm_pg_size_64kb_f(void)
70{
71 return 0x1;
72}
73static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r)
74{
75 return (r >> 15) & 0x1;
76}
77static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void)
78{
79 return 0x0;
80}
81static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r)
82{
83 return (r >> 16) & 0xff;
84}
85static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_v(u32 r)
86{
87 return (r >> 11) & 0x1;
88}
89static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_true_f(void)
90{
91 return 0x800;
92}
93static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_false_f(void)
94{
95 return 0x0;
96}
97static inline u32 fb_priv_mmu_phy_secure_r(void)
98{
99 return 0x00100ce4;
100}
101static inline u32 fb_mmu_invalidate_pdb_r(void)
102{
103 return 0x00100cb8;
104}
105static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void)
106{
107 return 0x0;
108}
109static inline u32 fb_mmu_invalidate_pdb_aperture_sys_mem_f(void)
110{
111 return 0x2;
112}
113static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v)
114{
115 return (v & 0xfffffff) << 4;
116}
117static inline u32 fb_mmu_invalidate_r(void)
118{
119 return 0x00100cbc;
120}
121static inline u32 fb_mmu_invalidate_all_va_true_f(void)
122{
123 return 0x1;
124}
125static inline u32 fb_mmu_invalidate_all_pdb_true_f(void)
126{
127 return 0x2;
128}
129static inline u32 fb_mmu_invalidate_hubtlb_only_s(void)
130{
131 return 1;
132}
133static inline u32 fb_mmu_invalidate_hubtlb_only_f(u32 v)
134{
135 return (v & 0x1) << 2;
136}
137static inline u32 fb_mmu_invalidate_hubtlb_only_m(void)
138{
139 return 0x1 << 2;
140}
141static inline u32 fb_mmu_invalidate_hubtlb_only_v(u32 r)
142{
143 return (r >> 2) & 0x1;
144}
145static inline u32 fb_mmu_invalidate_hubtlb_only_true_f(void)
146{
147 return 0x4;
148}
149static inline u32 fb_mmu_invalidate_replay_s(void)
150{
151 return 3;
152}
153static inline u32 fb_mmu_invalidate_replay_f(u32 v)
154{
155 return (v & 0x7) << 3;
156}
157static inline u32 fb_mmu_invalidate_replay_m(void)
158{
159 return 0x7 << 3;
160}
161static inline u32 fb_mmu_invalidate_replay_v(u32 r)
162{
163 return (r >> 3) & 0x7;
164}
165static inline u32 fb_mmu_invalidate_replay_none_f(void)
166{
167 return 0x0;
168}
169static inline u32 fb_mmu_invalidate_replay_start_f(void)
170{
171 return 0x8;
172}
173static inline u32 fb_mmu_invalidate_replay_start_ack_all_f(void)
174{
175 return 0x10;
176}
177static inline u32 fb_mmu_invalidate_replay_cancel_global_f(void)
178{
179 return 0x20;
180}
181static inline u32 fb_mmu_invalidate_sys_membar_s(void)
182{
183 return 1;
184}
185static inline u32 fb_mmu_invalidate_sys_membar_f(u32 v)
186{
187 return (v & 0x1) << 6;
188}
189static inline u32 fb_mmu_invalidate_sys_membar_m(void)
190{
191 return 0x1 << 6;
192}
193static inline u32 fb_mmu_invalidate_sys_membar_v(u32 r)
194{
195 return (r >> 6) & 0x1;
196}
197static inline u32 fb_mmu_invalidate_sys_membar_true_f(void)
198{
199 return 0x40;
200}
201static inline u32 fb_mmu_invalidate_ack_s(void)
202{
203 return 2;
204}
205static inline u32 fb_mmu_invalidate_ack_f(u32 v)
206{
207 return (v & 0x3) << 7;
208}
209static inline u32 fb_mmu_invalidate_ack_m(void)
210{
211 return 0x3 << 7;
212}
213static inline u32 fb_mmu_invalidate_ack_v(u32 r)
214{
215 return (r >> 7) & 0x3;
216}
217static inline u32 fb_mmu_invalidate_ack_ack_none_required_f(void)
218{
219 return 0x0;
220}
221static inline u32 fb_mmu_invalidate_ack_ack_intranode_f(void)
222{
223 return 0x100;
224}
225static inline u32 fb_mmu_invalidate_ack_ack_globally_f(void)
226{
227 return 0x80;
228}
229static inline u32 fb_mmu_invalidate_cancel_client_id_s(void)
230{
231 return 6;
232}
233static inline u32 fb_mmu_invalidate_cancel_client_id_f(u32 v)
234{
235 return (v & 0x3f) << 9;
236}
237static inline u32 fb_mmu_invalidate_cancel_client_id_m(void)
238{
239 return 0x3f << 9;
240}
241static inline u32 fb_mmu_invalidate_cancel_client_id_v(u32 r)
242{
243 return (r >> 9) & 0x3f;
244}
245static inline u32 fb_mmu_invalidate_cancel_gpc_id_s(void)
246{
247 return 5;
248}
249static inline u32 fb_mmu_invalidate_cancel_gpc_id_f(u32 v)
250{
251 return (v & 0x1f) << 15;
252}
253static inline u32 fb_mmu_invalidate_cancel_gpc_id_m(void)
254{
255 return 0x1f << 15;
256}
257static inline u32 fb_mmu_invalidate_cancel_gpc_id_v(u32 r)
258{
259 return (r >> 15) & 0x1f;
260}
261static inline u32 fb_mmu_invalidate_cancel_client_type_s(void)
262{
263 return 1;
264}
265static inline u32 fb_mmu_invalidate_cancel_client_type_f(u32 v)
266{
267 return (v & 0x1) << 20;
268}
269static inline u32 fb_mmu_invalidate_cancel_client_type_m(void)
270{
271 return 0x1 << 20;
272}
273static inline u32 fb_mmu_invalidate_cancel_client_type_v(u32 r)
274{
275 return (r >> 20) & 0x1;
276}
277static inline u32 fb_mmu_invalidate_cancel_client_type_gpc_f(void)
278{
279 return 0x0;
280}
281static inline u32 fb_mmu_invalidate_cancel_client_type_hub_f(void)
282{
283 return 0x100000;
284}
285static inline u32 fb_mmu_invalidate_cancel_cache_level_s(void)
286{
287 return 3;
288}
289static inline u32 fb_mmu_invalidate_cancel_cache_level_f(u32 v)
290{
291 return (v & 0x7) << 24;
292}
293static inline u32 fb_mmu_invalidate_cancel_cache_level_m(void)
294{
295 return 0x7 << 24;
296}
297static inline u32 fb_mmu_invalidate_cancel_cache_level_v(u32 r)
298{
299 return (r >> 24) & 0x7;
300}
301static inline u32 fb_mmu_invalidate_cancel_cache_level_all_f(void)
302{
303 return 0x0;
304}
305static inline u32 fb_mmu_invalidate_cancel_cache_level_pte_only_f(void)
306{
307 return 0x1000000;
308}
309static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde0_f(void)
310{
311 return 0x2000000;
312}
313static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde1_f(void)
314{
315 return 0x3000000;
316}
317static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde2_f(void)
318{
319 return 0x4000000;
320}
321static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde3_f(void)
322{
323 return 0x5000000;
324}
325static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde4_f(void)
326{
327 return 0x6000000;
328}
329static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde5_f(void)
330{
331 return 0x7000000;
332}
333static inline u32 fb_mmu_invalidate_trigger_s(void)
334{
335 return 1;
336}
337static inline u32 fb_mmu_invalidate_trigger_f(u32 v)
338{
339 return (v & 0x1) << 31;
340}
341static inline u32 fb_mmu_invalidate_trigger_m(void)
342{
343 return 0x1 << 31;
344}
345static inline u32 fb_mmu_invalidate_trigger_v(u32 r)
346{
347 return (r >> 31) & 0x1;
348}
349static inline u32 fb_mmu_invalidate_trigger_true_f(void)
350{
351 return 0x80000000;
352}
353static inline u32 fb_mmu_debug_wr_r(void)
354{
355 return 0x00100cc8;
356}
357static inline u32 fb_mmu_debug_wr_aperture_s(void)
358{
359 return 2;
360}
361static inline u32 fb_mmu_debug_wr_aperture_f(u32 v)
362{
363 return (v & 0x3) << 0;
364}
365static inline u32 fb_mmu_debug_wr_aperture_m(void)
366{
367 return 0x3 << 0;
368}
369static inline u32 fb_mmu_debug_wr_aperture_v(u32 r)
370{
371 return (r >> 0) & 0x3;
372}
373static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void)
374{
375 return 0x0;
376}
377static inline u32 fb_mmu_debug_wr_aperture_sys_mem_coh_f(void)
378{
379 return 0x2;
380}
381static inline u32 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(void)
382{
383 return 0x3;
384}
385static inline u32 fb_mmu_debug_wr_vol_false_f(void)
386{
387 return 0x0;
388}
389static inline u32 fb_mmu_debug_wr_vol_true_v(void)
390{
391 return 0x00000001;
392}
393static inline u32 fb_mmu_debug_wr_vol_true_f(void)
394{
395 return 0x4;
396}
397static inline u32 fb_mmu_debug_wr_addr_f(u32 v)
398{
399 return (v & 0xfffffff) << 4;
400}
401static inline u32 fb_mmu_debug_wr_addr_alignment_v(void)
402{
403 return 0x0000000c;
404}
405static inline u32 fb_mmu_debug_rd_r(void)
406{
407 return 0x00100ccc;
408}
409static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void)
410{
411 return 0x0;
412}
413static inline u32 fb_mmu_debug_rd_aperture_sys_mem_coh_f(void)
414{
415 return 0x2;
416}
417static inline u32 fb_mmu_debug_rd_aperture_sys_mem_ncoh_f(void)
418{
419 return 0x3;
420}
421static inline u32 fb_mmu_debug_rd_vol_false_f(void)
422{
423 return 0x0;
424}
425static inline u32 fb_mmu_debug_rd_addr_f(u32 v)
426{
427 return (v & 0xfffffff) << 4;
428}
429static inline u32 fb_mmu_debug_rd_addr_alignment_v(void)
430{
431 return 0x0000000c;
432}
433static inline u32 fb_mmu_debug_ctrl_r(void)
434{
435 return 0x00100cc4;
436}
437static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r)
438{
439 return (r >> 16) & 0x1;
440}
441static inline u32 fb_mmu_debug_ctrl_debug_m(void)
442{
443 return 0x1 << 16;
444}
445static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void)
446{
447 return 0x00000001;
448}
449static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void)
450{
451 return 0x00000000;
452}
453static inline u32 fb_mmu_vpr_info_r(void)
454{
455 return 0x00100cd0;
456}
457static inline u32 fb_mmu_vpr_info_fetch_v(u32 r)
458{
459 return (r >> 2) & 0x1;
460}
461static inline u32 fb_mmu_vpr_info_fetch_false_v(void)
462{
463 return 0x00000000;
464}
465static inline u32 fb_mmu_vpr_info_fetch_true_v(void)
466{
467 return 0x00000001;
468}
469static inline u32 fb_niso_flush_sysmem_addr_r(void)
470{
471 return 0x00100c10;
472}
473static inline u32 fb_niso_intr_r(void)
474{
475 return 0x00100a20;
476}
477static inline u32 fb_niso_intr_hub_access_counter_notify_m(void)
478{
479 return 0x1 << 0;
480}
481static inline u32 fb_niso_intr_hub_access_counter_notify_pending_f(void)
482{
483 return 0x1;
484}
485static inline u32 fb_niso_intr_hub_access_counter_error_m(void)
486{
487 return 0x1 << 1;
488}
489static inline u32 fb_niso_intr_hub_access_counter_error_pending_f(void)
490{
491 return 0x2;
492}
493static inline u32 fb_niso_intr_mmu_replayable_fault_notify_m(void)
494{
495 return 0x1 << 27;
496}
497static inline u32 fb_niso_intr_mmu_replayable_fault_notify_pending_f(void)
498{
499 return 0x8000000;
500}
501static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_m(void)
502{
503 return 0x1 << 28;
504}
505static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_pending_f(void)
506{
507 return 0x10000000;
508}
509static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_m(void)
510{
511 return 0x1 << 29;
512}
513static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_pending_f(void)
514{
515 return 0x20000000;
516}
517static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_m(void)
518{
519 return 0x1 << 30;
520}
521static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_pending_f(void)
522{
523 return 0x40000000;
524}
525static inline u32 fb_niso_intr_mmu_other_fault_notify_m(void)
526{
527 return 0x1 << 31;
528}
529static inline u32 fb_niso_intr_mmu_other_fault_notify_pending_f(void)
530{
531 return 0x80000000;
532}
533static inline u32 fb_niso_intr_en_r(u32 i)
534{
535 return 0x00100a24 + i*4;
536}
537static inline u32 fb_niso_intr_en__size_1_v(void)
538{
539 return 0x00000002;
540}
541static inline u32 fb_niso_intr_en_hub_access_counter_notify_f(u32 v)
542{
543 return (v & 0x1) << 0;
544}
545static inline u32 fb_niso_intr_en_hub_access_counter_notify_enabled_f(void)
546{
547 return 0x1;
548}
549static inline u32 fb_niso_intr_en_hub_access_counter_error_f(u32 v)
550{
551 return (v & 0x1) << 1;
552}
553static inline u32 fb_niso_intr_en_hub_access_counter_error_enabled_f(void)
554{
555 return 0x2;
556}
557static inline u32 fb_niso_intr_en_mmu_replayable_fault_notify_f(u32 v)
558{
559 return (v & 0x1) << 27;
560}
561static inline u32 fb_niso_intr_en_mmu_replayable_fault_notify_enabled_f(void)
562{
563 return 0x8000000;
564}
565static inline u32 fb_niso_intr_en_mmu_replayable_fault_overflow_f(u32 v)
566{
567 return (v & 0x1) << 28;
568}
569static inline u32 fb_niso_intr_en_mmu_replayable_fault_overflow_enabled_f(void)
570{
571 return 0x10000000;
572}
573static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_notify_f(u32 v)
574{
575 return (v & 0x1) << 29;
576}
577static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_notify_enabled_f(void)
578{
579 return 0x20000000;
580}
581static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_overflow_f(u32 v)
582{
583 return (v & 0x1) << 30;
584}
585static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_overflow_enabled_f(void)
586{
587 return 0x40000000;
588}
589static inline u32 fb_niso_intr_en_mmu_other_fault_notify_f(u32 v)
590{
591 return (v & 0x1) << 31;
592}
593static inline u32 fb_niso_intr_en_mmu_other_fault_notify_enabled_f(void)
594{
595 return 0x80000000;
596}
597static inline u32 fb_niso_intr_en_set_r(u32 i)
598{
599 return 0x00100a2c + i*4;
600}
601static inline u32 fb_niso_intr_en_set__size_1_v(void)
602{
603 return 0x00000002;
604}
605static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_m(void)
606{
607 return 0x1 << 0;
608}
609static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_set_f(void)
610{
611 return 0x1;
612}
613static inline u32 fb_niso_intr_en_set_hub_access_counter_error_m(void)
614{
615 return 0x1 << 1;
616}
617static inline u32 fb_niso_intr_en_set_hub_access_counter_error_set_f(void)
618{
619 return 0x2;
620}
621static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_m(void)
622{
623 return 0x1 << 27;
624}
625static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_set_f(void)
626{
627 return 0x8000000;
628}
629static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_m(void)
630{
631 return 0x1 << 28;
632}
633static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_set_f(void)
634{
635 return 0x10000000;
636}
637static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_m(void)
638{
639 return 0x1 << 29;
640}
641static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_set_f(void)
642{
643 return 0x20000000;
644}
645static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_m(void)
646{
647 return 0x1 << 30;
648}
649static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_set_f(void)
650{
651 return 0x40000000;
652}
653static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_m(void)
654{
655 return 0x1 << 31;
656}
657static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_set_f(void)
658{
659 return 0x80000000;
660}
661static inline u32 fb_niso_intr_en_clr_r(u32 i)
662{
663 return 0x00100a34 + i*4;
664}
665static inline u32 fb_niso_intr_en_clr__size_1_v(void)
666{
667 return 0x00000002;
668}
669static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_m(void)
670{
671 return 0x1 << 0;
672}
673static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_set_f(void)
674{
675 return 0x1;
676}
677static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_m(void)
678{
679 return 0x1 << 1;
680}
681static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_set_f(void)
682{
683 return 0x2;
684}
685static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_m(void)
686{
687 return 0x1 << 27;
688}
689static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_set_f(void)
690{
691 return 0x8000000;
692}
693static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_m(void)
694{
695 return 0x1 << 28;
696}
697static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_set_f(void)
698{
699 return 0x10000000;
700}
701static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_m(void)
702{
703 return 0x1 << 29;
704}
705static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_set_f(void)
706{
707 return 0x20000000;
708}
709static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_m(void)
710{
711 return 0x1 << 30;
712}
713static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_set_f(void)
714{
715 return 0x40000000;
716}
717static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_m(void)
718{
719 return 0x1 << 31;
720}
721static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_set_f(void)
722{
723 return 0x80000000;
724}
725static inline u32 fb_niso_intr_en_clr_mmu_non_replay_fault_buffer_v(void)
726{
727 return 0x00000000;
728}
729static inline u32 fb_niso_intr_en_clr_mmu_replay_fault_buffer_v(void)
730{
731 return 0x00000001;
732}
733static inline u32 fb_mmu_fault_buffer_lo_r(u32 i)
734{
735 return 0x00100e24 + i*20;
736}
737static inline u32 fb_mmu_fault_buffer_lo__size_1_v(void)
738{
739 return 0x00000002;
740}
741static inline u32 fb_mmu_fault_buffer_lo_addr_mode_f(u32 v)
742{
743 return (v & 0x1) << 0;
744}
745static inline u32 fb_mmu_fault_buffer_lo_addr_mode_v(u32 r)
746{
747 return (r >> 0) & 0x1;
748}
749static inline u32 fb_mmu_fault_buffer_lo_addr_mode_virtual_v(void)
750{
751 return 0x00000000;
752}
753static inline u32 fb_mmu_fault_buffer_lo_addr_mode_virtual_f(void)
754{
755 return 0x0;
756}
757static inline u32 fb_mmu_fault_buffer_lo_addr_mode_physical_v(void)
758{
759 return 0x00000001;
760}
761static inline u32 fb_mmu_fault_buffer_lo_addr_mode_physical_f(void)
762{
763 return 0x1;
764}
765static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_f(u32 v)
766{
767 return (v & 0x3) << 1;
768}
769static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_v(u32 r)
770{
771 return (r >> 1) & 0x3;
772}
773static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_coh_v(void)
774{
775 return 0x00000002;
776}
777static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_coh_f(void)
778{
779 return 0x4;
780}
781static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_nocoh_v(void)
782{
783 return 0x00000003;
784}
785static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_nocoh_f(void)
786{
787 return 0x6;
788}
789static inline u32 fb_mmu_fault_buffer_lo_phys_vol_f(u32 v)
790{
791 return (v & 0x1) << 3;
792}
793static inline u32 fb_mmu_fault_buffer_lo_phys_vol_v(u32 r)
794{
795 return (r >> 3) & 0x1;
796}
797static inline u32 fb_mmu_fault_buffer_lo_addr_f(u32 v)
798{
799 return (v & 0xfffff) << 12;
800}
801static inline u32 fb_mmu_fault_buffer_lo_addr_v(u32 r)
802{
803 return (r >> 12) & 0xfffff;
804}
805static inline u32 fb_mmu_fault_buffer_hi_r(u32 i)
806{
807 return 0x00100e28 + i*20;
808}
809static inline u32 fb_mmu_fault_buffer_hi__size_1_v(void)
810{
811 return 0x00000002;
812}
813static inline u32 fb_mmu_fault_buffer_hi_addr_f(u32 v)
814{
815 return (v & 0xffffffff) << 0;
816}
817static inline u32 fb_mmu_fault_buffer_hi_addr_v(u32 r)
818{
819 return (r >> 0) & 0xffffffff;
820}
821static inline u32 fb_mmu_fault_buffer_get_r(u32 i)
822{
823 return 0x00100e2c + i*20;
824}
825static inline u32 fb_mmu_fault_buffer_get__size_1_v(void)
826{
827 return 0x00000002;
828}
829static inline u32 fb_mmu_fault_buffer_get_ptr_f(u32 v)
830{
831 return (v & 0xfffff) << 0;
832}
833static inline u32 fb_mmu_fault_buffer_get_ptr_m(void)
834{
835 return 0xfffff << 0;
836}
837static inline u32 fb_mmu_fault_buffer_get_ptr_v(u32 r)
838{
839 return (r >> 0) & 0xfffff;
840}
841static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_f(u32 v)
842{
843 return (v & 0x1) << 30;
844}
845static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_m(void)
846{
847 return 0x1 << 30;
848}
849static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_clear_v(void)
850{
851 return 0x00000001;
852}
853static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_clear_f(void)
854{
855 return 0x40000000;
856}
857static inline u32 fb_mmu_fault_buffer_get_overflow_f(u32 v)
858{
859 return (v & 0x1) << 31;
860}
861static inline u32 fb_mmu_fault_buffer_get_overflow_m(void)
862{
863 return 0x1 << 31;
864}
865static inline u32 fb_mmu_fault_buffer_get_overflow_clear_v(void)
866{
867 return 0x00000001;
868}
869static inline u32 fb_mmu_fault_buffer_get_overflow_clear_f(void)
870{
871 return 0x80000000;
872}
873static inline u32 fb_mmu_fault_buffer_put_r(u32 i)
874{
875 return 0x00100e30 + i*20;
876}
877static inline u32 fb_mmu_fault_buffer_put__size_1_v(void)
878{
879 return 0x00000002;
880}
881static inline u32 fb_mmu_fault_buffer_put_ptr_f(u32 v)
882{
883 return (v & 0xfffff) << 0;
884}
885static inline u32 fb_mmu_fault_buffer_put_ptr_v(u32 r)
886{
887 return (r >> 0) & 0xfffff;
888}
889static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_f(u32 v)
890{
891 return (v & 0x1) << 30;
892}
893static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_v(u32 r)
894{
895 return (r >> 30) & 0x1;
896}
897static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_yes_v(void)
898{
899 return 0x00000001;
900}
901static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_yes_f(void)
902{
903 return 0x40000000;
904}
905static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_no_v(void)
906{
907 return 0x00000000;
908}
909static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_no_f(void)
910{
911 return 0x0;
912}
913static inline u32 fb_mmu_fault_buffer_put_overflow_f(u32 v)
914{
915 return (v & 0x1) << 31;
916}
917static inline u32 fb_mmu_fault_buffer_put_overflow_v(u32 r)
918{
919 return (r >> 31) & 0x1;
920}
921static inline u32 fb_mmu_fault_buffer_put_overflow_yes_v(void)
922{
923 return 0x00000001;
924}
925static inline u32 fb_mmu_fault_buffer_put_overflow_yes_f(void)
926{
927 return 0x80000000;
928}
929static inline u32 fb_mmu_fault_buffer_size_r(u32 i)
930{
931 return 0x00100e34 + i*20;
932}
933static inline u32 fb_mmu_fault_buffer_size__size_1_v(void)
934{
935 return 0x00000002;
936}
937static inline u32 fb_mmu_fault_buffer_size_val_f(u32 v)
938{
939 return (v & 0xfffff) << 0;
940}
941static inline u32 fb_mmu_fault_buffer_size_val_v(u32 r)
942{
943 return (r >> 0) & 0xfffff;
944}
945static inline u32 fb_mmu_fault_buffer_size_overflow_intr_f(u32 v)
946{
947 return (v & 0x1) << 29;
948}
949static inline u32 fb_mmu_fault_buffer_size_overflow_intr_v(u32 r)
950{
951 return (r >> 29) & 0x1;
952}
953static inline u32 fb_mmu_fault_buffer_size_overflow_intr_enable_v(void)
954{
955 return 0x00000001;
956}
957static inline u32 fb_mmu_fault_buffer_size_overflow_intr_enable_f(void)
958{
959 return 0x20000000;
960}
961static inline u32 fb_mmu_fault_buffer_size_set_default_f(u32 v)
962{
963 return (v & 0x1) << 30;
964}
965static inline u32 fb_mmu_fault_buffer_size_set_default_v(u32 r)
966{
967 return (r >> 30) & 0x1;
968}
969static inline u32 fb_mmu_fault_buffer_size_set_default_yes_v(void)
970{
971 return 0x00000001;
972}
973static inline u32 fb_mmu_fault_buffer_size_set_default_yes_f(void)
974{
975 return 0x40000000;
976}
977static inline u32 fb_mmu_fault_buffer_size_enable_f(u32 v)
978{
979 return (v & 0x1) << 31;
980}
981static inline u32 fb_mmu_fault_buffer_size_enable_m(void)
982{
983 return 0x1 << 31;
984}
985static inline u32 fb_mmu_fault_buffer_size_enable_v(u32 r)
986{
987 return (r >> 31) & 0x1;
988}
989static inline u32 fb_mmu_fault_buffer_size_enable_true_v(void)
990{
991 return 0x00000001;
992}
993static inline u32 fb_mmu_fault_buffer_size_enable_true_f(void)
994{
995 return 0x80000000;
996}
997static inline u32 fb_mmu_fault_addr_lo_r(void)
998{
999 return 0x00100e4c;
1000}
1001static inline u32 fb_mmu_fault_addr_lo_phys_aperture_f(u32 v)
1002{
1003 return (v & 0x3) << 0;
1004}
1005static inline u32 fb_mmu_fault_addr_lo_phys_aperture_v(u32 r)
1006{
1007 return (r >> 0) & 0x3;
1008}
1009static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_coh_v(void)
1010{
1011 return 0x00000002;
1012}
1013static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_coh_f(void)
1014{
1015 return 0x2;
1016}
1017static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_nocoh_v(void)
1018{
1019 return 0x00000003;
1020}
1021static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_nocoh_f(void)
1022{
1023 return 0x3;
1024}
1025static inline u32 fb_mmu_fault_addr_lo_addr_f(u32 v)
1026{
1027 return (v & 0xfffff) << 12;
1028}
1029static inline u32 fb_mmu_fault_addr_lo_addr_v(u32 r)
1030{
1031 return (r >> 12) & 0xfffff;
1032}
1033static inline u32 fb_mmu_fault_addr_hi_r(void)
1034{
1035 return 0x00100e50;
1036}
1037static inline u32 fb_mmu_fault_addr_hi_addr_f(u32 v)
1038{
1039 return (v & 0xffffffff) << 0;
1040}
1041static inline u32 fb_mmu_fault_addr_hi_addr_v(u32 r)
1042{
1043 return (r >> 0) & 0xffffffff;
1044}
1045static inline u32 fb_mmu_fault_inst_lo_r(void)
1046{
1047 return 0x00100e54;
1048}
1049static inline u32 fb_mmu_fault_inst_lo_engine_id_v(u32 r)
1050{
1051 return (r >> 0) & 0x1ff;
1052}
1053static inline u32 fb_mmu_fault_inst_lo_aperture_v(u32 r)
1054{
1055 return (r >> 10) & 0x3;
1056}
1057static inline u32 fb_mmu_fault_inst_lo_aperture_sys_coh_v(void)
1058{
1059 return 0x00000002;
1060}
1061static inline u32 fb_mmu_fault_inst_lo_aperture_sys_nocoh_v(void)
1062{
1063 return 0x00000003;
1064}
1065static inline u32 fb_mmu_fault_inst_lo_addr_f(u32 v)
1066{
1067 return (v & 0xfffff) << 12;
1068}
1069static inline u32 fb_mmu_fault_inst_lo_addr_v(u32 r)
1070{
1071 return (r >> 12) & 0xfffff;
1072}
1073static inline u32 fb_mmu_fault_inst_hi_r(void)
1074{
1075 return 0x00100e58;
1076}
1077static inline u32 fb_mmu_fault_inst_hi_addr_v(u32 r)
1078{
1079 return (r >> 0) & 0xffffffff;
1080}
1081static inline u32 fb_mmu_fault_info_r(void)
1082{
1083 return 0x00100e5c;
1084}
1085static inline u32 fb_mmu_fault_info_fault_type_v(u32 r)
1086{
1087 return (r >> 0) & 0x1f;
1088}
1089static inline u32 fb_mmu_fault_info_replayable_fault_v(u32 r)
1090{
1091 return (r >> 7) & 0x1;
1092}
1093static inline u32 fb_mmu_fault_info_client_v(u32 r)
1094{
1095 return (r >> 8) & 0x7f;
1096}
1097static inline u32 fb_mmu_fault_info_access_type_v(u32 r)
1098{
1099 return (r >> 16) & 0xf;
1100}
1101static inline u32 fb_mmu_fault_info_client_type_v(u32 r)
1102{
1103 return (r >> 20) & 0x1;
1104}
1105static inline u32 fb_mmu_fault_info_gpc_id_v(u32 r)
1106{
1107 return (r >> 24) & 0x1f;
1108}
1109static inline u32 fb_mmu_fault_info_protected_mode_v(u32 r)
1110{
1111 return (r >> 29) & 0x1;
1112}
1113static inline u32 fb_mmu_fault_info_replayable_fault_en_v(u32 r)
1114{
1115 return (r >> 30) & 0x1;
1116}
1117static inline u32 fb_mmu_fault_info_valid_v(u32 r)
1118{
1119 return (r >> 31) & 0x1;
1120}
1121static inline u32 fb_mmu_fault_status_r(void)
1122{
1123 return 0x00100e60;
1124}
1125static inline u32 fb_mmu_fault_status_dropped_bar1_phys_m(void)
1126{
1127 return 0x1 << 0;
1128}
1129static inline u32 fb_mmu_fault_status_dropped_bar1_phys_set_v(void)
1130{
1131 return 0x00000001;
1132}
1133static inline u32 fb_mmu_fault_status_dropped_bar1_phys_set_f(void)
1134{
1135 return 0x1;
1136}
1137static inline u32 fb_mmu_fault_status_dropped_bar1_phys_clear_v(void)
1138{
1139 return 0x00000001;
1140}
1141static inline u32 fb_mmu_fault_status_dropped_bar1_phys_clear_f(void)
1142{
1143 return 0x1;
1144}
1145static inline u32 fb_mmu_fault_status_dropped_bar1_virt_m(void)
1146{
1147 return 0x1 << 1;
1148}
1149static inline u32 fb_mmu_fault_status_dropped_bar1_virt_set_v(void)
1150{
1151 return 0x00000001;
1152}
1153static inline u32 fb_mmu_fault_status_dropped_bar1_virt_set_f(void)
1154{
1155 return 0x2;
1156}
1157static inline u32 fb_mmu_fault_status_dropped_bar1_virt_clear_v(void)
1158{
1159 return 0x00000001;
1160}
1161static inline u32 fb_mmu_fault_status_dropped_bar1_virt_clear_f(void)
1162{
1163 return 0x2;
1164}
1165static inline u32 fb_mmu_fault_status_dropped_bar2_phys_m(void)
1166{
1167 return 0x1 << 2;
1168}
1169static inline u32 fb_mmu_fault_status_dropped_bar2_phys_set_v(void)
1170{
1171 return 0x00000001;
1172}
1173static inline u32 fb_mmu_fault_status_dropped_bar2_phys_set_f(void)
1174{
1175 return 0x4;
1176}
1177static inline u32 fb_mmu_fault_status_dropped_bar2_phys_clear_v(void)
1178{
1179 return 0x00000001;
1180}
1181static inline u32 fb_mmu_fault_status_dropped_bar2_phys_clear_f(void)
1182{
1183 return 0x4;
1184}
1185static inline u32 fb_mmu_fault_status_dropped_bar2_virt_m(void)
1186{
1187 return 0x1 << 3;
1188}
1189static inline u32 fb_mmu_fault_status_dropped_bar2_virt_set_v(void)
1190{
1191 return 0x00000001;
1192}
1193static inline u32 fb_mmu_fault_status_dropped_bar2_virt_set_f(void)
1194{
1195 return 0x8;
1196}
1197static inline u32 fb_mmu_fault_status_dropped_bar2_virt_clear_v(void)
1198{
1199 return 0x00000001;
1200}
1201static inline u32 fb_mmu_fault_status_dropped_bar2_virt_clear_f(void)
1202{
1203 return 0x8;
1204}
1205static inline u32 fb_mmu_fault_status_dropped_ifb_phys_m(void)
1206{
1207 return 0x1 << 4;
1208}
1209static inline u32 fb_mmu_fault_status_dropped_ifb_phys_set_v(void)
1210{
1211 return 0x00000001;
1212}
1213static inline u32 fb_mmu_fault_status_dropped_ifb_phys_set_f(void)
1214{
1215 return 0x10;
1216}
1217static inline u32 fb_mmu_fault_status_dropped_ifb_phys_clear_v(void)
1218{
1219 return 0x00000001;
1220}
1221static inline u32 fb_mmu_fault_status_dropped_ifb_phys_clear_f(void)
1222{
1223 return 0x10;
1224}
1225static inline u32 fb_mmu_fault_status_dropped_ifb_virt_m(void)
1226{
1227 return 0x1 << 5;
1228}
1229static inline u32 fb_mmu_fault_status_dropped_ifb_virt_set_v(void)
1230{
1231 return 0x00000001;
1232}
1233static inline u32 fb_mmu_fault_status_dropped_ifb_virt_set_f(void)
1234{
1235 return 0x20;
1236}
1237static inline u32 fb_mmu_fault_status_dropped_ifb_virt_clear_v(void)
1238{
1239 return 0x00000001;
1240}
1241static inline u32 fb_mmu_fault_status_dropped_ifb_virt_clear_f(void)
1242{
1243 return 0x20;
1244}
1245static inline u32 fb_mmu_fault_status_dropped_other_phys_m(void)
1246{
1247 return 0x1 << 6;
1248}
1249static inline u32 fb_mmu_fault_status_dropped_other_phys_set_v(void)
1250{
1251 return 0x00000001;
1252}
1253static inline u32 fb_mmu_fault_status_dropped_other_phys_set_f(void)
1254{
1255 return 0x40;
1256}
1257static inline u32 fb_mmu_fault_status_dropped_other_phys_clear_v(void)
1258{
1259 return 0x00000001;
1260}
1261static inline u32 fb_mmu_fault_status_dropped_other_phys_clear_f(void)
1262{
1263 return 0x40;
1264}
1265static inline u32 fb_mmu_fault_status_dropped_other_virt_m(void)
1266{
1267 return 0x1 << 7;
1268}
1269static inline u32 fb_mmu_fault_status_dropped_other_virt_set_v(void)
1270{
1271 return 0x00000001;
1272}
1273static inline u32 fb_mmu_fault_status_dropped_other_virt_set_f(void)
1274{
1275 return 0x80;
1276}
1277static inline u32 fb_mmu_fault_status_dropped_other_virt_clear_v(void)
1278{
1279 return 0x00000001;
1280}
1281static inline u32 fb_mmu_fault_status_dropped_other_virt_clear_f(void)
1282{
1283 return 0x80;
1284}
1285static inline u32 fb_mmu_fault_status_replayable_m(void)
1286{
1287 return 0x1 << 8;
1288}
1289static inline u32 fb_mmu_fault_status_replayable_set_v(void)
1290{
1291 return 0x00000001;
1292}
1293static inline u32 fb_mmu_fault_status_replayable_set_f(void)
1294{
1295 return 0x100;
1296}
1297static inline u32 fb_mmu_fault_status_replayable_reset_f(void)
1298{
1299 return 0x0;
1300}
1301static inline u32 fb_mmu_fault_status_non_replayable_m(void)
1302{
1303 return 0x1 << 9;
1304}
1305static inline u32 fb_mmu_fault_status_non_replayable_set_v(void)
1306{
1307 return 0x00000001;
1308}
1309static inline u32 fb_mmu_fault_status_non_replayable_set_f(void)
1310{
1311 return 0x200;
1312}
1313static inline u32 fb_mmu_fault_status_non_replayable_reset_f(void)
1314{
1315 return 0x0;
1316}
1317static inline u32 fb_mmu_fault_status_replayable_error_m(void)
1318{
1319 return 0x1 << 10;
1320}
1321static inline u32 fb_mmu_fault_status_replayable_error_set_v(void)
1322{
1323 return 0x00000001;
1324}
1325static inline u32 fb_mmu_fault_status_replayable_error_set_f(void)
1326{
1327 return 0x400;
1328}
1329static inline u32 fb_mmu_fault_status_replayable_error_reset_f(void)
1330{
1331 return 0x0;
1332}
1333static inline u32 fb_mmu_fault_status_non_replayable_error_m(void)
1334{
1335 return 0x1 << 11;
1336}
1337static inline u32 fb_mmu_fault_status_non_replayable_error_set_v(void)
1338{
1339 return 0x00000001;
1340}
1341static inline u32 fb_mmu_fault_status_non_replayable_error_set_f(void)
1342{
1343 return 0x800;
1344}
1345static inline u32 fb_mmu_fault_status_non_replayable_error_reset_f(void)
1346{
1347 return 0x0;
1348}
1349static inline u32 fb_mmu_fault_status_replayable_overflow_m(void)
1350{
1351 return 0x1 << 12;
1352}
1353static inline u32 fb_mmu_fault_status_replayable_overflow_set_v(void)
1354{
1355 return 0x00000001;
1356}
1357static inline u32 fb_mmu_fault_status_replayable_overflow_set_f(void)
1358{
1359 return 0x1000;
1360}
1361static inline u32 fb_mmu_fault_status_replayable_overflow_reset_f(void)
1362{
1363 return 0x0;
1364}
1365static inline u32 fb_mmu_fault_status_non_replayable_overflow_m(void)
1366{
1367 return 0x1 << 13;
1368}
1369static inline u32 fb_mmu_fault_status_non_replayable_overflow_set_v(void)
1370{
1371 return 0x00000001;
1372}
1373static inline u32 fb_mmu_fault_status_non_replayable_overflow_set_f(void)
1374{
1375 return 0x2000;
1376}
1377static inline u32 fb_mmu_fault_status_non_replayable_overflow_reset_f(void)
1378{
1379 return 0x0;
1380}
1381static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_m(void)
1382{
1383 return 0x1 << 14;
1384}
1385static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_set_v(void)
1386{
1387 return 0x00000001;
1388}
1389static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_set_f(void)
1390{
1391 return 0x4000;
1392}
1393static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_m(void)
1394{
1395 return 0x1 << 15;
1396}
1397static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_set_v(void)
1398{
1399 return 0x00000001;
1400}
1401static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_set_f(void)
1402{
1403 return 0x8000;
1404}
1405static inline u32 fb_mmu_fault_status_busy_m(void)
1406{
1407 return 0x1 << 30;
1408}
1409static inline u32 fb_mmu_fault_status_busy_true_v(void)
1410{
1411 return 0x00000001;
1412}
1413static inline u32 fb_mmu_fault_status_busy_true_f(void)
1414{
1415 return 0x40000000;
1416}
1417static inline u32 fb_mmu_fault_status_valid_m(void)
1418{
1419 return 0x1 << 31;
1420}
1421static inline u32 fb_mmu_fault_status_valid_set_v(void)
1422{
1423 return 0x00000001;
1424}
1425static inline u32 fb_mmu_fault_status_valid_set_f(void)
1426{
1427 return 0x80000000;
1428}
1429static inline u32 fb_mmu_fault_status_valid_clear_v(void)
1430{
1431 return 0x00000001;
1432}
1433static inline u32 fb_mmu_fault_status_valid_clear_f(void)
1434{
1435 return 0x80000000;
1436}
1437static inline u32 fb_mmu_local_memory_range_r(void)
1438{
1439 return 0x00100ce0;
1440}
1441static inline u32 fb_mmu_local_memory_range_lower_scale_v(u32 r)
1442{
1443 return (r >> 0) & 0xf;
1444}
1445static inline u32 fb_mmu_local_memory_range_lower_mag_v(u32 r)
1446{
1447 return (r >> 4) & 0x3f;
1448}
1449static inline u32 fb_mmu_local_memory_range_ecc_mode_v(u32 r)
1450{
1451 return (r >> 30) & 0x1;
1452}
1453static inline u32 fb_niso_scrub_status_r(void)
1454{
1455 return 0x00100b20;
1456}
1457static inline u32 fb_niso_scrub_status_flag_v(u32 r)
1458{
1459 return (r >> 0) & 0x1;
1460}
1461static inline u32 fb_mmu_priv_level_mask_r(void)
1462{
1463 return 0x00100cdc;
1464}
1465static inline u32 fb_mmu_priv_level_mask_write_violation_m(void)
1466{
1467 return 0x1 << 7;
1468}
1469#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fifo_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fifo_gv100.h
new file mode 100644
index 00000000..9466a695
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fifo_gv100.h
@@ -0,0 +1,545 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_fifo_gv100_h_
51#define _hw_fifo_gv100_h_
52
53static inline u32 fifo_bar1_base_r(void)
54{
55 return 0x00002254;
56}
57static inline u32 fifo_bar1_base_ptr_f(u32 v)
58{
59 return (v & 0xfffffff) << 0;
60}
61static inline u32 fifo_bar1_base_ptr_align_shift_v(void)
62{
63 return 0x0000000c;
64}
65static inline u32 fifo_bar1_base_valid_false_f(void)
66{
67 return 0x0;
68}
69static inline u32 fifo_bar1_base_valid_true_f(void)
70{
71 return 0x10000000;
72}
73static inline u32 fifo_userd_writeback_r(void)
74{
75 return 0x0000225c;
76}
77static inline u32 fifo_userd_writeback_timer_f(u32 v)
78{
79 return (v & 0xff) << 0;
80}
81static inline u32 fifo_userd_writeback_timer_disabled_v(void)
82{
83 return 0x00000000;
84}
85static inline u32 fifo_userd_writeback_timer_shorter_v(void)
86{
87 return 0x00000003;
88}
89static inline u32 fifo_userd_writeback_timer_100us_v(void)
90{
91 return 0x00000064;
92}
93static inline u32 fifo_userd_writeback_timescale_f(u32 v)
94{
95 return (v & 0xf) << 12;
96}
97static inline u32 fifo_userd_writeback_timescale_0_v(void)
98{
99 return 0x00000000;
100}
101static inline u32 fifo_runlist_base_r(void)
102{
103 return 0x00002270;
104}
105static inline u32 fifo_runlist_base_ptr_f(u32 v)
106{
107 return (v & 0xfffffff) << 0;
108}
109static inline u32 fifo_runlist_base_target_vid_mem_f(void)
110{
111 return 0x0;
112}
113static inline u32 fifo_runlist_base_target_sys_mem_coh_f(void)
114{
115 return 0x20000000;
116}
117static inline u32 fifo_runlist_base_target_sys_mem_ncoh_f(void)
118{
119 return 0x30000000;
120}
121static inline u32 fifo_runlist_r(void)
122{
123 return 0x00002274;
124}
125static inline u32 fifo_runlist_engine_f(u32 v)
126{
127 return (v & 0xf) << 20;
128}
129static inline u32 fifo_eng_runlist_base_r(u32 i)
130{
131 return 0x00002280 + i*8;
132}
133static inline u32 fifo_eng_runlist_base__size_1_v(void)
134{
135 return 0x0000000d;
136}
137static inline u32 fifo_eng_runlist_r(u32 i)
138{
139 return 0x00002284 + i*8;
140}
141static inline u32 fifo_eng_runlist__size_1_v(void)
142{
143 return 0x0000000d;
144}
145static inline u32 fifo_eng_runlist_length_f(u32 v)
146{
147 return (v & 0xffff) << 0;
148}
149static inline u32 fifo_eng_runlist_length_max_v(void)
150{
151 return 0x0000ffff;
152}
153static inline u32 fifo_eng_runlist_pending_true_f(void)
154{
155 return 0x100000;
156}
157static inline u32 fifo_pb_timeslice_r(u32 i)
158{
159 return 0x00002350 + i*4;
160}
161static inline u32 fifo_pb_timeslice_timeout_16_f(void)
162{
163 return 0x10;
164}
165static inline u32 fifo_pb_timeslice_timescale_0_f(void)
166{
167 return 0x0;
168}
169static inline u32 fifo_pb_timeslice_enable_true_f(void)
170{
171 return 0x10000000;
172}
173static inline u32 fifo_pbdma_map_r(u32 i)
174{
175 return 0x00002390 + i*4;
176}
177static inline u32 fifo_intr_0_r(void)
178{
179 return 0x00002100;
180}
181static inline u32 fifo_intr_0_bind_error_pending_f(void)
182{
183 return 0x1;
184}
185static inline u32 fifo_intr_0_bind_error_reset_f(void)
186{
187 return 0x1;
188}
189static inline u32 fifo_intr_0_sched_error_pending_f(void)
190{
191 return 0x100;
192}
193static inline u32 fifo_intr_0_sched_error_reset_f(void)
194{
195 return 0x100;
196}
197static inline u32 fifo_intr_0_chsw_error_pending_f(void)
198{
199 return 0x10000;
200}
201static inline u32 fifo_intr_0_chsw_error_reset_f(void)
202{
203 return 0x10000;
204}
205static inline u32 fifo_intr_0_fb_flush_timeout_pending_f(void)
206{
207 return 0x800000;
208}
209static inline u32 fifo_intr_0_fb_flush_timeout_reset_f(void)
210{
211 return 0x800000;
212}
213static inline u32 fifo_intr_0_lb_error_pending_f(void)
214{
215 return 0x1000000;
216}
217static inline u32 fifo_intr_0_lb_error_reset_f(void)
218{
219 return 0x1000000;
220}
221static inline u32 fifo_intr_0_pbdma_intr_pending_f(void)
222{
223 return 0x20000000;
224}
225static inline u32 fifo_intr_0_runlist_event_pending_f(void)
226{
227 return 0x40000000;
228}
229static inline u32 fifo_intr_0_channel_intr_pending_f(void)
230{
231 return 0x80000000;
232}
233static inline u32 fifo_intr_en_0_r(void)
234{
235 return 0x00002140;
236}
237static inline u32 fifo_intr_en_0_sched_error_f(u32 v)
238{
239 return (v & 0x1) << 8;
240}
241static inline u32 fifo_intr_en_0_sched_error_m(void)
242{
243 return 0x1 << 8;
244}
245static inline u32 fifo_intr_en_1_r(void)
246{
247 return 0x00002528;
248}
249static inline u32 fifo_intr_bind_error_r(void)
250{
251 return 0x0000252c;
252}
253static inline u32 fifo_intr_sched_error_r(void)
254{
255 return 0x0000254c;
256}
257static inline u32 fifo_intr_sched_error_code_f(u32 v)
258{
259 return (v & 0xff) << 0;
260}
261static inline u32 fifo_intr_chsw_error_r(void)
262{
263 return 0x0000256c;
264}
265static inline u32 fifo_intr_pbdma_id_r(void)
266{
267 return 0x000025a0;
268}
269static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i)
270{
271 return (v & 0x1) << (0 + i*1);
272}
273static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i)
274{
275 return (r >> (0 + i*1)) & 0x1;
276}
277static inline u32 fifo_intr_pbdma_id_status__size_1_v(void)
278{
279 return 0x0000000e;
280}
281static inline u32 fifo_intr_runlist_r(void)
282{
283 return 0x00002a00;
284}
285static inline u32 fifo_fb_timeout_r(void)
286{
287 return 0x00002a04;
288}
289static inline u32 fifo_fb_timeout_period_m(void)
290{
291 return 0x3fffffff << 0;
292}
293static inline u32 fifo_fb_timeout_period_max_f(void)
294{
295 return 0x3fffffff;
296}
297static inline u32 fifo_fb_timeout_period_init_f(void)
298{
299 return 0x3c00;
300}
301static inline u32 fifo_sched_disable_r(void)
302{
303 return 0x00002630;
304}
305static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i)
306{
307 return (v & 0x1) << (0 + i*1);
308}
309static inline u32 fifo_sched_disable_runlist_m(u32 i)
310{
311 return 0x1 << (0 + i*1);
312}
313static inline u32 fifo_sched_disable_true_v(void)
314{
315 return 0x00000001;
316}
317static inline u32 fifo_runlist_preempt_r(void)
318{
319 return 0x00002638;
320}
321static inline u32 fifo_runlist_preempt_runlist_f(u32 v, u32 i)
322{
323 return (v & 0x1) << (0 + i*1);
324}
325static inline u32 fifo_runlist_preempt_runlist_m(u32 i)
326{
327 return 0x1 << (0 + i*1);
328}
329static inline u32 fifo_runlist_preempt_runlist_pending_v(void)
330{
331 return 0x00000001;
332}
333static inline u32 fifo_preempt_r(void)
334{
335 return 0x00002634;
336}
337static inline u32 fifo_preempt_pending_true_f(void)
338{
339 return 0x100000;
340}
341static inline u32 fifo_preempt_type_channel_f(void)
342{
343 return 0x0;
344}
345static inline u32 fifo_preempt_type_tsg_f(void)
346{
347 return 0x1000000;
348}
349static inline u32 fifo_preempt_chid_f(u32 v)
350{
351 return (v & 0xfff) << 0;
352}
353static inline u32 fifo_preempt_id_f(u32 v)
354{
355 return (v & 0xfff) << 0;
356}
357static inline u32 fifo_engine_status_r(u32 i)
358{
359 return 0x00002640 + i*8;
360}
361static inline u32 fifo_engine_status__size_1_v(void)
362{
363 return 0x0000000f;
364}
365static inline u32 fifo_engine_status_id_v(u32 r)
366{
367 return (r >> 0) & 0xfff;
368}
369static inline u32 fifo_engine_status_id_type_v(u32 r)
370{
371 return (r >> 12) & 0x1;
372}
373static inline u32 fifo_engine_status_id_type_chid_v(void)
374{
375 return 0x00000000;
376}
377static inline u32 fifo_engine_status_id_type_tsgid_v(void)
378{
379 return 0x00000001;
380}
381static inline u32 fifo_engine_status_ctx_status_v(u32 r)
382{
383 return (r >> 13) & 0x7;
384}
385static inline u32 fifo_engine_status_ctx_status_valid_v(void)
386{
387 return 0x00000001;
388}
389static inline u32 fifo_engine_status_ctx_status_ctxsw_load_v(void)
390{
391 return 0x00000005;
392}
393static inline u32 fifo_engine_status_ctx_status_ctxsw_save_v(void)
394{
395 return 0x00000006;
396}
397static inline u32 fifo_engine_status_ctx_status_ctxsw_switch_v(void)
398{
399 return 0x00000007;
400}
401static inline u32 fifo_engine_status_next_id_v(u32 r)
402{
403 return (r >> 16) & 0xfff;
404}
405static inline u32 fifo_engine_status_next_id_type_v(u32 r)
406{
407 return (r >> 28) & 0x1;
408}
409static inline u32 fifo_engine_status_next_id_type_chid_v(void)
410{
411 return 0x00000000;
412}
413static inline u32 fifo_engine_status_eng_reload_v(u32 r)
414{
415 return (r >> 29) & 0x1;
416}
417static inline u32 fifo_engine_status_faulted_v(u32 r)
418{
419 return (r >> 30) & 0x1;
420}
421static inline u32 fifo_engine_status_faulted_true_v(void)
422{
423 return 0x00000001;
424}
425static inline u32 fifo_engine_status_engine_v(u32 r)
426{
427 return (r >> 31) & 0x1;
428}
429static inline u32 fifo_engine_status_engine_idle_v(void)
430{
431 return 0x00000000;
432}
433static inline u32 fifo_engine_status_engine_busy_v(void)
434{
435 return 0x00000001;
436}
437static inline u32 fifo_engine_status_ctxsw_v(u32 r)
438{
439 return (r >> 15) & 0x1;
440}
441static inline u32 fifo_engine_status_ctxsw_in_progress_v(void)
442{
443 return 0x00000001;
444}
445static inline u32 fifo_engine_status_ctxsw_in_progress_f(void)
446{
447 return 0x8000;
448}
449static inline u32 fifo_pbdma_status_r(u32 i)
450{
451 return 0x00003080 + i*4;
452}
453static inline u32 fifo_pbdma_status__size_1_v(void)
454{
455 return 0x0000000e;
456}
457static inline u32 fifo_pbdma_status_id_v(u32 r)
458{
459 return (r >> 0) & 0xfff;
460}
461static inline u32 fifo_pbdma_status_id_type_v(u32 r)
462{
463 return (r >> 12) & 0x1;
464}
465static inline u32 fifo_pbdma_status_id_type_chid_v(void)
466{
467 return 0x00000000;
468}
469static inline u32 fifo_pbdma_status_id_type_tsgid_v(void)
470{
471 return 0x00000001;
472}
473static inline u32 fifo_pbdma_status_chan_status_v(u32 r)
474{
475 return (r >> 13) & 0x7;
476}
477static inline u32 fifo_pbdma_status_chan_status_valid_v(void)
478{
479 return 0x00000001;
480}
481static inline u32 fifo_pbdma_status_chan_status_chsw_load_v(void)
482{
483 return 0x00000005;
484}
485static inline u32 fifo_pbdma_status_chan_status_chsw_save_v(void)
486{
487 return 0x00000006;
488}
489static inline u32 fifo_pbdma_status_chan_status_chsw_switch_v(void)
490{
491 return 0x00000007;
492}
493static inline u32 fifo_pbdma_status_next_id_v(u32 r)
494{
495 return (r >> 16) & 0xfff;
496}
497static inline u32 fifo_pbdma_status_next_id_type_v(u32 r)
498{
499 return (r >> 28) & 0x1;
500}
501static inline u32 fifo_pbdma_status_next_id_type_chid_v(void)
502{
503 return 0x00000000;
504}
505static inline u32 fifo_pbdma_status_chsw_v(u32 r)
506{
507 return (r >> 15) & 0x1;
508}
509static inline u32 fifo_pbdma_status_chsw_in_progress_v(void)
510{
511 return 0x00000001;
512}
513static inline u32 fifo_cfg0_r(void)
514{
515 return 0x00002004;
516}
517static inline u32 fifo_cfg0_num_pbdma_v(u32 r)
518{
519 return (r >> 0) & 0xff;
520}
521static inline u32 fifo_cfg0_pbdma_fault_id_v(u32 r)
522{
523 return (r >> 16) & 0xff;
524}
525static inline u32 fifo_fb_iface_r(void)
526{
527 return 0x000026f0;
528}
529static inline u32 fifo_fb_iface_control_v(u32 r)
530{
531 return (r >> 0) & 0x1;
532}
533static inline u32 fifo_fb_iface_control_enable_f(void)
534{
535 return 0x1;
536}
537static inline u32 fifo_fb_iface_status_v(u32 r)
538{
539 return (r >> 4) & 0x1;
540}
541static inline u32 fifo_fb_iface_status_enabled_f(void)
542{
543 return 0x10;
544}
545#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_flush_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_flush_gv100.h
new file mode 100644
index 00000000..c9b592bf
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_flush_gv100.h
@@ -0,0 +1,181 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_flush_gv100_h_
51#define _hw_flush_gv100_h_
52
53static inline u32 flush_l2_system_invalidate_r(void)
54{
55 return 0x00070004;
56}
57static inline u32 flush_l2_system_invalidate_pending_v(u32 r)
58{
59 return (r >> 0) & 0x1;
60}
61static inline u32 flush_l2_system_invalidate_pending_busy_v(void)
62{
63 return 0x00000001;
64}
65static inline u32 flush_l2_system_invalidate_pending_busy_f(void)
66{
67 return 0x1;
68}
69static inline u32 flush_l2_system_invalidate_outstanding_v(u32 r)
70{
71 return (r >> 1) & 0x1;
72}
73static inline u32 flush_l2_system_invalidate_outstanding_true_v(void)
74{
75 return 0x00000001;
76}
77static inline u32 flush_l2_flush_dirty_r(void)
78{
79 return 0x00070010;
80}
81static inline u32 flush_l2_flush_dirty_pending_v(u32 r)
82{
83 return (r >> 0) & 0x1;
84}
85static inline u32 flush_l2_flush_dirty_pending_empty_v(void)
86{
87 return 0x00000000;
88}
89static inline u32 flush_l2_flush_dirty_pending_empty_f(void)
90{
91 return 0x0;
92}
93static inline u32 flush_l2_flush_dirty_pending_busy_v(void)
94{
95 return 0x00000001;
96}
97static inline u32 flush_l2_flush_dirty_pending_busy_f(void)
98{
99 return 0x1;
100}
101static inline u32 flush_l2_flush_dirty_outstanding_v(u32 r)
102{
103 return (r >> 1) & 0x1;
104}
105static inline u32 flush_l2_flush_dirty_outstanding_false_v(void)
106{
107 return 0x00000000;
108}
109static inline u32 flush_l2_flush_dirty_outstanding_false_f(void)
110{
111 return 0x0;
112}
113static inline u32 flush_l2_flush_dirty_outstanding_true_v(void)
114{
115 return 0x00000001;
116}
117static inline u32 flush_l2_clean_comptags_r(void)
118{
119 return 0x0007000c;
120}
121static inline u32 flush_l2_clean_comptags_pending_v(u32 r)
122{
123 return (r >> 0) & 0x1;
124}
125static inline u32 flush_l2_clean_comptags_pending_empty_v(void)
126{
127 return 0x00000000;
128}
129static inline u32 flush_l2_clean_comptags_pending_empty_f(void)
130{
131 return 0x0;
132}
133static inline u32 flush_l2_clean_comptags_pending_busy_v(void)
134{
135 return 0x00000001;
136}
137static inline u32 flush_l2_clean_comptags_pending_busy_f(void)
138{
139 return 0x1;
140}
141static inline u32 flush_l2_clean_comptags_outstanding_v(u32 r)
142{
143 return (r >> 1) & 0x1;
144}
145static inline u32 flush_l2_clean_comptags_outstanding_false_v(void)
146{
147 return 0x00000000;
148}
149static inline u32 flush_l2_clean_comptags_outstanding_false_f(void)
150{
151 return 0x0;
152}
153static inline u32 flush_l2_clean_comptags_outstanding_true_v(void)
154{
155 return 0x00000001;
156}
157static inline u32 flush_fb_flush_r(void)
158{
159 return 0x00070000;
160}
161static inline u32 flush_fb_flush_pending_v(u32 r)
162{
163 return (r >> 0) & 0x1;
164}
165static inline u32 flush_fb_flush_pending_busy_v(void)
166{
167 return 0x00000001;
168}
169static inline u32 flush_fb_flush_pending_busy_f(void)
170{
171 return 0x1;
172}
173static inline u32 flush_fb_flush_outstanding_v(u32 r)
174{
175 return (r >> 1) & 0x1;
176}
177static inline u32 flush_fb_flush_outstanding_true_v(void)
178{
179 return 0x00000001;
180}
181#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h
new file mode 100644
index 00000000..b2b52ff2
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h
@@ -0,0 +1,137 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_fuse_gv100_h_
51#define _hw_fuse_gv100_h_
52
53static inline u32 fuse_status_opt_tpc_gpc_r(u32 i)
54{
55 return 0x00021c38 + i*4;
56}
57static inline u32 fuse_ctrl_opt_tpc_gpc_r(u32 i)
58{
59 return 0x00021838 + i*4;
60}
61static inline u32 fuse_ctrl_opt_ram_svop_pdp_r(void)
62{
63 return 0x00021944;
64}
65static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_f(u32 v)
66{
67 return (v & 0xff) << 0;
68}
69static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_m(void)
70{
71 return 0xff << 0;
72}
73static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_v(u32 r)
74{
75 return (r >> 0) & 0xff;
76}
77static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_r(void)
78{
79 return 0x00021948;
80}
81static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_f(u32 v)
82{
83 return (v & 0x1) << 0;
84}
85static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_m(void)
86{
87 return 0x1 << 0;
88}
89static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_v(u32 r)
90{
91 return (r >> 0) & 0x1;
92}
93static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f(void)
94{
95 return 0x1;
96}
97static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_no_f(void)
98{
99 return 0x0;
100}
101static inline u32 fuse_status_opt_fbio_r(void)
102{
103 return 0x00021c14;
104}
105static inline u32 fuse_status_opt_fbio_data_f(u32 v)
106{
107 return (v & 0xffff) << 0;
108}
109static inline u32 fuse_status_opt_fbio_data_m(void)
110{
111 return 0xffff << 0;
112}
113static inline u32 fuse_status_opt_fbio_data_v(u32 r)
114{
115 return (r >> 0) & 0xffff;
116}
117static inline u32 fuse_status_opt_rop_l2_fbp_r(u32 i)
118{
119 return 0x00021d70 + i*4;
120}
121static inline u32 fuse_status_opt_fbp_r(void)
122{
123 return 0x00021d38;
124}
125static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i)
126{
127 return (r >> (0 + i*1)) & 0x1;
128}
129static inline u32 fuse_opt_ecc_en_r(void)
130{
131 return 0x00021228;
132}
133static inline u32 fuse_opt_feature_fuses_override_disable_r(void)
134{
135 return 0x000213f0;
136}
137#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gmmu_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gmmu_gv100.h
new file mode 100644
index 00000000..15bdde6c
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gmmu_gv100.h
@@ -0,0 +1,1281 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_gmmu_gv100_h_
51#define _hw_gmmu_gv100_h_
52
53static inline u32 gmmu_new_pde_is_pte_w(void)
54{
55 return 0;
56}
57static inline u32 gmmu_new_pde_is_pte_false_f(void)
58{
59 return 0x0;
60}
61static inline u32 gmmu_new_pde_aperture_w(void)
62{
63 return 0;
64}
65static inline u32 gmmu_new_pde_aperture_invalid_f(void)
66{
67 return 0x0;
68}
69static inline u32 gmmu_new_pde_aperture_video_memory_f(void)
70{
71 return 0x2;
72}
73static inline u32 gmmu_new_pde_aperture_sys_mem_coh_f(void)
74{
75 return 0x4;
76}
77static inline u32 gmmu_new_pde_aperture_sys_mem_ncoh_f(void)
78{
79 return 0x6;
80}
81static inline u32 gmmu_new_pde_address_sys_f(u32 v)
82{
83 return (v & 0xffffff) << 8;
84}
85static inline u32 gmmu_new_pde_address_sys_w(void)
86{
87 return 0;
88}
89static inline u32 gmmu_new_pde_vol_w(void)
90{
91 return 0;
92}
93static inline u32 gmmu_new_pde_vol_true_f(void)
94{
95 return 0x8;
96}
97static inline u32 gmmu_new_pde_vol_false_f(void)
98{
99 return 0x0;
100}
101static inline u32 gmmu_new_pde_address_shift_v(void)
102{
103 return 0x0000000c;
104}
105static inline u32 gmmu_new_pde__size_v(void)
106{
107 return 0x00000008;
108}
109static inline u32 gmmu_new_dual_pde_is_pte_w(void)
110{
111 return 0;
112}
113static inline u32 gmmu_new_dual_pde_is_pte_false_f(void)
114{
115 return 0x0;
116}
117static inline u32 gmmu_new_dual_pde_aperture_big_w(void)
118{
119 return 0;
120}
121static inline u32 gmmu_new_dual_pde_aperture_big_invalid_f(void)
122{
123 return 0x0;
124}
125static inline u32 gmmu_new_dual_pde_aperture_big_video_memory_f(void)
126{
127 return 0x2;
128}
129static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_coh_f(void)
130{
131 return 0x4;
132}
133static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f(void)
134{
135 return 0x6;
136}
137static inline u32 gmmu_new_dual_pde_address_big_sys_f(u32 v)
138{
139 return (v & 0xfffffff) << 4;
140}
141static inline u32 gmmu_new_dual_pde_address_big_sys_w(void)
142{
143 return 0;
144}
145static inline u32 gmmu_new_dual_pde_aperture_small_w(void)
146{
147 return 2;
148}
149static inline u32 gmmu_new_dual_pde_aperture_small_invalid_f(void)
150{
151 return 0x0;
152}
153static inline u32 gmmu_new_dual_pde_aperture_small_video_memory_f(void)
154{
155 return 0x2;
156}
157static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_coh_f(void)
158{
159 return 0x4;
160}
161static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f(void)
162{
163 return 0x6;
164}
165static inline u32 gmmu_new_dual_pde_vol_small_w(void)
166{
167 return 2;
168}
169static inline u32 gmmu_new_dual_pde_vol_small_true_f(void)
170{
171 return 0x8;
172}
173static inline u32 gmmu_new_dual_pde_vol_small_false_f(void)
174{
175 return 0x0;
176}
177static inline u32 gmmu_new_dual_pde_vol_big_w(void)
178{
179 return 0;
180}
181static inline u32 gmmu_new_dual_pde_vol_big_true_f(void)
182{
183 return 0x8;
184}
185static inline u32 gmmu_new_dual_pde_vol_big_false_f(void)
186{
187 return 0x0;
188}
189static inline u32 gmmu_new_dual_pde_address_small_sys_f(u32 v)
190{
191 return (v & 0xffffff) << 8;
192}
193static inline u32 gmmu_new_dual_pde_address_small_sys_w(void)
194{
195 return 2;
196}
197static inline u32 gmmu_new_dual_pde_address_shift_v(void)
198{
199 return 0x0000000c;
200}
201static inline u32 gmmu_new_dual_pde_address_big_shift_v(void)
202{
203 return 0x00000008;
204}
205static inline u32 gmmu_new_dual_pde__size_v(void)
206{
207 return 0x00000010;
208}
209static inline u32 gmmu_new_pte__size_v(void)
210{
211 return 0x00000008;
212}
213static inline u32 gmmu_new_pte_valid_w(void)
214{
215 return 0;
216}
217static inline u32 gmmu_new_pte_valid_true_f(void)
218{
219 return 0x1;
220}
221static inline u32 gmmu_new_pte_valid_false_f(void)
222{
223 return 0x0;
224}
225static inline u32 gmmu_new_pte_privilege_w(void)
226{
227 return 0;
228}
229static inline u32 gmmu_new_pte_privilege_true_f(void)
230{
231 return 0x20;
232}
233static inline u32 gmmu_new_pte_privilege_false_f(void)
234{
235 return 0x0;
236}
237static inline u32 gmmu_new_pte_address_sys_f(u32 v)
238{
239 return (v & 0xffffff) << 8;
240}
241static inline u32 gmmu_new_pte_address_sys_w(void)
242{
243 return 0;
244}
245static inline u32 gmmu_new_pte_address_vid_f(u32 v)
246{
247 return (v & 0xffffff) << 8;
248}
249static inline u32 gmmu_new_pte_address_vid_w(void)
250{
251 return 0;
252}
253static inline u32 gmmu_new_pte_vol_w(void)
254{
255 return 0;
256}
257static inline u32 gmmu_new_pte_vol_true_f(void)
258{
259 return 0x8;
260}
261static inline u32 gmmu_new_pte_vol_false_f(void)
262{
263 return 0x0;
264}
265static inline u32 gmmu_new_pte_aperture_w(void)
266{
267 return 0;
268}
269static inline u32 gmmu_new_pte_aperture_video_memory_f(void)
270{
271 return 0x0;
272}
273static inline u32 gmmu_new_pte_aperture_sys_mem_coh_f(void)
274{
275 return 0x4;
276}
277static inline u32 gmmu_new_pte_aperture_sys_mem_ncoh_f(void)
278{
279 return 0x6;
280}
281static inline u32 gmmu_new_pte_read_only_w(void)
282{
283 return 0;
284}
285static inline u32 gmmu_new_pte_read_only_true_f(void)
286{
287 return 0x40;
288}
289static inline u32 gmmu_new_pte_comptagline_f(u32 v)
290{
291 return (v & 0x3ffff) << 4;
292}
293static inline u32 gmmu_new_pte_comptagline_w(void)
294{
295 return 1;
296}
297static inline u32 gmmu_new_pte_kind_f(u32 v)
298{
299 return (v & 0xff) << 24;
300}
301static inline u32 gmmu_new_pte_kind_w(void)
302{
303 return 1;
304}
305static inline u32 gmmu_new_pte_address_shift_v(void)
306{
307 return 0x0000000c;
308}
309static inline u32 gmmu_pte_kind_f(u32 v)
310{
311 return (v & 0xff) << 4;
312}
313static inline u32 gmmu_pte_kind_w(void)
314{
315 return 1;
316}
317static inline u32 gmmu_pte_kind_invalid_v(void)
318{
319 return 0x000000ff;
320}
321static inline u32 gmmu_pte_kind_pitch_v(void)
322{
323 return 0x00000000;
324}
325static inline u32 gmmu_pte_kind_z16_v(void)
326{
327 return 0x00000001;
328}
329static inline u32 gmmu_pte_kind_z16_2c_v(void)
330{
331 return 0x00000002;
332}
333static inline u32 gmmu_pte_kind_z16_ms2_2c_v(void)
334{
335 return 0x00000003;
336}
337static inline u32 gmmu_pte_kind_z16_ms4_2c_v(void)
338{
339 return 0x00000004;
340}
341static inline u32 gmmu_pte_kind_z16_ms8_2c_v(void)
342{
343 return 0x00000005;
344}
345static inline u32 gmmu_pte_kind_z16_ms16_2c_v(void)
346{
347 return 0x00000006;
348}
349static inline u32 gmmu_pte_kind_z16_2z_v(void)
350{
351 return 0x00000007;
352}
353static inline u32 gmmu_pte_kind_z16_ms2_2z_v(void)
354{
355 return 0x00000008;
356}
357static inline u32 gmmu_pte_kind_z16_ms4_2z_v(void)
358{
359 return 0x00000009;
360}
361static inline u32 gmmu_pte_kind_z16_ms8_2z_v(void)
362{
363 return 0x0000000a;
364}
365static inline u32 gmmu_pte_kind_z16_ms16_2z_v(void)
366{
367 return 0x0000000b;
368}
369static inline u32 gmmu_pte_kind_z16_2cz_v(void)
370{
371 return 0x00000036;
372}
373static inline u32 gmmu_pte_kind_z16_ms2_2cz_v(void)
374{
375 return 0x00000037;
376}
377static inline u32 gmmu_pte_kind_z16_ms4_2cz_v(void)
378{
379 return 0x00000038;
380}
381static inline u32 gmmu_pte_kind_z16_ms8_2cz_v(void)
382{
383 return 0x00000039;
384}
385static inline u32 gmmu_pte_kind_z16_ms16_2cz_v(void)
386{
387 return 0x0000005f;
388}
389static inline u32 gmmu_pte_kind_s8z24_v(void)
390{
391 return 0x00000011;
392}
393static inline u32 gmmu_pte_kind_s8z24_1z_v(void)
394{
395 return 0x00000012;
396}
397static inline u32 gmmu_pte_kind_s8z24_ms2_1z_v(void)
398{
399 return 0x00000013;
400}
401static inline u32 gmmu_pte_kind_s8z24_ms4_1z_v(void)
402{
403 return 0x00000014;
404}
405static inline u32 gmmu_pte_kind_s8z24_ms8_1z_v(void)
406{
407 return 0x00000015;
408}
409static inline u32 gmmu_pte_kind_s8z24_ms16_1z_v(void)
410{
411 return 0x00000016;
412}
413static inline u32 gmmu_pte_kind_s8z24_2cz_v(void)
414{
415 return 0x00000017;
416}
417static inline u32 gmmu_pte_kind_s8z24_ms2_2cz_v(void)
418{
419 return 0x00000018;
420}
421static inline u32 gmmu_pte_kind_s8z24_ms4_2cz_v(void)
422{
423 return 0x00000019;
424}
425static inline u32 gmmu_pte_kind_s8z24_ms8_2cz_v(void)
426{
427 return 0x0000001a;
428}
429static inline u32 gmmu_pte_kind_s8z24_ms16_2cz_v(void)
430{
431 return 0x0000001b;
432}
433static inline u32 gmmu_pte_kind_s8z24_2cs_v(void)
434{
435 return 0x0000001c;
436}
437static inline u32 gmmu_pte_kind_s8z24_ms2_2cs_v(void)
438{
439 return 0x0000001d;
440}
441static inline u32 gmmu_pte_kind_s8z24_ms4_2cs_v(void)
442{
443 return 0x0000001e;
444}
445static inline u32 gmmu_pte_kind_s8z24_ms8_2cs_v(void)
446{
447 return 0x0000001f;
448}
449static inline u32 gmmu_pte_kind_s8z24_ms16_2cs_v(void)
450{
451 return 0x00000020;
452}
453static inline u32 gmmu_pte_kind_s8z24_4cszv_v(void)
454{
455 return 0x00000021;
456}
457static inline u32 gmmu_pte_kind_s8z24_ms2_4cszv_v(void)
458{
459 return 0x00000022;
460}
461static inline u32 gmmu_pte_kind_s8z24_ms4_4cszv_v(void)
462{
463 return 0x00000023;
464}
465static inline u32 gmmu_pte_kind_s8z24_ms8_4cszv_v(void)
466{
467 return 0x00000024;
468}
469static inline u32 gmmu_pte_kind_s8z24_ms16_4cszv_v(void)
470{
471 return 0x00000025;
472}
473static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_v(void)
474{
475 return 0x00000026;
476}
477static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_v(void)
478{
479 return 0x00000027;
480}
481static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_v(void)
482{
483 return 0x00000028;
484}
485static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_v(void)
486{
487 return 0x00000029;
488}
489static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_1zv_v(void)
490{
491 return 0x0000002e;
492}
493static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_1zv_v(void)
494{
495 return 0x0000002f;
496}
497static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_1zv_v(void)
498{
499 return 0x00000030;
500}
501static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_1zv_v(void)
502{
503 return 0x00000031;
504}
505static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2cs_v(void)
506{
507 return 0x00000032;
508}
509static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2cs_v(void)
510{
511 return 0x00000033;
512}
513static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2cs_v(void)
514{
515 return 0x00000034;
516}
517static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2cs_v(void)
518{
519 return 0x00000035;
520}
521static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2czv_v(void)
522{
523 return 0x0000003a;
524}
525static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2czv_v(void)
526{
527 return 0x0000003b;
528}
529static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2czv_v(void)
530{
531 return 0x0000003c;
532}
533static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2czv_v(void)
534{
535 return 0x0000003d;
536}
537static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2zv_v(void)
538{
539 return 0x0000003e;
540}
541static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2zv_v(void)
542{
543 return 0x0000003f;
544}
545static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2zv_v(void)
546{
547 return 0x00000040;
548}
549static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2zv_v(void)
550{
551 return 0x00000041;
552}
553static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_4cszv_v(void)
554{
555 return 0x00000042;
556}
557static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_4cszv_v(void)
558{
559 return 0x00000043;
560}
561static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_4cszv_v(void)
562{
563 return 0x00000044;
564}
565static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_4cszv_v(void)
566{
567 return 0x00000045;
568}
569static inline u32 gmmu_pte_kind_z24s8_v(void)
570{
571 return 0x00000046;
572}
573static inline u32 gmmu_pte_kind_z24s8_1z_v(void)
574{
575 return 0x00000047;
576}
577static inline u32 gmmu_pte_kind_z24s8_ms2_1z_v(void)
578{
579 return 0x00000048;
580}
581static inline u32 gmmu_pte_kind_z24s8_ms4_1z_v(void)
582{
583 return 0x00000049;
584}
585static inline u32 gmmu_pte_kind_z24s8_ms8_1z_v(void)
586{
587 return 0x0000004a;
588}
589static inline u32 gmmu_pte_kind_z24s8_ms16_1z_v(void)
590{
591 return 0x0000004b;
592}
593static inline u32 gmmu_pte_kind_z24s8_2cs_v(void)
594{
595 return 0x0000004c;
596}
597static inline u32 gmmu_pte_kind_z24s8_ms2_2cs_v(void)
598{
599 return 0x0000004d;
600}
601static inline u32 gmmu_pte_kind_z24s8_ms4_2cs_v(void)
602{
603 return 0x0000004e;
604}
605static inline u32 gmmu_pte_kind_z24s8_ms8_2cs_v(void)
606{
607 return 0x0000004f;
608}
609static inline u32 gmmu_pte_kind_z24s8_ms16_2cs_v(void)
610{
611 return 0x00000050;
612}
613static inline u32 gmmu_pte_kind_z24s8_2cz_v(void)
614{
615 return 0x00000051;
616}
617static inline u32 gmmu_pte_kind_z24s8_ms2_2cz_v(void)
618{
619 return 0x00000052;
620}
621static inline u32 gmmu_pte_kind_z24s8_ms4_2cz_v(void)
622{
623 return 0x00000053;
624}
625static inline u32 gmmu_pte_kind_z24s8_ms8_2cz_v(void)
626{
627 return 0x00000054;
628}
629static inline u32 gmmu_pte_kind_z24s8_ms16_2cz_v(void)
630{
631 return 0x00000055;
632}
633static inline u32 gmmu_pte_kind_z24s8_4cszv_v(void)
634{
635 return 0x00000056;
636}
637static inline u32 gmmu_pte_kind_z24s8_ms2_4cszv_v(void)
638{
639 return 0x00000057;
640}
641static inline u32 gmmu_pte_kind_z24s8_ms4_4cszv_v(void)
642{
643 return 0x00000058;
644}
645static inline u32 gmmu_pte_kind_z24s8_ms8_4cszv_v(void)
646{
647 return 0x00000059;
648}
649static inline u32 gmmu_pte_kind_z24s8_ms16_4cszv_v(void)
650{
651 return 0x0000005a;
652}
653static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_v(void)
654{
655 return 0x0000005b;
656}
657static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_v(void)
658{
659 return 0x0000005c;
660}
661static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_v(void)
662{
663 return 0x0000005d;
664}
665static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_v(void)
666{
667 return 0x0000005e;
668}
669static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_1zv_v(void)
670{
671 return 0x00000063;
672}
673static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_1zv_v(void)
674{
675 return 0x00000064;
676}
677static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_1zv_v(void)
678{
679 return 0x00000065;
680}
681static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_1zv_v(void)
682{
683 return 0x00000066;
684}
685static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2cs_v(void)
686{
687 return 0x00000067;
688}
689static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2cs_v(void)
690{
691 return 0x00000068;
692}
693static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2cs_v(void)
694{
695 return 0x00000069;
696}
697static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2cs_v(void)
698{
699 return 0x0000006a;
700}
701static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2czv_v(void)
702{
703 return 0x0000006f;
704}
705static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2czv_v(void)
706{
707 return 0x00000070;
708}
709static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2czv_v(void)
710{
711 return 0x00000071;
712}
713static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2czv_v(void)
714{
715 return 0x00000072;
716}
717static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2zv_v(void)
718{
719 return 0x00000073;
720}
721static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2zv_v(void)
722{
723 return 0x00000074;
724}
725static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2zv_v(void)
726{
727 return 0x00000075;
728}
729static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2zv_v(void)
730{
731 return 0x00000076;
732}
733static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_4cszv_v(void)
734{
735 return 0x00000077;
736}
737static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_4cszv_v(void)
738{
739 return 0x00000078;
740}
741static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_4cszv_v(void)
742{
743 return 0x00000079;
744}
745static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_4cszv_v(void)
746{
747 return 0x0000007a;
748}
749static inline u32 gmmu_pte_kind_zf32_v(void)
750{
751 return 0x0000007b;
752}
753static inline u32 gmmu_pte_kind_zf32_1z_v(void)
754{
755 return 0x0000007c;
756}
757static inline u32 gmmu_pte_kind_zf32_ms2_1z_v(void)
758{
759 return 0x0000007d;
760}
761static inline u32 gmmu_pte_kind_zf32_ms4_1z_v(void)
762{
763 return 0x0000007e;
764}
765static inline u32 gmmu_pte_kind_zf32_ms8_1z_v(void)
766{
767 return 0x0000007f;
768}
769static inline u32 gmmu_pte_kind_zf32_ms16_1z_v(void)
770{
771 return 0x00000080;
772}
773static inline u32 gmmu_pte_kind_zf32_2cs_v(void)
774{
775 return 0x00000081;
776}
777static inline u32 gmmu_pte_kind_zf32_ms2_2cs_v(void)
778{
779 return 0x00000082;
780}
781static inline u32 gmmu_pte_kind_zf32_ms4_2cs_v(void)
782{
783 return 0x00000083;
784}
785static inline u32 gmmu_pte_kind_zf32_ms8_2cs_v(void)
786{
787 return 0x00000084;
788}
789static inline u32 gmmu_pte_kind_zf32_ms16_2cs_v(void)
790{
791 return 0x00000085;
792}
793static inline u32 gmmu_pte_kind_zf32_2cz_v(void)
794{
795 return 0x00000086;
796}
797static inline u32 gmmu_pte_kind_zf32_ms2_2cz_v(void)
798{
799 return 0x00000087;
800}
801static inline u32 gmmu_pte_kind_zf32_ms4_2cz_v(void)
802{
803 return 0x00000088;
804}
805static inline u32 gmmu_pte_kind_zf32_ms8_2cz_v(void)
806{
807 return 0x00000089;
808}
809static inline u32 gmmu_pte_kind_zf32_ms16_2cz_v(void)
810{
811 return 0x0000008a;
812}
813static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_v(void)
814{
815 return 0x0000008b;
816}
817static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_v(void)
818{
819 return 0x0000008c;
820}
821static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_v(void)
822{
823 return 0x0000008d;
824}
825static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_v(void)
826{
827 return 0x0000008e;
828}
829static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1cs_v(void)
830{
831 return 0x0000008f;
832}
833static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1cs_v(void)
834{
835 return 0x00000090;
836}
837static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1cs_v(void)
838{
839 return 0x00000091;
840}
841static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1cs_v(void)
842{
843 return 0x00000092;
844}
845static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1zv_v(void)
846{
847 return 0x00000097;
848}
849static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1zv_v(void)
850{
851 return 0x00000098;
852}
853static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1zv_v(void)
854{
855 return 0x00000099;
856}
857static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1zv_v(void)
858{
859 return 0x0000009a;
860}
861static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1czv_v(void)
862{
863 return 0x0000009b;
864}
865static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1czv_v(void)
866{
867 return 0x0000009c;
868}
869static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1czv_v(void)
870{
871 return 0x0000009d;
872}
873static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1czv_v(void)
874{
875 return 0x0000009e;
876}
877static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cs_v(void)
878{
879 return 0x0000009f;
880}
881static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cs_v(void)
882{
883 return 0x000000a0;
884}
885static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cs_v(void)
886{
887 return 0x000000a1;
888}
889static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cs_v(void)
890{
891 return 0x000000a2;
892}
893static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cszv_v(void)
894{
895 return 0x000000a3;
896}
897static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cszv_v(void)
898{
899 return 0x000000a4;
900}
901static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cszv_v(void)
902{
903 return 0x000000a5;
904}
905static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cszv_v(void)
906{
907 return 0x000000a6;
908}
909static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_v(void)
910{
911 return 0x000000a7;
912}
913static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_v(void)
914{
915 return 0x000000a8;
916}
917static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_v(void)
918{
919 return 0x000000a9;
920}
921static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_v(void)
922{
923 return 0x000000aa;
924}
925static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1cs_v(void)
926{
927 return 0x000000ab;
928}
929static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1cs_v(void)
930{
931 return 0x000000ac;
932}
933static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1cs_v(void)
934{
935 return 0x000000ad;
936}
937static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1cs_v(void)
938{
939 return 0x000000ae;
940}
941static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1zv_v(void)
942{
943 return 0x000000b3;
944}
945static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1zv_v(void)
946{
947 return 0x000000b4;
948}
949static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1zv_v(void)
950{
951 return 0x000000b5;
952}
953static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1zv_v(void)
954{
955 return 0x000000b6;
956}
957static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1czv_v(void)
958{
959 return 0x000000b7;
960}
961static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1czv_v(void)
962{
963 return 0x000000b8;
964}
965static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1czv_v(void)
966{
967 return 0x000000b9;
968}
969static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1czv_v(void)
970{
971 return 0x000000ba;
972}
973static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cs_v(void)
974{
975 return 0x000000bb;
976}
977static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cs_v(void)
978{
979 return 0x000000bc;
980}
981static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cs_v(void)
982{
983 return 0x000000bd;
984}
985static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cs_v(void)
986{
987 return 0x000000be;
988}
989static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cszv_v(void)
990{
991 return 0x000000bf;
992}
993static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cszv_v(void)
994{
995 return 0x000000c0;
996}
997static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cszv_v(void)
998{
999 return 0x000000c1;
1000}
1001static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cszv_v(void)
1002{
1003 return 0x000000c2;
1004}
1005static inline u32 gmmu_pte_kind_zf32_x24s8_v(void)
1006{
1007 return 0x000000c3;
1008}
1009static inline u32 gmmu_pte_kind_zf32_x24s8_1cs_v(void)
1010{
1011 return 0x000000c4;
1012}
1013static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_1cs_v(void)
1014{
1015 return 0x000000c5;
1016}
1017static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_1cs_v(void)
1018{
1019 return 0x000000c6;
1020}
1021static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_1cs_v(void)
1022{
1023 return 0x000000c7;
1024}
1025static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_1cs_v(void)
1026{
1027 return 0x000000c8;
1028}
1029static inline u32 gmmu_pte_kind_zf32_x24s8_2cszv_v(void)
1030{
1031 return 0x000000ce;
1032}
1033static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cszv_v(void)
1034{
1035 return 0x000000cf;
1036}
1037static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cszv_v(void)
1038{
1039 return 0x000000d0;
1040}
1041static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cszv_v(void)
1042{
1043 return 0x000000d1;
1044}
1045static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cszv_v(void)
1046{
1047 return 0x000000d2;
1048}
1049static inline u32 gmmu_pte_kind_zf32_x24s8_2cs_v(void)
1050{
1051 return 0x000000d3;
1052}
1053static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cs_v(void)
1054{
1055 return 0x000000d4;
1056}
1057static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cs_v(void)
1058{
1059 return 0x000000d5;
1060}
1061static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cs_v(void)
1062{
1063 return 0x000000d6;
1064}
1065static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cs_v(void)
1066{
1067 return 0x000000d7;
1068}
1069static inline u32 gmmu_pte_kind_generic_16bx2_v(void)
1070{
1071 return 0x000000fe;
1072}
1073static inline u32 gmmu_pte_kind_c32_2c_v(void)
1074{
1075 return 0x000000d8;
1076}
1077static inline u32 gmmu_pte_kind_c32_2cbr_v(void)
1078{
1079 return 0x000000d9;
1080}
1081static inline u32 gmmu_pte_kind_c32_2cba_v(void)
1082{
1083 return 0x000000da;
1084}
1085static inline u32 gmmu_pte_kind_c32_2cra_v(void)
1086{
1087 return 0x000000db;
1088}
1089static inline u32 gmmu_pte_kind_c32_2bra_v(void)
1090{
1091 return 0x000000dc;
1092}
1093static inline u32 gmmu_pte_kind_c32_ms2_2c_v(void)
1094{
1095 return 0x000000dd;
1096}
1097static inline u32 gmmu_pte_kind_c32_ms2_2cbr_v(void)
1098{
1099 return 0x000000de;
1100}
1101static inline u32 gmmu_pte_kind_c32_ms2_4cbra_v(void)
1102{
1103 return 0x000000cc;
1104}
1105static inline u32 gmmu_pte_kind_c32_ms4_2c_v(void)
1106{
1107 return 0x000000df;
1108}
1109static inline u32 gmmu_pte_kind_c32_ms4_2cbr_v(void)
1110{
1111 return 0x000000e0;
1112}
1113static inline u32 gmmu_pte_kind_c32_ms4_2cba_v(void)
1114{
1115 return 0x000000e1;
1116}
1117static inline u32 gmmu_pte_kind_c32_ms4_2cra_v(void)
1118{
1119 return 0x000000e2;
1120}
1121static inline u32 gmmu_pte_kind_c32_ms4_2bra_v(void)
1122{
1123 return 0x000000e3;
1124}
1125static inline u32 gmmu_pte_kind_c32_ms4_4cbra_v(void)
1126{
1127 return 0x0000002c;
1128}
1129static inline u32 gmmu_pte_kind_c32_ms8_ms16_2c_v(void)
1130{
1131 return 0x000000e4;
1132}
1133static inline u32 gmmu_pte_kind_c32_ms8_ms16_2cra_v(void)
1134{
1135 return 0x000000e5;
1136}
1137static inline u32 gmmu_pte_kind_c64_2c_v(void)
1138{
1139 return 0x000000e6;
1140}
1141static inline u32 gmmu_pte_kind_c64_2cbr_v(void)
1142{
1143 return 0x000000e7;
1144}
1145static inline u32 gmmu_pte_kind_c64_2cba_v(void)
1146{
1147 return 0x000000e8;
1148}
1149static inline u32 gmmu_pte_kind_c64_2cra_v(void)
1150{
1151 return 0x000000e9;
1152}
1153static inline u32 gmmu_pte_kind_c64_2bra_v(void)
1154{
1155 return 0x000000ea;
1156}
1157static inline u32 gmmu_pte_kind_c64_ms2_2c_v(void)
1158{
1159 return 0x000000eb;
1160}
1161static inline u32 gmmu_pte_kind_c64_ms2_2cbr_v(void)
1162{
1163 return 0x000000ec;
1164}
1165static inline u32 gmmu_pte_kind_c64_ms2_4cbra_v(void)
1166{
1167 return 0x000000cd;
1168}
1169static inline u32 gmmu_pte_kind_c64_ms4_2c_v(void)
1170{
1171 return 0x000000ed;
1172}
1173static inline u32 gmmu_pte_kind_c64_ms4_2cbr_v(void)
1174{
1175 return 0x000000ee;
1176}
1177static inline u32 gmmu_pte_kind_c64_ms4_2cba_v(void)
1178{
1179 return 0x000000ef;
1180}
1181static inline u32 gmmu_pte_kind_c64_ms4_2cra_v(void)
1182{
1183 return 0x000000f0;
1184}
1185static inline u32 gmmu_pte_kind_c64_ms4_2bra_v(void)
1186{
1187 return 0x000000f1;
1188}
1189static inline u32 gmmu_pte_kind_c64_ms4_4cbra_v(void)
1190{
1191 return 0x0000002d;
1192}
1193static inline u32 gmmu_pte_kind_c64_ms8_ms16_2c_v(void)
1194{
1195 return 0x000000f2;
1196}
1197static inline u32 gmmu_pte_kind_c64_ms8_ms16_2cra_v(void)
1198{
1199 return 0x000000f3;
1200}
1201static inline u32 gmmu_pte_kind_c128_2c_v(void)
1202{
1203 return 0x000000f4;
1204}
1205static inline u32 gmmu_pte_kind_c128_2cr_v(void)
1206{
1207 return 0x000000f5;
1208}
1209static inline u32 gmmu_pte_kind_c128_ms2_2c_v(void)
1210{
1211 return 0x000000f6;
1212}
1213static inline u32 gmmu_pte_kind_c128_ms2_2cr_v(void)
1214{
1215 return 0x000000f7;
1216}
1217static inline u32 gmmu_pte_kind_c128_ms4_2c_v(void)
1218{
1219 return 0x000000f8;
1220}
1221static inline u32 gmmu_pte_kind_c128_ms4_2cr_v(void)
1222{
1223 return 0x000000f9;
1224}
1225static inline u32 gmmu_pte_kind_c128_ms8_ms16_2c_v(void)
1226{
1227 return 0x000000fa;
1228}
1229static inline u32 gmmu_pte_kind_c128_ms8_ms16_2cr_v(void)
1230{
1231 return 0x000000fb;
1232}
1233static inline u32 gmmu_pte_kind_x8c24_v(void)
1234{
1235 return 0x000000fc;
1236}
1237static inline u32 gmmu_pte_kind_pitch_no_swizzle_v(void)
1238{
1239 return 0x000000fd;
1240}
1241static inline u32 gmmu_pte_kind_smsked_message_v(void)
1242{
1243 return 0x000000ca;
1244}
1245static inline u32 gmmu_pte_kind_smhost_message_v(void)
1246{
1247 return 0x000000cb;
1248}
1249static inline u32 gmmu_pte_kind_s8_v(void)
1250{
1251 return 0x0000002a;
1252}
1253static inline u32 gmmu_pte_kind_s8_2s_v(void)
1254{
1255 return 0x0000002b;
1256}
1257static inline u32 gmmu_fault_client_type_gpc_v(void)
1258{
1259 return 0x00000000;
1260}
1261static inline u32 gmmu_fault_client_type_hub_v(void)
1262{
1263 return 0x00000001;
1264}
1265static inline u32 gmmu_fault_type_unbound_inst_block_v(void)
1266{
1267 return 0x00000004;
1268}
1269static inline u32 gmmu_fault_mmu_eng_id_bar2_v(void)
1270{
1271 return 0x00000005;
1272}
1273static inline u32 gmmu_fault_mmu_eng_id_physical_v(void)
1274{
1275 return 0x0000001f;
1276}
1277static inline u32 gmmu_fault_mmu_eng_id_ce0_v(void)
1278{
1279 return 0x0000000f;
1280}
1281#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h
new file mode 100644
index 00000000..af1915b2
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h
@@ -0,0 +1,3905 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_gr_gv100_h_
51#define _hw_gr_gv100_h_
52
53static inline u32 gr_intr_r(void)
54{
55 return 0x00400100;
56}
57static inline u32 gr_intr_notify_pending_f(void)
58{
59 return 0x1;
60}
61static inline u32 gr_intr_notify_reset_f(void)
62{
63 return 0x1;
64}
65static inline u32 gr_intr_semaphore_pending_f(void)
66{
67 return 0x2;
68}
69static inline u32 gr_intr_semaphore_reset_f(void)
70{
71 return 0x2;
72}
73static inline u32 gr_intr_illegal_method_pending_f(void)
74{
75 return 0x10;
76}
77static inline u32 gr_intr_illegal_method_reset_f(void)
78{
79 return 0x10;
80}
81static inline u32 gr_intr_illegal_notify_pending_f(void)
82{
83 return 0x40;
84}
85static inline u32 gr_intr_illegal_notify_reset_f(void)
86{
87 return 0x40;
88}
89static inline u32 gr_intr_firmware_method_f(u32 v)
90{
91 return (v & 0x1) << 8;
92}
93static inline u32 gr_intr_firmware_method_pending_f(void)
94{
95 return 0x100;
96}
97static inline u32 gr_intr_firmware_method_reset_f(void)
98{
99 return 0x100;
100}
101static inline u32 gr_intr_illegal_class_pending_f(void)
102{
103 return 0x20;
104}
105static inline u32 gr_intr_illegal_class_reset_f(void)
106{
107 return 0x20;
108}
109static inline u32 gr_intr_fecs_error_pending_f(void)
110{
111 return 0x80000;
112}
113static inline u32 gr_intr_fecs_error_reset_f(void)
114{
115 return 0x80000;
116}
117static inline u32 gr_intr_class_error_pending_f(void)
118{
119 return 0x100000;
120}
121static inline u32 gr_intr_class_error_reset_f(void)
122{
123 return 0x100000;
124}
125static inline u32 gr_intr_exception_pending_f(void)
126{
127 return 0x200000;
128}
129static inline u32 gr_intr_exception_reset_f(void)
130{
131 return 0x200000;
132}
133static inline u32 gr_fecs_intr_r(void)
134{
135 return 0x00400144;
136}
137static inline u32 gr_class_error_r(void)
138{
139 return 0x00400110;
140}
141static inline u32 gr_class_error_code_v(u32 r)
142{
143 return (r >> 0) & 0xffff;
144}
145static inline u32 gr_intr_nonstall_r(void)
146{
147 return 0x00400120;
148}
149static inline u32 gr_intr_nonstall_trap_pending_f(void)
150{
151 return 0x2;
152}
153static inline u32 gr_intr_en_r(void)
154{
155 return 0x0040013c;
156}
157static inline u32 gr_exception_r(void)
158{
159 return 0x00400108;
160}
161static inline u32 gr_exception_fe_m(void)
162{
163 return 0x1 << 0;
164}
165static inline u32 gr_exception_gpc_m(void)
166{
167 return 0x1 << 24;
168}
169static inline u32 gr_exception_memfmt_m(void)
170{
171 return 0x1 << 1;
172}
173static inline u32 gr_exception_ds_m(void)
174{
175 return 0x1 << 4;
176}
177static inline u32 gr_exception_sked_m(void)
178{
179 return 0x1 << 8;
180}
181static inline u32 gr_exception1_r(void)
182{
183 return 0x00400118;
184}
185static inline u32 gr_exception1_gpc_0_pending_f(void)
186{
187 return 0x1;
188}
189static inline u32 gr_exception2_r(void)
190{
191 return 0x0040011c;
192}
193static inline u32 gr_exception_en_r(void)
194{
195 return 0x00400138;
196}
197static inline u32 gr_exception_en_fe_m(void)
198{
199 return 0x1 << 0;
200}
201static inline u32 gr_exception_en_fe_enabled_f(void)
202{
203 return 0x1;
204}
205static inline u32 gr_exception_en_gpc_m(void)
206{
207 return 0x1 << 24;
208}
209static inline u32 gr_exception_en_gpc_enabled_f(void)
210{
211 return 0x1000000;
212}
213static inline u32 gr_exception_en_memfmt_m(void)
214{
215 return 0x1 << 1;
216}
217static inline u32 gr_exception_en_memfmt_enabled_f(void)
218{
219 return 0x2;
220}
221static inline u32 gr_exception_en_ds_m(void)
222{
223 return 0x1 << 4;
224}
225static inline u32 gr_exception_en_ds_enabled_f(void)
226{
227 return 0x10;
228}
229static inline u32 gr_exception1_en_r(void)
230{
231 return 0x00400130;
232}
233static inline u32 gr_exception2_en_r(void)
234{
235 return 0x00400134;
236}
237static inline u32 gr_gpfifo_ctl_r(void)
238{
239 return 0x00400500;
240}
241static inline u32 gr_gpfifo_ctl_access_f(u32 v)
242{
243 return (v & 0x1) << 0;
244}
245static inline u32 gr_gpfifo_ctl_access_disabled_f(void)
246{
247 return 0x0;
248}
249static inline u32 gr_gpfifo_ctl_access_enabled_f(void)
250{
251 return 0x1;
252}
253static inline u32 gr_gpfifo_ctl_semaphore_access_f(u32 v)
254{
255 return (v & 0x1) << 16;
256}
257static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_v(void)
258{
259 return 0x00000001;
260}
261static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_f(void)
262{
263 return 0x10000;
264}
265static inline u32 gr_gpfifo_status_r(void)
266{
267 return 0x00400504;
268}
269static inline u32 gr_trapped_addr_r(void)
270{
271 return 0x00400704;
272}
273static inline u32 gr_trapped_addr_mthd_v(u32 r)
274{
275 return (r >> 2) & 0xfff;
276}
277static inline u32 gr_trapped_addr_subch_v(u32 r)
278{
279 return (r >> 16) & 0x7;
280}
281static inline u32 gr_trapped_data_lo_r(void)
282{
283 return 0x00400708;
284}
285static inline u32 gr_trapped_data_hi_r(void)
286{
287 return 0x0040070c;
288}
289static inline u32 gr_status_r(void)
290{
291 return 0x00400700;
292}
293static inline u32 gr_status_fe_method_upper_v(u32 r)
294{
295 return (r >> 1) & 0x1;
296}
297static inline u32 gr_status_fe_method_lower_v(u32 r)
298{
299 return (r >> 2) & 0x1;
300}
301static inline u32 gr_status_fe_method_lower_idle_v(void)
302{
303 return 0x00000000;
304}
305static inline u32 gr_status_fe_gi_v(u32 r)
306{
307 return (r >> 21) & 0x1;
308}
309static inline u32 gr_status_mask_r(void)
310{
311 return 0x00400610;
312}
313static inline u32 gr_status_1_r(void)
314{
315 return 0x00400604;
316}
317static inline u32 gr_status_2_r(void)
318{
319 return 0x00400608;
320}
321static inline u32 gr_engine_status_r(void)
322{
323 return 0x0040060c;
324}
325static inline u32 gr_engine_status_value_busy_f(void)
326{
327 return 0x1;
328}
329static inline u32 gr_pri_be0_becs_be_exception_r(void)
330{
331 return 0x00410204;
332}
333static inline u32 gr_pri_be0_becs_be_exception_en_r(void)
334{
335 return 0x00410208;
336}
337static inline u32 gr_pri_gpc0_gpccs_gpc_exception_r(void)
338{
339 return 0x00502c90;
340}
341static inline u32 gr_pri_gpc0_gpccs_gpc_exception_en_r(void)
342{
343 return 0x00502c94;
344}
345static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_r(void)
346{
347 return 0x00504508;
348}
349static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r(void)
350{
351 return 0x0050450c;
352}
353static inline u32 gr_activity_0_r(void)
354{
355 return 0x00400380;
356}
357static inline u32 gr_activity_1_r(void)
358{
359 return 0x00400384;
360}
361static inline u32 gr_activity_2_r(void)
362{
363 return 0x00400388;
364}
365static inline u32 gr_activity_4_r(void)
366{
367 return 0x00400390;
368}
369static inline u32 gr_activity_4_gpc0_s(void)
370{
371 return 3;
372}
373static inline u32 gr_activity_4_gpc0_f(u32 v)
374{
375 return (v & 0x7) << 0;
376}
377static inline u32 gr_activity_4_gpc0_m(void)
378{
379 return 0x7 << 0;
380}
381static inline u32 gr_activity_4_gpc0_v(u32 r)
382{
383 return (r >> 0) & 0x7;
384}
385static inline u32 gr_activity_4_gpc0_empty_v(void)
386{
387 return 0x00000000;
388}
389static inline u32 gr_activity_4_gpc0_preempted_v(void)
390{
391 return 0x00000004;
392}
393static inline u32 gr_pri_gpc0_gcc_dbg_r(void)
394{
395 return 0x00501000;
396}
397static inline u32 gr_pri_gpcs_gcc_dbg_r(void)
398{
399 return 0x00419000;
400}
401static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void)
402{
403 return 0x1 << 1;
404}
405static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void)
406{
407 return 0x0050433c;
408}
409static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void)
410{
411 return 0x00419b3c;
412}
413static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void)
414{
415 return 0x1 << 0;
416}
417static inline u32 gr_pri_sked_activity_r(void)
418{
419 return 0x00407054;
420}
421static inline u32 gr_pri_gpc0_gpccs_gpc_activity0_r(void)
422{
423 return 0x00502c80;
424}
425static inline u32 gr_pri_gpc0_gpccs_gpc_activity1_r(void)
426{
427 return 0x00502c84;
428}
429static inline u32 gr_pri_gpc0_gpccs_gpc_activity2_r(void)
430{
431 return 0x00502c88;
432}
433static inline u32 gr_pri_gpc0_gpccs_gpc_activity3_r(void)
434{
435 return 0x00502c8c;
436}
437static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r(void)
438{
439 return 0x00504500;
440}
441static inline u32 gr_pri_gpc0_tpc1_tpccs_tpc_activity_0_r(void)
442{
443 return 0x00504d00;
444}
445static inline u32 gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r(void)
446{
447 return 0x00501d00;
448}
449static inline u32 gr_pri_gpcs_gpccs_gpc_activity_0_r(void)
450{
451 return 0x0041ac80;
452}
453static inline u32 gr_pri_gpcs_gpccs_gpc_activity_1_r(void)
454{
455 return 0x0041ac84;
456}
457static inline u32 gr_pri_gpcs_gpccs_gpc_activity_2_r(void)
458{
459 return 0x0041ac88;
460}
461static inline u32 gr_pri_gpcs_gpccs_gpc_activity_3_r(void)
462{
463 return 0x0041ac8c;
464}
465static inline u32 gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r(void)
466{
467 return 0x0041c500;
468}
469static inline u32 gr_pri_gpcs_tpc1_tpccs_tpc_activity_0_r(void)
470{
471 return 0x0041cd00;
472}
473static inline u32 gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r(void)
474{
475 return 0x00419d00;
476}
477static inline u32 gr_pri_be0_becs_be_activity0_r(void)
478{
479 return 0x00410200;
480}
481static inline u32 gr_pri_be1_becs_be_activity0_r(void)
482{
483 return 0x00410600;
484}
485static inline u32 gr_pri_bes_becs_be_activity0_r(void)
486{
487 return 0x00408a00;
488}
489static inline u32 gr_pri_ds_mpipe_status_r(void)
490{
491 return 0x00405858;
492}
493static inline u32 gr_pri_fe_go_idle_info_r(void)
494{
495 return 0x00404194;
496}
497static inline u32 gr_pri_fe_chip_def_info_r(void)
498{
499 return 0x00404030;
500}
501static inline u32 gr_pri_fe_chip_def_info_max_veid_count_v(u32 r)
502{
503 return (r >> 0) & 0xfff;
504}
505static inline u32 gr_pri_fe_chip_def_info_max_veid_count_init_v(void)
506{
507 return 0x00000040;
508}
509static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void)
510{
511 return 0x00504238;
512}
513static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r(void)
514{
515 return 0x00504358;
516}
517static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp0_m(void)
518{
519 return 0x1 << 0;
520}
521static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp1_m(void)
522{
523 return 0x1 << 1;
524}
525static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp2_m(void)
526{
527 return 0x1 << 2;
528}
529static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp3_m(void)
530{
531 return 0x1 << 3;
532}
533static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp4_m(void)
534{
535 return 0x1 << 4;
536}
537static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp5_m(void)
538{
539 return 0x1 << 5;
540}
541static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp6_m(void)
542{
543 return 0x1 << 6;
544}
545static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp7_m(void)
546{
547 return 0x1 << 7;
548}
549static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp0_m(void)
550{
551 return 0x1 << 8;
552}
553static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp1_m(void)
554{
555 return 0x1 << 9;
556}
557static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp2_m(void)
558{
559 return 0x1 << 10;
560}
561static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp3_m(void)
562{
563 return 0x1 << 11;
564}
565static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp4_m(void)
566{
567 return 0x1 << 12;
568}
569static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp5_m(void)
570{
571 return 0x1 << 13;
572}
573static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp6_m(void)
574{
575 return 0x1 << 14;
576}
577static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp7_m(void)
578{
579 return 0x1 << 15;
580}
581static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_total_counter_overflow_v(u32 r)
582{
583 return (r >> 24) & 0x1;
584}
585static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r)
586{
587 return (r >> 26) & 0x1;
588}
589static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_reset_task_f(void)
590{
591 return 0x40000000;
592}
593static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_r(void)
594{
595 return 0x0050435c;
596}
597static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_s(void)
598{
599 return 16;
600}
601static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_v(u32 r)
602{
603 return (r >> 0) & 0xffff;
604}
605static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_r(void)
606{
607 return 0x00504360;
608}
609static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_s(void)
610{
611 return 16;
612}
613static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_v(u32 r)
614{
615 return (r >> 0) & 0xffff;
616}
617static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_r(void)
618{
619 return 0x0050436c;
620}
621static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_0_m(void)
622{
623 return 0x1 << 0;
624}
625static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_1_m(void)
626{
627 return 0x1 << 1;
628}
629static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_0_m(void)
630{
631 return 0x1 << 2;
632}
633static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_1_m(void)
634{
635 return 0x1 << 3;
636}
637static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_total_counter_overflow_v(u32 r)
638{
639 return (r >> 8) & 0x1;
640}
641static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r)
642{
643 return (r >> 10) & 0x1;
644}
645static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_reset_task_f(void)
646{
647 return 0x40000000;
648}
649static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_r(void)
650{
651 return 0x00504370;
652}
653static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_s(void)
654{
655 return 16;
656}
657static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_v(u32 r)
658{
659 return (r >> 0) & 0xffff;
660}
661static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_r(void)
662{
663 return 0x00504374;
664}
665static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_s(void)
666{
667 return 16;
668}
669static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_v(u32 r)
670{
671 return (r >> 0) & 0xffff;
672}
673static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_r(void)
674{
675 return 0x00504638;
676}
677static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm0_m(void)
678{
679 return 0x1 << 0;
680}
681static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm1_m(void)
682{
683 return 0x1 << 1;
684}
685static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm0_m(void)
686{
687 return 0x1 << 2;
688}
689static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm1_m(void)
690{
691 return 0x1 << 3;
692}
693static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm0_m(void)
694{
695 return 0x1 << 4;
696}
697static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm1_m(void)
698{
699 return 0x1 << 5;
700}
701static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm0_m(void)
702{
703 return 0x1 << 6;
704}
705static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm1_m(void)
706{
707 return 0x1 << 7;
708}
709static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_total_counter_overflow_v(u32 r)
710{
711 return (r >> 16) & 0x1;
712}
713static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r)
714{
715 return (r >> 18) & 0x1;
716}
717static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_reset_task_f(void)
718{
719 return 0x40000000;
720}
721static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_r(void)
722{
723 return 0x0050463c;
724}
725static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_s(void)
726{
727 return 16;
728}
729static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_v(u32 r)
730{
731 return (r >> 0) & 0xffff;
732}
733static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_r(void)
734{
735 return 0x00504640;
736}
737static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_s(void)
738{
739 return 16;
740}
741static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_v(u32 r)
742{
743 return (r >> 0) & 0xffff;
744}
745static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_r(void)
746{
747 return 0x005042c4;
748}
749static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f(void)
750{
751 return 0x0;
752}
753static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f(void)
754{
755 return 0x1;
756}
757static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f(void)
758{
759 return 0x2;
760}
761static inline u32 gr_gpc0_tpc0_mpc_hww_esr_r(void)
762{
763 return 0x00504430;
764}
765static inline u32 gr_gpc0_tpc0_mpc_hww_esr_reset_trigger_f(void)
766{
767 return 0x40000000;
768}
769static inline u32 gr_gpc0_tpc0_mpc_hww_esr_info_r(void)
770{
771 return 0x00504434;
772}
773static inline u32 gr_gpc0_tpc0_mpc_hww_esr_info_veid_v(u32 r)
774{
775 return (r >> 0) & 0x3f;
776}
777static inline u32 gr_pri_be0_crop_status1_r(void)
778{
779 return 0x00410134;
780}
781static inline u32 gr_pri_bes_crop_status1_r(void)
782{
783 return 0x00408934;
784}
785static inline u32 gr_pri_be0_zrop_status_r(void)
786{
787 return 0x00410048;
788}
789static inline u32 gr_pri_be0_zrop_status2_r(void)
790{
791 return 0x0041004c;
792}
793static inline u32 gr_pri_bes_zrop_status_r(void)
794{
795 return 0x00408848;
796}
797static inline u32 gr_pri_bes_zrop_status2_r(void)
798{
799 return 0x0040884c;
800}
801static inline u32 gr_pipe_bundle_address_r(void)
802{
803 return 0x00400200;
804}
805static inline u32 gr_pipe_bundle_address_value_v(u32 r)
806{
807 return (r >> 0) & 0xffff;
808}
809static inline u32 gr_pipe_bundle_address_veid_f(u32 v)
810{
811 return (v & 0x3f) << 20;
812}
813static inline u32 gr_pipe_bundle_address_veid_w(void)
814{
815 return 0;
816}
817static inline u32 gr_pipe_bundle_data_r(void)
818{
819 return 0x00400204;
820}
821static inline u32 gr_pipe_bundle_config_r(void)
822{
823 return 0x00400208;
824}
825static inline u32 gr_pipe_bundle_config_override_pipe_mode_disabled_f(void)
826{
827 return 0x0;
828}
829static inline u32 gr_pipe_bundle_config_override_pipe_mode_enabled_f(void)
830{
831 return 0x80000000;
832}
833static inline u32 gr_fe_hww_esr_r(void)
834{
835 return 0x00404000;
836}
837static inline u32 gr_fe_hww_esr_reset_active_f(void)
838{
839 return 0x40000000;
840}
841static inline u32 gr_fe_hww_esr_en_enable_f(void)
842{
843 return 0x80000000;
844}
845static inline u32 gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r(void)
846{
847 return 0x00419eac;
848}
849static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_r(void)
850{
851 return 0x0050472c;
852}
853static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_multiple_warp_errors_report_f(void)
854{
855 return 0x4;
856}
857static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_bpt_int_report_f(void)
858{
859 return 0x10;
860}
861static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_bpt_pause_report_f(void)
862{
863 return 0x20;
864}
865static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_single_step_complete_report_f(void)
866{
867 return 0x40;
868}
869static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_error_in_trap_report_f(void)
870{
871 return 0x100;
872}
873static inline u32 gr_gpcs_tpcs_sms_hww_global_esr_r(void)
874{
875 return 0x00419eb4;
876}
877static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_r(void)
878{
879 return 0x00504734;
880}
881static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_m(void)
882{
883 return 0x1 << 4;
884}
885static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f(void)
886{
887 return 0x10;
888}
889static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_m(void)
890{
891 return 0x1 << 5;
892}
893static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_pending_f(void)
894{
895 return 0x20;
896}
897static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_m(void)
898{
899 return 0x1 << 6;
900}
901static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_pending_f(void)
902{
903 return 0x40;
904}
905static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_m(void)
906{
907 return 0x1 << 2;
908}
909static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_pending_f(void)
910{
911 return 0x4;
912}
913static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_m(void)
914{
915 return 0x1 << 8;
916}
917static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_pending_f(void)
918{
919 return 0x100;
920}
921static inline u32 gr_fe_go_idle_timeout_r(void)
922{
923 return 0x00404154;
924}
925static inline u32 gr_fe_go_idle_timeout_count_f(u32 v)
926{
927 return (v & 0xffffffff) << 0;
928}
929static inline u32 gr_fe_go_idle_timeout_count_disabled_f(void)
930{
931 return 0x0;
932}
933static inline u32 gr_fe_go_idle_timeout_count_prod_f(void)
934{
935 return 0x1800;
936}
937static inline u32 gr_fe_object_table_r(u32 i)
938{
939 return 0x00404200 + i*4;
940}
941static inline u32 gr_fe_object_table_nvclass_v(u32 r)
942{
943 return (r >> 0) & 0xffff;
944}
945static inline u32 gr_fe_tpc_fs_r(u32 i)
946{
947 return 0x0040a200 + i*4;
948}
949static inline u32 gr_pri_mme_shadow_raw_index_r(void)
950{
951 return 0x00404488;
952}
953static inline u32 gr_pri_mme_shadow_raw_index_write_trigger_f(void)
954{
955 return 0x80000000;
956}
957static inline u32 gr_pri_mme_shadow_raw_data_r(void)
958{
959 return 0x0040448c;
960}
961static inline u32 gr_mme_hww_esr_r(void)
962{
963 return 0x00404490;
964}
965static inline u32 gr_mme_hww_esr_reset_active_f(void)
966{
967 return 0x40000000;
968}
969static inline u32 gr_mme_hww_esr_en_enable_f(void)
970{
971 return 0x80000000;
972}
973static inline u32 gr_memfmt_hww_esr_r(void)
974{
975 return 0x00404600;
976}
977static inline u32 gr_memfmt_hww_esr_reset_active_f(void)
978{
979 return 0x40000000;
980}
981static inline u32 gr_memfmt_hww_esr_en_enable_f(void)
982{
983 return 0x80000000;
984}
985static inline u32 gr_fecs_cpuctl_r(void)
986{
987 return 0x00409100;
988}
989static inline u32 gr_fecs_cpuctl_startcpu_f(u32 v)
990{
991 return (v & 0x1) << 1;
992}
993static inline u32 gr_fecs_cpuctl_alias_r(void)
994{
995 return 0x00409130;
996}
997static inline u32 gr_fecs_cpuctl_alias_startcpu_f(u32 v)
998{
999 return (v & 0x1) << 1;
1000}
1001static inline u32 gr_fecs_dmactl_r(void)
1002{
1003 return 0x0040910c;
1004}
1005static inline u32 gr_fecs_dmactl_require_ctx_f(u32 v)
1006{
1007 return (v & 0x1) << 0;
1008}
1009static inline u32 gr_fecs_dmactl_dmem_scrubbing_m(void)
1010{
1011 return 0x1 << 1;
1012}
1013static inline u32 gr_fecs_dmactl_imem_scrubbing_m(void)
1014{
1015 return 0x1 << 2;
1016}
1017static inline u32 gr_fecs_os_r(void)
1018{
1019 return 0x00409080;
1020}
1021static inline u32 gr_fecs_idlestate_r(void)
1022{
1023 return 0x0040904c;
1024}
1025static inline u32 gr_fecs_mailbox0_r(void)
1026{
1027 return 0x00409040;
1028}
1029static inline u32 gr_fecs_mailbox1_r(void)
1030{
1031 return 0x00409044;
1032}
1033static inline u32 gr_fecs_irqstat_r(void)
1034{
1035 return 0x00409008;
1036}
1037static inline u32 gr_fecs_irqmode_r(void)
1038{
1039 return 0x0040900c;
1040}
1041static inline u32 gr_fecs_irqmask_r(void)
1042{
1043 return 0x00409018;
1044}
1045static inline u32 gr_fecs_irqdest_r(void)
1046{
1047 return 0x0040901c;
1048}
1049static inline u32 gr_fecs_curctx_r(void)
1050{
1051 return 0x00409050;
1052}
1053static inline u32 gr_fecs_nxtctx_r(void)
1054{
1055 return 0x00409054;
1056}
1057static inline u32 gr_fecs_engctl_r(void)
1058{
1059 return 0x004090a4;
1060}
1061static inline u32 gr_fecs_debug1_r(void)
1062{
1063 return 0x00409090;
1064}
1065static inline u32 gr_fecs_debuginfo_r(void)
1066{
1067 return 0x00409094;
1068}
1069static inline u32 gr_fecs_icd_cmd_r(void)
1070{
1071 return 0x00409200;
1072}
1073static inline u32 gr_fecs_icd_cmd_opc_s(void)
1074{
1075 return 4;
1076}
1077static inline u32 gr_fecs_icd_cmd_opc_f(u32 v)
1078{
1079 return (v & 0xf) << 0;
1080}
1081static inline u32 gr_fecs_icd_cmd_opc_m(void)
1082{
1083 return 0xf << 0;
1084}
1085static inline u32 gr_fecs_icd_cmd_opc_v(u32 r)
1086{
1087 return (r >> 0) & 0xf;
1088}
1089static inline u32 gr_fecs_icd_cmd_opc_rreg_f(void)
1090{
1091 return 0x8;
1092}
1093static inline u32 gr_fecs_icd_cmd_opc_rstat_f(void)
1094{
1095 return 0xe;
1096}
1097static inline u32 gr_fecs_icd_cmd_idx_f(u32 v)
1098{
1099 return (v & 0x1f) << 8;
1100}
1101static inline u32 gr_fecs_icd_rdata_r(void)
1102{
1103 return 0x0040920c;
1104}
1105static inline u32 gr_fecs_imemc_r(u32 i)
1106{
1107 return 0x00409180 + i*16;
1108}
1109static inline u32 gr_fecs_imemc_offs_f(u32 v)
1110{
1111 return (v & 0x3f) << 2;
1112}
1113static inline u32 gr_fecs_imemc_blk_f(u32 v)
1114{
1115 return (v & 0xff) << 8;
1116}
1117static inline u32 gr_fecs_imemc_aincw_f(u32 v)
1118{
1119 return (v & 0x1) << 24;
1120}
1121static inline u32 gr_fecs_imemd_r(u32 i)
1122{
1123 return 0x00409184 + i*16;
1124}
1125static inline u32 gr_fecs_imemt_r(u32 i)
1126{
1127 return 0x00409188 + i*16;
1128}
1129static inline u32 gr_fecs_imemt_tag_f(u32 v)
1130{
1131 return (v & 0xffff) << 0;
1132}
1133static inline u32 gr_fecs_dmemc_r(u32 i)
1134{
1135 return 0x004091c0 + i*8;
1136}
1137static inline u32 gr_fecs_dmemc_offs_s(void)
1138{
1139 return 6;
1140}
1141static inline u32 gr_fecs_dmemc_offs_f(u32 v)
1142{
1143 return (v & 0x3f) << 2;
1144}
1145static inline u32 gr_fecs_dmemc_offs_m(void)
1146{
1147 return 0x3f << 2;
1148}
1149static inline u32 gr_fecs_dmemc_offs_v(u32 r)
1150{
1151 return (r >> 2) & 0x3f;
1152}
1153static inline u32 gr_fecs_dmemc_blk_f(u32 v)
1154{
1155 return (v & 0xff) << 8;
1156}
1157static inline u32 gr_fecs_dmemc_aincw_f(u32 v)
1158{
1159 return (v & 0x1) << 24;
1160}
1161static inline u32 gr_fecs_dmemd_r(u32 i)
1162{
1163 return 0x004091c4 + i*8;
1164}
1165static inline u32 gr_fecs_dmatrfbase_r(void)
1166{
1167 return 0x00409110;
1168}
1169static inline u32 gr_fecs_dmatrfmoffs_r(void)
1170{
1171 return 0x00409114;
1172}
1173static inline u32 gr_fecs_dmatrffboffs_r(void)
1174{
1175 return 0x0040911c;
1176}
1177static inline u32 gr_fecs_dmatrfcmd_r(void)
1178{
1179 return 0x00409118;
1180}
1181static inline u32 gr_fecs_dmatrfcmd_imem_f(u32 v)
1182{
1183 return (v & 0x1) << 4;
1184}
1185static inline u32 gr_fecs_dmatrfcmd_write_f(u32 v)
1186{
1187 return (v & 0x1) << 5;
1188}
1189static inline u32 gr_fecs_dmatrfcmd_size_f(u32 v)
1190{
1191 return (v & 0x7) << 8;
1192}
1193static inline u32 gr_fecs_dmatrfcmd_ctxdma_f(u32 v)
1194{
1195 return (v & 0x7) << 12;
1196}
1197static inline u32 gr_fecs_bootvec_r(void)
1198{
1199 return 0x00409104;
1200}
1201static inline u32 gr_fecs_bootvec_vec_f(u32 v)
1202{
1203 return (v & 0xffffffff) << 0;
1204}
1205static inline u32 gr_fecs_falcon_hwcfg_r(void)
1206{
1207 return 0x00409108;
1208}
1209static inline u32 gr_gpcs_gpccs_falcon_hwcfg_r(void)
1210{
1211 return 0x0041a108;
1212}
1213static inline u32 gr_fecs_falcon_rm_r(void)
1214{
1215 return 0x00409084;
1216}
1217static inline u32 gr_fecs_current_ctx_r(void)
1218{
1219 return 0x00409b00;
1220}
1221static inline u32 gr_fecs_current_ctx_ptr_f(u32 v)
1222{
1223 return (v & 0xfffffff) << 0;
1224}
1225static inline u32 gr_fecs_current_ctx_ptr_v(u32 r)
1226{
1227 return (r >> 0) & 0xfffffff;
1228}
1229static inline u32 gr_fecs_current_ctx_target_s(void)
1230{
1231 return 2;
1232}
1233static inline u32 gr_fecs_current_ctx_target_f(u32 v)
1234{
1235 return (v & 0x3) << 28;
1236}
1237static inline u32 gr_fecs_current_ctx_target_m(void)
1238{
1239 return 0x3 << 28;
1240}
1241static inline u32 gr_fecs_current_ctx_target_v(u32 r)
1242{
1243 return (r >> 28) & 0x3;
1244}
1245static inline u32 gr_fecs_current_ctx_target_vid_mem_f(void)
1246{
1247 return 0x0;
1248}
1249static inline u32 gr_fecs_current_ctx_target_sys_mem_coh_f(void)
1250{
1251 return 0x20000000;
1252}
1253static inline u32 gr_fecs_current_ctx_target_sys_mem_ncoh_f(void)
1254{
1255 return 0x30000000;
1256}
1257static inline u32 gr_fecs_current_ctx_valid_s(void)
1258{
1259 return 1;
1260}
1261static inline u32 gr_fecs_current_ctx_valid_f(u32 v)
1262{
1263 return (v & 0x1) << 31;
1264}
1265static inline u32 gr_fecs_current_ctx_valid_m(void)
1266{
1267 return 0x1 << 31;
1268}
1269static inline u32 gr_fecs_current_ctx_valid_v(u32 r)
1270{
1271 return (r >> 31) & 0x1;
1272}
1273static inline u32 gr_fecs_current_ctx_valid_false_f(void)
1274{
1275 return 0x0;
1276}
1277static inline u32 gr_fecs_method_data_r(void)
1278{
1279 return 0x00409500;
1280}
1281static inline u32 gr_fecs_method_push_r(void)
1282{
1283 return 0x00409504;
1284}
1285static inline u32 gr_fecs_method_push_adr_f(u32 v)
1286{
1287 return (v & 0xfff) << 0;
1288}
1289static inline u32 gr_fecs_method_push_adr_bind_pointer_v(void)
1290{
1291 return 0x00000003;
1292}
1293static inline u32 gr_fecs_method_push_adr_bind_pointer_f(void)
1294{
1295 return 0x3;
1296}
1297static inline u32 gr_fecs_method_push_adr_discover_image_size_v(void)
1298{
1299 return 0x00000010;
1300}
1301static inline u32 gr_fecs_method_push_adr_wfi_golden_save_v(void)
1302{
1303 return 0x00000009;
1304}
1305static inline u32 gr_fecs_method_push_adr_restore_golden_v(void)
1306{
1307 return 0x00000015;
1308}
1309static inline u32 gr_fecs_method_push_adr_discover_zcull_image_size_v(void)
1310{
1311 return 0x00000016;
1312}
1313static inline u32 gr_fecs_method_push_adr_discover_pm_image_size_v(void)
1314{
1315 return 0x00000025;
1316}
1317static inline u32 gr_fecs_method_push_adr_discover_reglist_image_size_v(void)
1318{
1319 return 0x00000030;
1320}
1321static inline u32 gr_fecs_method_push_adr_set_reglist_bind_instance_v(void)
1322{
1323 return 0x00000031;
1324}
1325static inline u32 gr_fecs_method_push_adr_set_reglist_virtual_address_v(void)
1326{
1327 return 0x00000032;
1328}
1329static inline u32 gr_fecs_method_push_adr_stop_ctxsw_v(void)
1330{
1331 return 0x00000038;
1332}
1333static inline u32 gr_fecs_method_push_adr_start_ctxsw_v(void)
1334{
1335 return 0x00000039;
1336}
1337static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void)
1338{
1339 return 0x21;
1340}
1341static inline u32 gr_fecs_method_push_adr_discover_preemption_image_size_v(void)
1342{
1343 return 0x0000001a;
1344}
1345static inline u32 gr_fecs_method_push_adr_halt_pipeline_v(void)
1346{
1347 return 0x00000004;
1348}
1349static inline u32 gr_fecs_method_push_adr_configure_interrupt_completion_option_v(void)
1350{
1351 return 0x0000003a;
1352}
1353static inline u32 gr_fecs_host_int_status_r(void)
1354{
1355 return 0x00409c18;
1356}
1357static inline u32 gr_fecs_host_int_status_fault_during_ctxsw_f(u32 v)
1358{
1359 return (v & 0x1) << 16;
1360}
1361static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v)
1362{
1363 return (v & 0x1) << 17;
1364}
1365static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v)
1366{
1367 return (v & 0x1) << 18;
1368}
1369static inline u32 gr_fecs_host_int_status_ctxsw_intr_f(u32 v)
1370{
1371 return (v & 0xffff) << 0;
1372}
1373static inline u32 gr_fecs_host_int_clear_r(void)
1374{
1375 return 0x00409c20;
1376}
1377static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_f(u32 v)
1378{
1379 return (v & 0x1) << 1;
1380}
1381static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_clear_f(void)
1382{
1383 return 0x2;
1384}
1385static inline u32 gr_fecs_host_int_enable_r(void)
1386{
1387 return 0x00409c24;
1388}
1389static inline u32 gr_fecs_host_int_enable_ctxsw_intr1_enable_f(void)
1390{
1391 return 0x2;
1392}
1393static inline u32 gr_fecs_host_int_enable_fault_during_ctxsw_enable_f(void)
1394{
1395 return 0x10000;
1396}
1397static inline u32 gr_fecs_host_int_enable_umimp_firmware_method_enable_f(void)
1398{
1399 return 0x20000;
1400}
1401static inline u32 gr_fecs_host_int_enable_umimp_illegal_method_enable_f(void)
1402{
1403 return 0x40000;
1404}
1405static inline u32 gr_fecs_host_int_enable_watchdog_enable_f(void)
1406{
1407 return 0x80000;
1408}
1409static inline u32 gr_fecs_ctxsw_reset_ctl_r(void)
1410{
1411 return 0x00409614;
1412}
1413static inline u32 gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f(void)
1414{
1415 return 0x0;
1416}
1417static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f(void)
1418{
1419 return 0x0;
1420}
1421static inline u32 gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f(void)
1422{
1423 return 0x0;
1424}
1425static inline u32 gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f(void)
1426{
1427 return 0x10;
1428}
1429static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f(void)
1430{
1431 return 0x20;
1432}
1433static inline u32 gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f(void)
1434{
1435 return 0x40;
1436}
1437static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f(void)
1438{
1439 return 0x0;
1440}
1441static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f(void)
1442{
1443 return 0x100;
1444}
1445static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f(void)
1446{
1447 return 0x0;
1448}
1449static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f(void)
1450{
1451 return 0x200;
1452}
1453static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_s(void)
1454{
1455 return 1;
1456}
1457static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_f(u32 v)
1458{
1459 return (v & 0x1) << 10;
1460}
1461static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_m(void)
1462{
1463 return 0x1 << 10;
1464}
1465static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_v(u32 r)
1466{
1467 return (r >> 10) & 0x1;
1468}
1469static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f(void)
1470{
1471 return 0x0;
1472}
1473static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f(void)
1474{
1475 return 0x400;
1476}
1477static inline u32 gr_fecs_ctx_state_store_major_rev_id_r(void)
1478{
1479 return 0x0040960c;
1480}
1481static inline u32 gr_fecs_ctxsw_mailbox_r(u32 i)
1482{
1483 return 0x00409800 + i*4;
1484}
1485static inline u32 gr_fecs_ctxsw_mailbox__size_1_v(void)
1486{
1487 return 0x00000010;
1488}
1489static inline u32 gr_fecs_ctxsw_mailbox_value_f(u32 v)
1490{
1491 return (v & 0xffffffff) << 0;
1492}
1493static inline u32 gr_fecs_ctxsw_mailbox_value_pass_v(void)
1494{
1495 return 0x00000001;
1496}
1497static inline u32 gr_fecs_ctxsw_mailbox_value_fail_v(void)
1498{
1499 return 0x00000002;
1500}
1501static inline u32 gr_fecs_ctxsw_mailbox_set_r(u32 i)
1502{
1503 return 0x004098c0 + i*4;
1504}
1505static inline u32 gr_fecs_ctxsw_mailbox_set_value_f(u32 v)
1506{
1507 return (v & 0xffffffff) << 0;
1508}
1509static inline u32 gr_fecs_ctxsw_mailbox_clear_r(u32 i)
1510{
1511 return 0x00409840 + i*4;
1512}
1513static inline u32 gr_fecs_ctxsw_mailbox_clear_value_f(u32 v)
1514{
1515 return (v & 0xffffffff) << 0;
1516}
1517static inline u32 gr_fecs_fs_r(void)
1518{
1519 return 0x00409604;
1520}
1521static inline u32 gr_fecs_fs_num_available_gpcs_s(void)
1522{
1523 return 5;
1524}
1525static inline u32 gr_fecs_fs_num_available_gpcs_f(u32 v)
1526{
1527 return (v & 0x1f) << 0;
1528}
1529static inline u32 gr_fecs_fs_num_available_gpcs_m(void)
1530{
1531 return 0x1f << 0;
1532}
1533static inline u32 gr_fecs_fs_num_available_gpcs_v(u32 r)
1534{
1535 return (r >> 0) & 0x1f;
1536}
1537static inline u32 gr_fecs_fs_num_available_fbps_s(void)
1538{
1539 return 5;
1540}
1541static inline u32 gr_fecs_fs_num_available_fbps_f(u32 v)
1542{
1543 return (v & 0x1f) << 16;
1544}
1545static inline u32 gr_fecs_fs_num_available_fbps_m(void)
1546{
1547 return 0x1f << 16;
1548}
1549static inline u32 gr_fecs_fs_num_available_fbps_v(u32 r)
1550{
1551 return (r >> 16) & 0x1f;
1552}
1553static inline u32 gr_fecs_cfg_r(void)
1554{
1555 return 0x00409620;
1556}
1557static inline u32 gr_fecs_cfg_imem_sz_v(u32 r)
1558{
1559 return (r >> 0) & 0xff;
1560}
1561static inline u32 gr_fecs_rc_lanes_r(void)
1562{
1563 return 0x00409880;
1564}
1565static inline u32 gr_fecs_rc_lanes_num_chains_s(void)
1566{
1567 return 6;
1568}
1569static inline u32 gr_fecs_rc_lanes_num_chains_f(u32 v)
1570{
1571 return (v & 0x3f) << 0;
1572}
1573static inline u32 gr_fecs_rc_lanes_num_chains_m(void)
1574{
1575 return 0x3f << 0;
1576}
1577static inline u32 gr_fecs_rc_lanes_num_chains_v(u32 r)
1578{
1579 return (r >> 0) & 0x3f;
1580}
1581static inline u32 gr_fecs_ctxsw_status_1_r(void)
1582{
1583 return 0x00409400;
1584}
1585static inline u32 gr_fecs_ctxsw_status_1_arb_busy_s(void)
1586{
1587 return 1;
1588}
1589static inline u32 gr_fecs_ctxsw_status_1_arb_busy_f(u32 v)
1590{
1591 return (v & 0x1) << 12;
1592}
1593static inline u32 gr_fecs_ctxsw_status_1_arb_busy_m(void)
1594{
1595 return 0x1 << 12;
1596}
1597static inline u32 gr_fecs_ctxsw_status_1_arb_busy_v(u32 r)
1598{
1599 return (r >> 12) & 0x1;
1600}
1601static inline u32 gr_fecs_arb_ctx_adr_r(void)
1602{
1603 return 0x00409a24;
1604}
1605static inline u32 gr_fecs_new_ctx_r(void)
1606{
1607 return 0x00409b04;
1608}
1609static inline u32 gr_fecs_new_ctx_ptr_s(void)
1610{
1611 return 28;
1612}
1613static inline u32 gr_fecs_new_ctx_ptr_f(u32 v)
1614{
1615 return (v & 0xfffffff) << 0;
1616}
1617static inline u32 gr_fecs_new_ctx_ptr_m(void)
1618{
1619 return 0xfffffff << 0;
1620}
1621static inline u32 gr_fecs_new_ctx_ptr_v(u32 r)
1622{
1623 return (r >> 0) & 0xfffffff;
1624}
1625static inline u32 gr_fecs_new_ctx_target_s(void)
1626{
1627 return 2;
1628}
1629static inline u32 gr_fecs_new_ctx_target_f(u32 v)
1630{
1631 return (v & 0x3) << 28;
1632}
1633static inline u32 gr_fecs_new_ctx_target_m(void)
1634{
1635 return 0x3 << 28;
1636}
1637static inline u32 gr_fecs_new_ctx_target_v(u32 r)
1638{
1639 return (r >> 28) & 0x3;
1640}
1641static inline u32 gr_fecs_new_ctx_valid_s(void)
1642{
1643 return 1;
1644}
1645static inline u32 gr_fecs_new_ctx_valid_f(u32 v)
1646{
1647 return (v & 0x1) << 31;
1648}
1649static inline u32 gr_fecs_new_ctx_valid_m(void)
1650{
1651 return 0x1 << 31;
1652}
1653static inline u32 gr_fecs_new_ctx_valid_v(u32 r)
1654{
1655 return (r >> 31) & 0x1;
1656}
1657static inline u32 gr_fecs_arb_ctx_ptr_r(void)
1658{
1659 return 0x00409a0c;
1660}
1661static inline u32 gr_fecs_arb_ctx_ptr_ptr_s(void)
1662{
1663 return 28;
1664}
1665static inline u32 gr_fecs_arb_ctx_ptr_ptr_f(u32 v)
1666{
1667 return (v & 0xfffffff) << 0;
1668}
1669static inline u32 gr_fecs_arb_ctx_ptr_ptr_m(void)
1670{
1671 return 0xfffffff << 0;
1672}
1673static inline u32 gr_fecs_arb_ctx_ptr_ptr_v(u32 r)
1674{
1675 return (r >> 0) & 0xfffffff;
1676}
1677static inline u32 gr_fecs_arb_ctx_ptr_target_s(void)
1678{
1679 return 2;
1680}
1681static inline u32 gr_fecs_arb_ctx_ptr_target_f(u32 v)
1682{
1683 return (v & 0x3) << 28;
1684}
1685static inline u32 gr_fecs_arb_ctx_ptr_target_m(void)
1686{
1687 return 0x3 << 28;
1688}
1689static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r)
1690{
1691 return (r >> 28) & 0x3;
1692}
1693static inline u32 gr_fecs_arb_ctx_cmd_r(void)
1694{
1695 return 0x00409a10;
1696}
1697static inline u32 gr_fecs_arb_ctx_cmd_cmd_s(void)
1698{
1699 return 5;
1700}
1701static inline u32 gr_fecs_arb_ctx_cmd_cmd_f(u32 v)
1702{
1703 return (v & 0x1f) << 0;
1704}
1705static inline u32 gr_fecs_arb_ctx_cmd_cmd_m(void)
1706{
1707 return 0x1f << 0;
1708}
1709static inline u32 gr_fecs_arb_ctx_cmd_cmd_v(u32 r)
1710{
1711 return (r >> 0) & 0x1f;
1712}
1713static inline u32 gr_fecs_ctxsw_status_fe_0_r(void)
1714{
1715 return 0x00409c00;
1716}
1717static inline u32 gr_gpc0_gpccs_ctxsw_status_gpc_0_r(void)
1718{
1719 return 0x00502c04;
1720}
1721static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void)
1722{
1723 return 0x00502400;
1724}
1725static inline u32 gr_fecs_ctxsw_idlestate_r(void)
1726{
1727 return 0x00409420;
1728}
1729static inline u32 gr_fecs_feature_override_ecc_r(void)
1730{
1731 return 0x00409658;
1732}
1733static inline u32 gr_fecs_feature_override_ecc_sm_lrf_override_v(u32 r)
1734{
1735 return (r >> 3) & 0x1;
1736}
1737static inline u32 gr_fecs_feature_override_ecc_ltc_override_v(u32 r)
1738{
1739 return (r >> 15) & 0x1;
1740}
1741static inline u32 gr_fecs_feature_override_ecc_sm_lrf_v(u32 r)
1742{
1743 return (r >> 0) & 0x1;
1744}
1745static inline u32 gr_fecs_feature_override_ecc_ltc_v(u32 r)
1746{
1747 return (r >> 12) & 0x1;
1748}
1749static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void)
1750{
1751 return 0x00502420;
1752}
1753static inline u32 gr_rstr2d_gpc_map_r(u32 i)
1754{
1755 return 0x0040780c + i*4;
1756}
1757static inline u32 gr_rstr2d_map_table_cfg_r(void)
1758{
1759 return 0x004078bc;
1760}
1761static inline u32 gr_rstr2d_map_table_cfg_row_offset_f(u32 v)
1762{
1763 return (v & 0xff) << 0;
1764}
1765static inline u32 gr_rstr2d_map_table_cfg_num_entries_f(u32 v)
1766{
1767 return (v & 0xff) << 8;
1768}
1769static inline u32 gr_pd_hww_esr_r(void)
1770{
1771 return 0x00406018;
1772}
1773static inline u32 gr_pd_hww_esr_reset_active_f(void)
1774{
1775 return 0x40000000;
1776}
1777static inline u32 gr_pd_hww_esr_en_enable_f(void)
1778{
1779 return 0x80000000;
1780}
1781static inline u32 gr_pd_num_tpc_per_gpc_r(u32 i)
1782{
1783 return 0x00406028 + i*4;
1784}
1785static inline u32 gr_pd_num_tpc_per_gpc__size_1_v(void)
1786{
1787 return 0x00000004;
1788}
1789static inline u32 gr_pd_num_tpc_per_gpc_count0_f(u32 v)
1790{
1791 return (v & 0xf) << 0;
1792}
1793static inline u32 gr_pd_num_tpc_per_gpc_count1_f(u32 v)
1794{
1795 return (v & 0xf) << 4;
1796}
1797static inline u32 gr_pd_num_tpc_per_gpc_count2_f(u32 v)
1798{
1799 return (v & 0xf) << 8;
1800}
1801static inline u32 gr_pd_num_tpc_per_gpc_count3_f(u32 v)
1802{
1803 return (v & 0xf) << 12;
1804}
1805static inline u32 gr_pd_num_tpc_per_gpc_count4_f(u32 v)
1806{
1807 return (v & 0xf) << 16;
1808}
1809static inline u32 gr_pd_num_tpc_per_gpc_count5_f(u32 v)
1810{
1811 return (v & 0xf) << 20;
1812}
1813static inline u32 gr_pd_num_tpc_per_gpc_count6_f(u32 v)
1814{
1815 return (v & 0xf) << 24;
1816}
1817static inline u32 gr_pd_num_tpc_per_gpc_count7_f(u32 v)
1818{
1819 return (v & 0xf) << 28;
1820}
1821static inline u32 gr_pd_ab_dist_cfg0_r(void)
1822{
1823 return 0x004064c0;
1824}
1825static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_en_f(void)
1826{
1827 return 0x80000000;
1828}
1829static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_dis_f(void)
1830{
1831 return 0x0;
1832}
1833static inline u32 gr_pd_ab_dist_cfg1_r(void)
1834{
1835 return 0x004064c4;
1836}
1837static inline u32 gr_pd_ab_dist_cfg1_max_batches_init_f(void)
1838{
1839 return 0xffff;
1840}
1841static inline u32 gr_pd_ab_dist_cfg1_max_output_f(u32 v)
1842{
1843 return (v & 0xffff) << 16;
1844}
1845static inline u32 gr_pd_ab_dist_cfg1_max_output_granularity_v(void)
1846{
1847 return 0x00000080;
1848}
1849static inline u32 gr_pd_ab_dist_cfg2_r(void)
1850{
1851 return 0x004064c8;
1852}
1853static inline u32 gr_pd_ab_dist_cfg2_token_limit_f(u32 v)
1854{
1855 return (v & 0x1fff) << 0;
1856}
1857static inline u32 gr_pd_ab_dist_cfg2_token_limit_init_v(void)
1858{
1859 return 0x00001680;
1860}
1861static inline u32 gr_pd_ab_dist_cfg2_state_limit_f(u32 v)
1862{
1863 return (v & 0x1fff) << 16;
1864}
1865static inline u32 gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(void)
1866{
1867 return 0x00000020;
1868}
1869static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void)
1870{
1871 return 0x00001680;
1872}
1873static inline u32 gr_pd_dist_skip_table_r(u32 i)
1874{
1875 return 0x004064d0 + i*4;
1876}
1877static inline u32 gr_pd_dist_skip_table__size_1_v(void)
1878{
1879 return 0x00000008;
1880}
1881static inline u32 gr_pd_dist_skip_table_gpc_4n0_mask_f(u32 v)
1882{
1883 return (v & 0xff) << 0;
1884}
1885static inline u32 gr_pd_dist_skip_table_gpc_4n1_mask_f(u32 v)
1886{
1887 return (v & 0xff) << 8;
1888}
1889static inline u32 gr_pd_dist_skip_table_gpc_4n2_mask_f(u32 v)
1890{
1891 return (v & 0xff) << 16;
1892}
1893static inline u32 gr_pd_dist_skip_table_gpc_4n3_mask_f(u32 v)
1894{
1895 return (v & 0xff) << 24;
1896}
1897static inline u32 gr_ds_debug_r(void)
1898{
1899 return 0x00405800;
1900}
1901static inline u32 gr_ds_debug_timeslice_mode_disable_f(void)
1902{
1903 return 0x0;
1904}
1905static inline u32 gr_ds_debug_timeslice_mode_enable_f(void)
1906{
1907 return 0x8000000;
1908}
1909static inline u32 gr_ds_zbc_color_r_r(void)
1910{
1911 return 0x00405804;
1912}
1913static inline u32 gr_ds_zbc_color_r_val_f(u32 v)
1914{
1915 return (v & 0xffffffff) << 0;
1916}
1917static inline u32 gr_ds_zbc_color_g_r(void)
1918{
1919 return 0x00405808;
1920}
1921static inline u32 gr_ds_zbc_color_g_val_f(u32 v)
1922{
1923 return (v & 0xffffffff) << 0;
1924}
1925static inline u32 gr_ds_zbc_color_b_r(void)
1926{
1927 return 0x0040580c;
1928}
1929static inline u32 gr_ds_zbc_color_b_val_f(u32 v)
1930{
1931 return (v & 0xffffffff) << 0;
1932}
1933static inline u32 gr_ds_zbc_color_a_r(void)
1934{
1935 return 0x00405810;
1936}
1937static inline u32 gr_ds_zbc_color_a_val_f(u32 v)
1938{
1939 return (v & 0xffffffff) << 0;
1940}
1941static inline u32 gr_ds_zbc_color_fmt_r(void)
1942{
1943 return 0x00405814;
1944}
1945static inline u32 gr_ds_zbc_color_fmt_val_f(u32 v)
1946{
1947 return (v & 0x7f) << 0;
1948}
1949static inline u32 gr_ds_zbc_color_fmt_val_invalid_f(void)
1950{
1951 return 0x0;
1952}
1953static inline u32 gr_ds_zbc_color_fmt_val_zero_v(void)
1954{
1955 return 0x00000001;
1956}
1957static inline u32 gr_ds_zbc_color_fmt_val_unorm_one_v(void)
1958{
1959 return 0x00000002;
1960}
1961static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void)
1962{
1963 return 0x00000004;
1964}
1965static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void)
1966{
1967 return 0x00000028;
1968}
1969static inline u32 gr_ds_zbc_z_r(void)
1970{
1971 return 0x00405818;
1972}
1973static inline u32 gr_ds_zbc_z_val_s(void)
1974{
1975 return 32;
1976}
1977static inline u32 gr_ds_zbc_z_val_f(u32 v)
1978{
1979 return (v & 0xffffffff) << 0;
1980}
1981static inline u32 gr_ds_zbc_z_val_m(void)
1982{
1983 return 0xffffffff << 0;
1984}
1985static inline u32 gr_ds_zbc_z_val_v(u32 r)
1986{
1987 return (r >> 0) & 0xffffffff;
1988}
1989static inline u32 gr_ds_zbc_z_val__init_v(void)
1990{
1991 return 0x00000000;
1992}
1993static inline u32 gr_ds_zbc_z_val__init_f(void)
1994{
1995 return 0x0;
1996}
1997static inline u32 gr_ds_zbc_z_fmt_r(void)
1998{
1999 return 0x0040581c;
2000}
2001static inline u32 gr_ds_zbc_z_fmt_val_f(u32 v)
2002{
2003 return (v & 0x1) << 0;
2004}
2005static inline u32 gr_ds_zbc_z_fmt_val_invalid_f(void)
2006{
2007 return 0x0;
2008}
2009static inline u32 gr_ds_zbc_z_fmt_val_fp32_v(void)
2010{
2011 return 0x00000001;
2012}
2013static inline u32 gr_ds_zbc_tbl_index_r(void)
2014{
2015 return 0x00405820;
2016}
2017static inline u32 gr_ds_zbc_tbl_index_val_f(u32 v)
2018{
2019 return (v & 0xf) << 0;
2020}
2021static inline u32 gr_ds_zbc_tbl_ld_r(void)
2022{
2023 return 0x00405824;
2024}
2025static inline u32 gr_ds_zbc_tbl_ld_select_c_f(void)
2026{
2027 return 0x0;
2028}
2029static inline u32 gr_ds_zbc_tbl_ld_select_z_f(void)
2030{
2031 return 0x1;
2032}
2033static inline u32 gr_ds_zbc_tbl_ld_action_write_f(void)
2034{
2035 return 0x0;
2036}
2037static inline u32 gr_ds_zbc_tbl_ld_trigger_active_f(void)
2038{
2039 return 0x4;
2040}
2041static inline u32 gr_ds_tga_constraintlogic_beta_r(void)
2042{
2043 return 0x00405830;
2044}
2045static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v)
2046{
2047 return (v & 0x3fffff) << 0;
2048}
2049static inline u32 gr_ds_tga_constraintlogic_alpha_r(void)
2050{
2051 return 0x0040585c;
2052}
2053static inline u32 gr_ds_tga_constraintlogic_alpha_cbsize_f(u32 v)
2054{
2055 return (v & 0xffff) << 0;
2056}
2057static inline u32 gr_ds_hww_esr_r(void)
2058{
2059 return 0x00405840;
2060}
2061static inline u32 gr_ds_hww_esr_reset_s(void)
2062{
2063 return 1;
2064}
2065static inline u32 gr_ds_hww_esr_reset_f(u32 v)
2066{
2067 return (v & 0x1) << 30;
2068}
2069static inline u32 gr_ds_hww_esr_reset_m(void)
2070{
2071 return 0x1 << 30;
2072}
2073static inline u32 gr_ds_hww_esr_reset_v(u32 r)
2074{
2075 return (r >> 30) & 0x1;
2076}
2077static inline u32 gr_ds_hww_esr_reset_task_v(void)
2078{
2079 return 0x00000001;
2080}
2081static inline u32 gr_ds_hww_esr_reset_task_f(void)
2082{
2083 return 0x40000000;
2084}
2085static inline u32 gr_ds_hww_esr_en_enabled_f(void)
2086{
2087 return 0x80000000;
2088}
2089static inline u32 gr_ds_hww_esr_2_r(void)
2090{
2091 return 0x00405848;
2092}
2093static inline u32 gr_ds_hww_esr_2_reset_s(void)
2094{
2095 return 1;
2096}
2097static inline u32 gr_ds_hww_esr_2_reset_f(u32 v)
2098{
2099 return (v & 0x1) << 30;
2100}
2101static inline u32 gr_ds_hww_esr_2_reset_m(void)
2102{
2103 return 0x1 << 30;
2104}
2105static inline u32 gr_ds_hww_esr_2_reset_v(u32 r)
2106{
2107 return (r >> 30) & 0x1;
2108}
2109static inline u32 gr_ds_hww_esr_2_reset_task_v(void)
2110{
2111 return 0x00000001;
2112}
2113static inline u32 gr_ds_hww_esr_2_reset_task_f(void)
2114{
2115 return 0x40000000;
2116}
2117static inline u32 gr_ds_hww_esr_2_en_enabled_f(void)
2118{
2119 return 0x80000000;
2120}
2121static inline u32 gr_ds_hww_report_mask_r(void)
2122{
2123 return 0x00405844;
2124}
2125static inline u32 gr_ds_hww_report_mask_sph0_err_report_f(void)
2126{
2127 return 0x1;
2128}
2129static inline u32 gr_ds_hww_report_mask_sph1_err_report_f(void)
2130{
2131 return 0x2;
2132}
2133static inline u32 gr_ds_hww_report_mask_sph2_err_report_f(void)
2134{
2135 return 0x4;
2136}
2137static inline u32 gr_ds_hww_report_mask_sph3_err_report_f(void)
2138{
2139 return 0x8;
2140}
2141static inline u32 gr_ds_hww_report_mask_sph4_err_report_f(void)
2142{
2143 return 0x10;
2144}
2145static inline u32 gr_ds_hww_report_mask_sph5_err_report_f(void)
2146{
2147 return 0x20;
2148}
2149static inline u32 gr_ds_hww_report_mask_sph6_err_report_f(void)
2150{
2151 return 0x40;
2152}
2153static inline u32 gr_ds_hww_report_mask_sph7_err_report_f(void)
2154{
2155 return 0x80;
2156}
2157static inline u32 gr_ds_hww_report_mask_sph8_err_report_f(void)
2158{
2159 return 0x100;
2160}
2161static inline u32 gr_ds_hww_report_mask_sph9_err_report_f(void)
2162{
2163 return 0x200;
2164}
2165static inline u32 gr_ds_hww_report_mask_sph10_err_report_f(void)
2166{
2167 return 0x400;
2168}
2169static inline u32 gr_ds_hww_report_mask_sph11_err_report_f(void)
2170{
2171 return 0x800;
2172}
2173static inline u32 gr_ds_hww_report_mask_sph12_err_report_f(void)
2174{
2175 return 0x1000;
2176}
2177static inline u32 gr_ds_hww_report_mask_sph13_err_report_f(void)
2178{
2179 return 0x2000;
2180}
2181static inline u32 gr_ds_hww_report_mask_sph14_err_report_f(void)
2182{
2183 return 0x4000;
2184}
2185static inline u32 gr_ds_hww_report_mask_sph15_err_report_f(void)
2186{
2187 return 0x8000;
2188}
2189static inline u32 gr_ds_hww_report_mask_sph16_err_report_f(void)
2190{
2191 return 0x10000;
2192}
2193static inline u32 gr_ds_hww_report_mask_sph17_err_report_f(void)
2194{
2195 return 0x20000;
2196}
2197static inline u32 gr_ds_hww_report_mask_sph18_err_report_f(void)
2198{
2199 return 0x40000;
2200}
2201static inline u32 gr_ds_hww_report_mask_sph19_err_report_f(void)
2202{
2203 return 0x80000;
2204}
2205static inline u32 gr_ds_hww_report_mask_sph20_err_report_f(void)
2206{
2207 return 0x100000;
2208}
2209static inline u32 gr_ds_hww_report_mask_sph21_err_report_f(void)
2210{
2211 return 0x200000;
2212}
2213static inline u32 gr_ds_hww_report_mask_sph22_err_report_f(void)
2214{
2215 return 0x400000;
2216}
2217static inline u32 gr_ds_hww_report_mask_sph23_err_report_f(void)
2218{
2219 return 0x800000;
2220}
2221static inline u32 gr_ds_hww_report_mask_2_r(void)
2222{
2223 return 0x0040584c;
2224}
2225static inline u32 gr_ds_hww_report_mask_2_sph24_err_report_f(void)
2226{
2227 return 0x1;
2228}
2229static inline u32 gr_ds_num_tpc_per_gpc_r(u32 i)
2230{
2231 return 0x00405870 + i*4;
2232}
2233static inline u32 gr_scc_bundle_cb_base_r(void)
2234{
2235 return 0x00408004;
2236}
2237static inline u32 gr_scc_bundle_cb_base_addr_39_8_f(u32 v)
2238{
2239 return (v & 0xffffffff) << 0;
2240}
2241static inline u32 gr_scc_bundle_cb_base_addr_39_8_align_bits_v(void)
2242{
2243 return 0x00000008;
2244}
2245static inline u32 gr_scc_bundle_cb_size_r(void)
2246{
2247 return 0x00408008;
2248}
2249static inline u32 gr_scc_bundle_cb_size_div_256b_f(u32 v)
2250{
2251 return (v & 0x7ff) << 0;
2252}
2253static inline u32 gr_scc_bundle_cb_size_div_256b__prod_v(void)
2254{
2255 return 0x00000030;
2256}
2257static inline u32 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(void)
2258{
2259 return 0x00000100;
2260}
2261static inline u32 gr_scc_bundle_cb_size_valid_false_v(void)
2262{
2263 return 0x00000000;
2264}
2265static inline u32 gr_scc_bundle_cb_size_valid_false_f(void)
2266{
2267 return 0x0;
2268}
2269static inline u32 gr_scc_bundle_cb_size_valid_true_f(void)
2270{
2271 return 0x80000000;
2272}
2273static inline u32 gr_scc_pagepool_base_r(void)
2274{
2275 return 0x0040800c;
2276}
2277static inline u32 gr_scc_pagepool_base_addr_39_8_f(u32 v)
2278{
2279 return (v & 0xffffffff) << 0;
2280}
2281static inline u32 gr_scc_pagepool_base_addr_39_8_align_bits_v(void)
2282{
2283 return 0x00000008;
2284}
2285static inline u32 gr_scc_pagepool_r(void)
2286{
2287 return 0x00408010;
2288}
2289static inline u32 gr_scc_pagepool_total_pages_f(u32 v)
2290{
2291 return (v & 0x3ff) << 0;
2292}
2293static inline u32 gr_scc_pagepool_total_pages_hwmax_v(void)
2294{
2295 return 0x00000000;
2296}
2297static inline u32 gr_scc_pagepool_total_pages_hwmax_value_v(void)
2298{
2299 return 0x00000200;
2300}
2301static inline u32 gr_scc_pagepool_total_pages_byte_granularity_v(void)
2302{
2303 return 0x00000100;
2304}
2305static inline u32 gr_scc_pagepool_max_valid_pages_s(void)
2306{
2307 return 10;
2308}
2309static inline u32 gr_scc_pagepool_max_valid_pages_f(u32 v)
2310{
2311 return (v & 0x3ff) << 10;
2312}
2313static inline u32 gr_scc_pagepool_max_valid_pages_m(void)
2314{
2315 return 0x3ff << 10;
2316}
2317static inline u32 gr_scc_pagepool_max_valid_pages_v(u32 r)
2318{
2319 return (r >> 10) & 0x3ff;
2320}
2321static inline u32 gr_scc_pagepool_valid_true_f(void)
2322{
2323 return 0x80000000;
2324}
2325static inline u32 gr_scc_init_r(void)
2326{
2327 return 0x0040802c;
2328}
2329static inline u32 gr_scc_init_ram_trigger_f(void)
2330{
2331 return 0x1;
2332}
2333static inline u32 gr_scc_hww_esr_r(void)
2334{
2335 return 0x00408030;
2336}
2337static inline u32 gr_scc_hww_esr_reset_active_f(void)
2338{
2339 return 0x40000000;
2340}
2341static inline u32 gr_scc_hww_esr_en_enable_f(void)
2342{
2343 return 0x80000000;
2344}
2345static inline u32 gr_sked_hww_esr_r(void)
2346{
2347 return 0x00407020;
2348}
2349static inline u32 gr_sked_hww_esr_reset_active_f(void)
2350{
2351 return 0x40000000;
2352}
2353static inline u32 gr_sked_hww_esr_en_r(void)
2354{
2355 return 0x00407024;
2356}
2357static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_m(void)
2358{
2359 return 0x1 << 25;
2360}
2361static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_disabled_f(void)
2362{
2363 return 0x0;
2364}
2365static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_enabled_f(void)
2366{
2367 return 0x2000000;
2368}
2369static inline u32 gr_cwd_fs_r(void)
2370{
2371 return 0x00405b00;
2372}
2373static inline u32 gr_cwd_fs_num_gpcs_f(u32 v)
2374{
2375 return (v & 0xff) << 0;
2376}
2377static inline u32 gr_cwd_fs_num_tpcs_f(u32 v)
2378{
2379 return (v & 0xff) << 8;
2380}
2381static inline u32 gr_cwd_gpc_tpc_id_r(u32 i)
2382{
2383 return 0x00405b60 + i*4;
2384}
2385static inline u32 gr_cwd_gpc_tpc_id_tpc0_s(void)
2386{
2387 return 4;
2388}
2389static inline u32 gr_cwd_gpc_tpc_id_tpc0_f(u32 v)
2390{
2391 return (v & 0xf) << 0;
2392}
2393static inline u32 gr_cwd_gpc_tpc_id_gpc0_s(void)
2394{
2395 return 4;
2396}
2397static inline u32 gr_cwd_gpc_tpc_id_gpc0_f(u32 v)
2398{
2399 return (v & 0xf) << 4;
2400}
2401static inline u32 gr_cwd_gpc_tpc_id_tpc1_f(u32 v)
2402{
2403 return (v & 0xf) << 8;
2404}
2405static inline u32 gr_cwd_sm_id_r(u32 i)
2406{
2407 return 0x00405ba0 + i*4;
2408}
2409static inline u32 gr_cwd_sm_id__size_1_v(void)
2410{
2411 return 0x00000010;
2412}
2413static inline u32 gr_cwd_sm_id_tpc0_f(u32 v)
2414{
2415 return (v & 0xff) << 0;
2416}
2417static inline u32 gr_cwd_sm_id_tpc1_f(u32 v)
2418{
2419 return (v & 0xff) << 8;
2420}
2421static inline u32 gr_gpc0_fs_gpc_r(void)
2422{
2423 return 0x00502608;
2424}
2425static inline u32 gr_gpc0_fs_gpc_num_available_tpcs_v(u32 r)
2426{
2427 return (r >> 0) & 0x1f;
2428}
2429static inline u32 gr_gpc0_fs_gpc_num_available_zculls_v(u32 r)
2430{
2431 return (r >> 16) & 0x1f;
2432}
2433static inline u32 gr_gpc0_cfg_r(void)
2434{
2435 return 0x00502620;
2436}
2437static inline u32 gr_gpc0_cfg_imem_sz_v(u32 r)
2438{
2439 return (r >> 0) & 0xff;
2440}
2441static inline u32 gr_gpccs_rc_lanes_r(void)
2442{
2443 return 0x00502880;
2444}
2445static inline u32 gr_gpccs_rc_lanes_num_chains_s(void)
2446{
2447 return 6;
2448}
2449static inline u32 gr_gpccs_rc_lanes_num_chains_f(u32 v)
2450{
2451 return (v & 0x3f) << 0;
2452}
2453static inline u32 gr_gpccs_rc_lanes_num_chains_m(void)
2454{
2455 return 0x3f << 0;
2456}
2457static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r)
2458{
2459 return (r >> 0) & 0x3f;
2460}
2461static inline u32 gr_gpccs_rc_lane_size_r(void)
2462{
2463 return 0x00502910;
2464}
2465static inline u32 gr_gpccs_rc_lane_size_v_s(void)
2466{
2467 return 24;
2468}
2469static inline u32 gr_gpccs_rc_lane_size_v_f(u32 v)
2470{
2471 return (v & 0xffffff) << 0;
2472}
2473static inline u32 gr_gpccs_rc_lane_size_v_m(void)
2474{
2475 return 0xffffff << 0;
2476}
2477static inline u32 gr_gpccs_rc_lane_size_v_v(u32 r)
2478{
2479 return (r >> 0) & 0xffffff;
2480}
2481static inline u32 gr_gpccs_rc_lane_size_v_0_v(void)
2482{
2483 return 0x00000000;
2484}
2485static inline u32 gr_gpccs_rc_lane_size_v_0_f(void)
2486{
2487 return 0x0;
2488}
2489static inline u32 gr_gpc0_zcull_fs_r(void)
2490{
2491 return 0x00500910;
2492}
2493static inline u32 gr_gpc0_zcull_fs_num_sms_f(u32 v)
2494{
2495 return (v & 0x1ff) << 0;
2496}
2497static inline u32 gr_gpc0_zcull_fs_num_active_banks_f(u32 v)
2498{
2499 return (v & 0xf) << 16;
2500}
2501static inline u32 gr_gpc0_zcull_ram_addr_r(void)
2502{
2503 return 0x00500914;
2504}
2505static inline u32 gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(u32 v)
2506{
2507 return (v & 0xf) << 0;
2508}
2509static inline u32 gr_gpc0_zcull_ram_addr_row_offset_f(u32 v)
2510{
2511 return (v & 0xf) << 8;
2512}
2513static inline u32 gr_gpc0_zcull_sm_num_rcp_r(void)
2514{
2515 return 0x00500918;
2516}
2517static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative_f(u32 v)
2518{
2519 return (v & 0xffffff) << 0;
2520}
2521static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative__max_v(void)
2522{
2523 return 0x00800000;
2524}
2525static inline u32 gr_gpc0_zcull_total_ram_size_r(void)
2526{
2527 return 0x00500920;
2528}
2529static inline u32 gr_gpc0_zcull_total_ram_size_num_aliquots_f(u32 v)
2530{
2531 return (v & 0xffff) << 0;
2532}
2533static inline u32 gr_gpc0_zcull_zcsize_r(u32 i)
2534{
2535 return 0x00500a04 + i*32;
2536}
2537static inline u32 gr_gpc0_zcull_zcsize_height_subregion__multiple_v(void)
2538{
2539 return 0x00000040;
2540}
2541static inline u32 gr_gpc0_zcull_zcsize_width_subregion__multiple_v(void)
2542{
2543 return 0x00000010;
2544}
2545static inline u32 gr_gpc0_gpm_pd_sm_id_r(u32 i)
2546{
2547 return 0x00500c10 + i*4;
2548}
2549static inline u32 gr_gpc0_gpm_pd_sm_id_id_f(u32 v)
2550{
2551 return (v & 0xff) << 0;
2552}
2553static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_r(u32 i)
2554{
2555 return 0x00500c30 + i*4;
2556}
2557static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(u32 r)
2558{
2559 return (r >> 0) & 0xff;
2560}
2561static inline u32 gr_gpc0_tpc0_pe_cfg_smid_r(void)
2562{
2563 return 0x00504088;
2564}
2565static inline u32 gr_gpc0_tpc0_pe_cfg_smid_value_f(u32 v)
2566{
2567 return (v & 0xffff) << 0;
2568}
2569static inline u32 gr_gpc0_tpc0_sm_cfg_r(void)
2570{
2571 return 0x00504608;
2572}
2573static inline u32 gr_gpc0_tpc0_sm_cfg_tpc_id_f(u32 v)
2574{
2575 return (v & 0xffff) << 0;
2576}
2577static inline u32 gr_gpc0_tpc0_sm_cfg_tpc_id_v(u32 r)
2578{
2579 return (r >> 0) & 0xffff;
2580}
2581static inline u32 gr_gpc0_tpc0_sm_arch_r(void)
2582{
2583 return 0x00504330;
2584}
2585static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r)
2586{
2587 return (r >> 0) & 0xff;
2588}
2589static inline u32 gr_gpc0_tpc0_sm_arch_spa_version_v(u32 r)
2590{
2591 return (r >> 8) & 0xfff;
2592}
2593static inline u32 gr_gpc0_tpc0_sm_arch_sm_version_v(u32 r)
2594{
2595 return (r >> 20) & 0xfff;
2596}
2597static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void)
2598{
2599 return 0x00503018;
2600}
2601static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_m(void)
2602{
2603 return 0x1 << 0;
2604}
2605static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f(void)
2606{
2607 return 0x1;
2608}
2609static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_r(void)
2610{
2611 return 0x005030c0;
2612}
2613static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_f(u32 v)
2614{
2615 return (v & 0x3fffff) << 0;
2616}
2617static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void)
2618{
2619 return 0x3fffff << 0;
2620}
2621static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void)
2622{
2623 return 0x00000480;
2624}
2625static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v(void)
2626{
2627 return 0x00000d10;
2628}
2629static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void)
2630{
2631 return 0x00000020;
2632}
2633static inline u32 gr_gpc0_ppc0_cbm_beta_cb_offset_r(void)
2634{
2635 return 0x005030f4;
2636}
2637static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_r(void)
2638{
2639 return 0x005030e4;
2640}
2641static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(u32 v)
2642{
2643 return (v & 0xffff) << 0;
2644}
2645static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(void)
2646{
2647 return 0xffff << 0;
2648}
2649static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(void)
2650{
2651 return 0x00000800;
2652}
2653static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v(void)
2654{
2655 return 0x00000020;
2656}
2657static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_offset_r(void)
2658{
2659 return 0x005030f8;
2660}
2661static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r(void)
2662{
2663 return 0x005030f0;
2664}
2665static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(u32 v)
2666{
2667 return (v & 0x3fffff) << 0;
2668}
2669static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(void)
2670{
2671 return 0x00000480;
2672}
2673static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_r(void)
2674{
2675 return 0x00419e00;
2676}
2677static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(u32 v)
2678{
2679 return (v & 0xffffffff) << 0;
2680}
2681static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_r(void)
2682{
2683 return 0x00419e04;
2684}
2685static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_s(void)
2686{
2687 return 21;
2688}
2689static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(u32 v)
2690{
2691 return (v & 0x1fffff) << 0;
2692}
2693static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_m(void)
2694{
2695 return 0x1fffff << 0;
2696}
2697static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_v(u32 r)
2698{
2699 return (r >> 0) & 0x1fffff;
2700}
2701static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f(void)
2702{
2703 return 0x80;
2704}
2705static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_s(void)
2706{
2707 return 1;
2708}
2709static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_f(u32 v)
2710{
2711 return (v & 0x1) << 31;
2712}
2713static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_m(void)
2714{
2715 return 0x1 << 31;
2716}
2717static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_v(u32 r)
2718{
2719 return (r >> 31) & 0x1;
2720}
2721static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f(void)
2722{
2723 return 0x80000000;
2724}
2725static inline u32 gr_gpccs_falcon_addr_r(void)
2726{
2727 return 0x0041a0ac;
2728}
2729static inline u32 gr_gpccs_falcon_addr_lsb_s(void)
2730{
2731 return 6;
2732}
2733static inline u32 gr_gpccs_falcon_addr_lsb_f(u32 v)
2734{
2735 return (v & 0x3f) << 0;
2736}
2737static inline u32 gr_gpccs_falcon_addr_lsb_m(void)
2738{
2739 return 0x3f << 0;
2740}
2741static inline u32 gr_gpccs_falcon_addr_lsb_v(u32 r)
2742{
2743 return (r >> 0) & 0x3f;
2744}
2745static inline u32 gr_gpccs_falcon_addr_lsb_init_v(void)
2746{
2747 return 0x00000000;
2748}
2749static inline u32 gr_gpccs_falcon_addr_lsb_init_f(void)
2750{
2751 return 0x0;
2752}
2753static inline u32 gr_gpccs_falcon_addr_msb_s(void)
2754{
2755 return 6;
2756}
2757static inline u32 gr_gpccs_falcon_addr_msb_f(u32 v)
2758{
2759 return (v & 0x3f) << 6;
2760}
2761static inline u32 gr_gpccs_falcon_addr_msb_m(void)
2762{
2763 return 0x3f << 6;
2764}
2765static inline u32 gr_gpccs_falcon_addr_msb_v(u32 r)
2766{
2767 return (r >> 6) & 0x3f;
2768}
2769static inline u32 gr_gpccs_falcon_addr_msb_init_v(void)
2770{
2771 return 0x00000000;
2772}
2773static inline u32 gr_gpccs_falcon_addr_msb_init_f(void)
2774{
2775 return 0x0;
2776}
2777static inline u32 gr_gpccs_falcon_addr_ext_s(void)
2778{
2779 return 12;
2780}
2781static inline u32 gr_gpccs_falcon_addr_ext_f(u32 v)
2782{
2783 return (v & 0xfff) << 0;
2784}
2785static inline u32 gr_gpccs_falcon_addr_ext_m(void)
2786{
2787 return 0xfff << 0;
2788}
2789static inline u32 gr_gpccs_falcon_addr_ext_v(u32 r)
2790{
2791 return (r >> 0) & 0xfff;
2792}
2793static inline u32 gr_gpccs_cpuctl_r(void)
2794{
2795 return 0x0041a100;
2796}
2797static inline u32 gr_gpccs_cpuctl_startcpu_f(u32 v)
2798{
2799 return (v & 0x1) << 1;
2800}
2801static inline u32 gr_gpccs_dmactl_r(void)
2802{
2803 return 0x0041a10c;
2804}
2805static inline u32 gr_gpccs_dmactl_require_ctx_f(u32 v)
2806{
2807 return (v & 0x1) << 0;
2808}
2809static inline u32 gr_gpccs_dmactl_dmem_scrubbing_m(void)
2810{
2811 return 0x1 << 1;
2812}
2813static inline u32 gr_gpccs_dmactl_imem_scrubbing_m(void)
2814{
2815 return 0x1 << 2;
2816}
2817static inline u32 gr_gpccs_imemc_r(u32 i)
2818{
2819 return 0x0041a180 + i*16;
2820}
2821static inline u32 gr_gpccs_imemc_offs_f(u32 v)
2822{
2823 return (v & 0x3f) << 2;
2824}
2825static inline u32 gr_gpccs_imemc_blk_f(u32 v)
2826{
2827 return (v & 0xff) << 8;
2828}
2829static inline u32 gr_gpccs_imemc_aincw_f(u32 v)
2830{
2831 return (v & 0x1) << 24;
2832}
2833static inline u32 gr_gpccs_imemd_r(u32 i)
2834{
2835 return 0x0041a184 + i*16;
2836}
2837static inline u32 gr_gpccs_imemt_r(u32 i)
2838{
2839 return 0x0041a188 + i*16;
2840}
2841static inline u32 gr_gpccs_imemt__size_1_v(void)
2842{
2843 return 0x00000004;
2844}
2845static inline u32 gr_gpccs_imemt_tag_f(u32 v)
2846{
2847 return (v & 0xffff) << 0;
2848}
2849static inline u32 gr_gpccs_dmemc_r(u32 i)
2850{
2851 return 0x0041a1c0 + i*8;
2852}
2853static inline u32 gr_gpccs_dmemc_offs_f(u32 v)
2854{
2855 return (v & 0x3f) << 2;
2856}
2857static inline u32 gr_gpccs_dmemc_blk_f(u32 v)
2858{
2859 return (v & 0xff) << 8;
2860}
2861static inline u32 gr_gpccs_dmemc_aincw_f(u32 v)
2862{
2863 return (v & 0x1) << 24;
2864}
2865static inline u32 gr_gpccs_dmemd_r(u32 i)
2866{
2867 return 0x0041a1c4 + i*8;
2868}
2869static inline u32 gr_gpccs_ctxsw_mailbox_r(u32 i)
2870{
2871 return 0x0041a800 + i*4;
2872}
2873static inline u32 gr_gpccs_ctxsw_mailbox_value_f(u32 v)
2874{
2875 return (v & 0xffffffff) << 0;
2876}
2877static inline u32 gr_gpcs_swdx_bundle_cb_base_r(void)
2878{
2879 return 0x00418e24;
2880}
2881static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_s(void)
2882{
2883 return 32;
2884}
2885static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(u32 v)
2886{
2887 return (v & 0xffffffff) << 0;
2888}
2889static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_m(void)
2890{
2891 return 0xffffffff << 0;
2892}
2893static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(u32 r)
2894{
2895 return (r >> 0) & 0xffffffff;
2896}
2897static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v(void)
2898{
2899 return 0x00000000;
2900}
2901static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f(void)
2902{
2903 return 0x0;
2904}
2905static inline u32 gr_gpcs_swdx_bundle_cb_size_r(void)
2906{
2907 return 0x00418e28;
2908}
2909static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_s(void)
2910{
2911 return 11;
2912}
2913static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_f(u32 v)
2914{
2915 return (v & 0x7ff) << 0;
2916}
2917static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_m(void)
2918{
2919 return 0x7ff << 0;
2920}
2921static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_v(u32 r)
2922{
2923 return (r >> 0) & 0x7ff;
2924}
2925static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_v(void)
2926{
2927 return 0x00000030;
2928}
2929static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_f(void)
2930{
2931 return 0x30;
2932}
2933static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_s(void)
2934{
2935 return 1;
2936}
2937static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_f(u32 v)
2938{
2939 return (v & 0x1) << 31;
2940}
2941static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_m(void)
2942{
2943 return 0x1 << 31;
2944}
2945static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_v(u32 r)
2946{
2947 return (r >> 31) & 0x1;
2948}
2949static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_v(void)
2950{
2951 return 0x00000000;
2952}
2953static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_f(void)
2954{
2955 return 0x0;
2956}
2957static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_v(void)
2958{
2959 return 0x00000001;
2960}
2961static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_f(void)
2962{
2963 return 0x80000000;
2964}
2965static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_r(void)
2966{
2967 return 0x005001dc;
2968}
2969static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_f(u32 v)
2970{
2971 return (v & 0xffff) << 0;
2972}
2973static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v(void)
2974{
2975 return 0x000004b0;
2976}
2977static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(void)
2978{
2979 return 0x00000100;
2980}
2981static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_r(void)
2982{
2983 return 0x005001d8;
2984}
2985static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(u32 v)
2986{
2987 return (v & 0xffffffff) << 0;
2988}
2989static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v(void)
2990{
2991 return 0x00000008;
2992}
2993static inline u32 gr_gpcs_swdx_beta_cb_ctrl_r(void)
2994{
2995 return 0x004181e4;
2996}
2997static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(u32 v)
2998{
2999 return (v & 0xfff) << 0;
3000}
3001static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v(void)
3002{
3003 return 0x00000100;
3004}
3005static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_r(void)
3006{
3007 return 0x0041befc;
3008}
3009static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f(u32 v)
3010{
3011 return (v & 0xfff) << 0;
3012}
3013static inline u32 gr_gpcs_swdx_tc_beta_cb_size_r(u32 i)
3014{
3015 return 0x00418ea0 + i*4;
3016}
3017static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_f(u32 v)
3018{
3019 return (v & 0x3fffff) << 0;
3020}
3021static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void)
3022{
3023 return 0x3fffff << 0;
3024}
3025static inline u32 gr_gpcs_swdx_dss_zbc_color_r_r(u32 i)
3026{
3027 return 0x00418010 + i*4;
3028}
3029static inline u32 gr_gpcs_swdx_dss_zbc_color_r_val_f(u32 v)
3030{
3031 return (v & 0xffffffff) << 0;
3032}
3033static inline u32 gr_gpcs_swdx_dss_zbc_color_g_r(u32 i)
3034{
3035 return 0x0041804c + i*4;
3036}
3037static inline u32 gr_gpcs_swdx_dss_zbc_color_g_val_f(u32 v)
3038{
3039 return (v & 0xffffffff) << 0;
3040}
3041static inline u32 gr_gpcs_swdx_dss_zbc_color_b_r(u32 i)
3042{
3043 return 0x00418088 + i*4;
3044}
3045static inline u32 gr_gpcs_swdx_dss_zbc_color_b_val_f(u32 v)
3046{
3047 return (v & 0xffffffff) << 0;
3048}
3049static inline u32 gr_gpcs_swdx_dss_zbc_color_a_r(u32 i)
3050{
3051 return 0x004180c4 + i*4;
3052}
3053static inline u32 gr_gpcs_swdx_dss_zbc_color_a_val_f(u32 v)
3054{
3055 return (v & 0xffffffff) << 0;
3056}
3057static inline u32 gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r(void)
3058{
3059 return 0x00418100;
3060}
3061static inline u32 gr_gpcs_swdx_dss_zbc_z_r(u32 i)
3062{
3063 return 0x00418110 + i*4;
3064}
3065static inline u32 gr_gpcs_swdx_dss_zbc_z_val_f(u32 v)
3066{
3067 return (v & 0xffffffff) << 0;
3068}
3069static inline u32 gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r(void)
3070{
3071 return 0x0041814c;
3072}
3073static inline u32 gr_gpcs_swdx_dss_zbc_s_r(u32 i)
3074{
3075 return 0x0041815c + i*4;
3076}
3077static inline u32 gr_gpcs_swdx_dss_zbc_s_val_f(u32 v)
3078{
3079 return (v & 0xff) << 0;
3080}
3081static inline u32 gr_gpcs_swdx_dss_zbc_s_01_to_04_format_r(void)
3082{
3083 return 0x00418198;
3084}
3085static inline u32 gr_gpcs_setup_attrib_cb_base_r(void)
3086{
3087 return 0x00418810;
3088}
3089static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_f(u32 v)
3090{
3091 return (v & 0xfffffff) << 0;
3092}
3093static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v(void)
3094{
3095 return 0x0000000c;
3096}
3097static inline u32 gr_gpcs_setup_attrib_cb_base_valid_true_f(void)
3098{
3099 return 0x80000000;
3100}
3101static inline u32 gr_crstr_gpc_map_r(u32 i)
3102{
3103 return 0x00418b08 + i*4;
3104}
3105static inline u32 gr_crstr_gpc_map_tile0_f(u32 v)
3106{
3107 return (v & 0x1f) << 0;
3108}
3109static inline u32 gr_crstr_gpc_map_tile1_f(u32 v)
3110{
3111 return (v & 0x1f) << 5;
3112}
3113static inline u32 gr_crstr_gpc_map_tile2_f(u32 v)
3114{
3115 return (v & 0x1f) << 10;
3116}
3117static inline u32 gr_crstr_gpc_map_tile3_f(u32 v)
3118{
3119 return (v & 0x1f) << 15;
3120}
3121static inline u32 gr_crstr_gpc_map_tile4_f(u32 v)
3122{
3123 return (v & 0x1f) << 20;
3124}
3125static inline u32 gr_crstr_gpc_map_tile5_f(u32 v)
3126{
3127 return (v & 0x1f) << 25;
3128}
3129static inline u32 gr_crstr_map_table_cfg_r(void)
3130{
3131 return 0x00418bb8;
3132}
3133static inline u32 gr_crstr_map_table_cfg_row_offset_f(u32 v)
3134{
3135 return (v & 0xff) << 0;
3136}
3137static inline u32 gr_crstr_map_table_cfg_num_entries_f(u32 v)
3138{
3139 return (v & 0xff) << 8;
3140}
3141static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_r(u32 i)
3142{
3143 return 0x00418980 + i*4;
3144}
3145static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_0_f(u32 v)
3146{
3147 return (v & 0x7) << 0;
3148}
3149static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_1_f(u32 v)
3150{
3151 return (v & 0x7) << 4;
3152}
3153static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_2_f(u32 v)
3154{
3155 return (v & 0x7) << 8;
3156}
3157static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_3_f(u32 v)
3158{
3159 return (v & 0x7) << 12;
3160}
3161static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_4_f(u32 v)
3162{
3163 return (v & 0x7) << 16;
3164}
3165static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_5_f(u32 v)
3166{
3167 return (v & 0x7) << 20;
3168}
3169static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_6_f(u32 v)
3170{
3171 return (v & 0x7) << 24;
3172}
3173static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_7_f(u32 v)
3174{
3175 return (v & 0x7) << 28;
3176}
3177static inline u32 gr_gpcs_gpm_pd_cfg_r(void)
3178{
3179 return 0x00418c6c;
3180}
3181static inline u32 gr_gpcs_gcc_pagepool_base_r(void)
3182{
3183 return 0x00419004;
3184}
3185static inline u32 gr_gpcs_gcc_pagepool_base_addr_39_8_f(u32 v)
3186{
3187 return (v & 0xffffffff) << 0;
3188}
3189static inline u32 gr_gpcs_gcc_pagepool_r(void)
3190{
3191 return 0x00419008;
3192}
3193static inline u32 gr_gpcs_gcc_pagepool_total_pages_f(u32 v)
3194{
3195 return (v & 0x3ff) << 0;
3196}
3197static inline u32 gr_gpcs_tpcs_pe_vaf_r(void)
3198{
3199 return 0x0041980c;
3200}
3201static inline u32 gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f(void)
3202{
3203 return 0x10;
3204}
3205static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r(void)
3206{
3207 return 0x00419848;
3208}
3209static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(u32 v)
3210{
3211 return (v & 0xfffffff) << 0;
3212}
3213static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(u32 v)
3214{
3215 return (v & 0x1) << 28;
3216}
3217static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f(void)
3218{
3219 return 0x10000000;
3220}
3221static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_r(void)
3222{
3223 return 0x00419c00;
3224}
3225static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f(void)
3226{
3227 return 0x0;
3228}
3229static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f(void)
3230{
3231 return 0x8;
3232}
3233static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r(void)
3234{
3235 return 0x00419c2c;
3236}
3237static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(u32 v)
3238{
3239 return (v & 0xfffffff) << 0;
3240}
3241static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(u32 v)
3242{
3243 return (v & 0x1) << 28;
3244}
3245static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void)
3246{
3247 return 0x10000000;
3248}
3249static inline u32 gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r(void)
3250{
3251 return 0x00419ea8;
3252}
3253static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_r(void)
3254{
3255 return 0x00504728;
3256}
3257static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_stack_error_report_f(void)
3258{
3259 return 0x2;
3260}
3261static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_api_stack_error_report_f(void)
3262{
3263 return 0x4;
3264}
3265static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_pc_wrap_report_f(void)
3266{
3267 return 0x10;
3268}
3269static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_pc_report_f(void)
3270{
3271 return 0x20;
3272}
3273static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_pc_overflow_report_f(void)
3274{
3275 return 0x40;
3276}
3277static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_reg_report_f(void)
3278{
3279 return 0x100;
3280}
3281static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void)
3282{
3283 return 0x200;
3284}
3285static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_param_report_f(void)
3286{
3287 return 0x800;
3288}
3289static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_reg_report_f(void)
3290{
3291 return 0x2000;
3292}
3293static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_addr_report_f(void)
3294{
3295 return 0x4000;
3296}
3297static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_addr_report_f(void)
3298{
3299 return 0x8000;
3300}
3301static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_addr_space_report_f(void)
3302{
3303 return 0x10000;
3304}
3305static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void)
3306{
3307 return 0x40000;
3308}
3309static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_mmu_fault_report_f(void)
3310{
3311 return 0x800000;
3312}
3313static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_stack_overflow_report_f(void)
3314{
3315 return 0x400000;
3316}
3317static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void)
3318{
3319 return 0x00419d0c;
3320}
3321static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f(void)
3322{
3323 return 0x2;
3324}
3325static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f(void)
3326{
3327 return 0x1;
3328}
3329static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_mpc_enabled_f(void)
3330{
3331 return 0x10;
3332}
3333static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void)
3334{
3335 return 0x0050450c;
3336}
3337static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(u32 r)
3338{
3339 return (r >> 1) & 0x1;
3340}
3341static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void)
3342{
3343 return 0x2;
3344}
3345static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_mpc_enabled_f(void)
3346{
3347 return 0x10;
3348}
3349static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void)
3350{
3351 return 0x0041ac94;
3352}
3353static inline u32 gr_gpcs_gpccs_gpc_exception_en_gcc_f(u32 v)
3354{
3355 return (v & 0x1) << 2;
3356}
3357static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v)
3358{
3359 return (v & 0xff) << 16;
3360}
3361static inline u32 gr_gpc0_gpccs_gpc_exception_r(void)
3362{
3363 return 0x00502c90;
3364}
3365static inline u32 gr_gpc0_gpccs_gpc_exception_gcc_v(u32 r)
3366{
3367 return (r >> 2) & 0x1;
3368}
3369static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r)
3370{
3371 return (r >> 16) & 0xff;
3372}
3373static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v(void)
3374{
3375 return 0x00000001;
3376}
3377static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void)
3378{
3379 return 0x00504508;
3380}
3381static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_v(u32 r)
3382{
3383 return (r >> 0) & 0x1;
3384}
3385static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_pending_v(void)
3386{
3387 return 0x00000001;
3388}
3389static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r)
3390{
3391 return (r >> 1) & 0x1;
3392}
3393static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void)
3394{
3395 return 0x00000001;
3396}
3397static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_mpc_m(void)
3398{
3399 return 0x1 << 4;
3400}
3401static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_mpc_pending_f(void)
3402{
3403 return 0x10;
3404}
3405static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_r(void)
3406{
3407 return 0x00504704;
3408}
3409static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_m(void)
3410{
3411 return 0x1 << 0;
3412}
3413static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_v(u32 r)
3414{
3415 return (r >> 0) & 0x1;
3416}
3417static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_v(void)
3418{
3419 return 0x00000001;
3420}
3421static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_f(void)
3422{
3423 return 0x1;
3424}
3425static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_v(void)
3426{
3427 return 0x00000000;
3428}
3429static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_f(void)
3430{
3431 return 0x0;
3432}
3433static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_m(void)
3434{
3435 return 0x1 << 31;
3436}
3437static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_enable_f(void)
3438{
3439 return 0x80000000;
3440}
3441static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_disable_f(void)
3442{
3443 return 0x0;
3444}
3445static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_m(void)
3446{
3447 return 0x1 << 3;
3448}
3449static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_enable_f(void)
3450{
3451 return 0x8;
3452}
3453static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_disable_f(void)
3454{
3455 return 0x0;
3456}
3457static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_run_trigger_task_f(void)
3458{
3459 return 0x40000000;
3460}
3461static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_0_r(void)
3462{
3463 return 0x00504708;
3464}
3465static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_1_r(void)
3466{
3467 return 0x0050470c;
3468}
3469static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_0_r(void)
3470{
3471 return 0x00504710;
3472}
3473static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_1_r(void)
3474{
3475 return 0x00504714;
3476}
3477static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_0_r(void)
3478{
3479 return 0x00504718;
3480}
3481static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_1_r(void)
3482{
3483 return 0x0050471c;
3484}
3485static inline u32 gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_0_r(void)
3486{
3487 return 0x00419e90;
3488}
3489static inline u32 gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_1_r(void)
3490{
3491 return 0x00419e94;
3492}
3493static inline u32 gr_gpcs_tpcs_sms_dbgr_status0_r(void)
3494{
3495 return 0x00419e80;
3496}
3497static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_r(void)
3498{
3499 return 0x00504700;
3500}
3501static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_sm_in_trap_mode_v(u32 r)
3502{
3503 return (r >> 0) & 0x1;
3504}
3505static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_v(u32 r)
3506{
3507 return (r >> 4) & 0x1;
3508}
3509static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_true_v(void)
3510{
3511 return 0x00000001;
3512}
3513static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_r(void)
3514{
3515 return 0x00504730;
3516}
3517static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_v(u32 r)
3518{
3519 return (r >> 0) & 0xffff;
3520}
3521static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_v(void)
3522{
3523 return 0x00000000;
3524}
3525static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_f(void)
3526{
3527 return 0x0;
3528}
3529static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_wrap_id_m(void)
3530{
3531 return 0xff << 16;
3532}
3533static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_m(void)
3534{
3535 return 0xf << 24;
3536}
3537static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_none_f(void)
3538{
3539 return 0x0;
3540}
3541static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_r(void)
3542{
3543 return 0x0050460c;
3544}
3545static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm0_error_v(u32 r)
3546{
3547 return (r >> 0) & 0x1;
3548}
3549static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm1_error_v(u32 r)
3550{
3551 return (r >> 1) & 0x1;
3552}
3553static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_pc_r(void)
3554{
3555 return 0x00504738;
3556}
3557static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void)
3558{
3559 return 0x005043a0;
3560}
3561static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void)
3562{
3563 return 0x00419ba0;
3564}
3565static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void)
3566{
3567 return 0x1 << 4;
3568}
3569static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v)
3570{
3571 return (v & 0x1) << 4;
3572}
3573static inline u32 gr_gpc0_tpc0_sm_debug_sfe_control_r(void)
3574{
3575 return 0x005043b0;
3576}
3577static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void)
3578{
3579 return 0x00419bb0;
3580}
3581static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void)
3582{
3583 return 0x1 << 0;
3584}
3585static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v)
3586{
3587 return (v & 0x1) << 0;
3588}
3589static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void)
3590{
3591 return 0x0041be08;
3592}
3593static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f(void)
3594{
3595 return 0x4;
3596}
3597static inline u32 gr_ppcs_wwdx_map_gpc_map_r(u32 i)
3598{
3599 return 0x0041bf00 + i*4;
3600}
3601static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void)
3602{
3603 return 0x0041bfd0;
3604}
3605static inline u32 gr_ppcs_wwdx_map_table_cfg_row_offset_f(u32 v)
3606{
3607 return (v & 0xff) << 0;
3608}
3609static inline u32 gr_ppcs_wwdx_map_table_cfg_num_entries_f(u32 v)
3610{
3611 return (v & 0xff) << 8;
3612}
3613static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(u32 v)
3614{
3615 return (v & 0x1f) << 16;
3616}
3617static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(u32 v)
3618{
3619 return (v & 0x7) << 21;
3620}
3621static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_r(void)
3622{
3623 return 0x0041bfd4;
3624}
3625static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(u32 v)
3626{
3627 return (v & 0xffffff) << 0;
3628}
3629static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_r(u32 i)
3630{
3631 return 0x0041bfb0 + i*4;
3632}
3633static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff__size_1_v(void)
3634{
3635 return 0x00000005;
3636}
3637static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_0_mod_value_f(u32 v)
3638{
3639 return (v & 0xff) << 0;
3640}
3641static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_1_mod_value_f(u32 v)
3642{
3643 return (v & 0xff) << 8;
3644}
3645static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_2_mod_value_f(u32 v)
3646{
3647 return (v & 0xff) << 16;
3648}
3649static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_3_mod_value_f(u32 v)
3650{
3651 return (v & 0xff) << 24;
3652}
3653static inline u32 gr_bes_zrop_settings_r(void)
3654{
3655 return 0x00408850;
3656}
3657static inline u32 gr_bes_zrop_settings_num_active_ltcs_f(u32 v)
3658{
3659 return (v & 0xf) << 0;
3660}
3661static inline u32 gr_be0_crop_debug3_r(void)
3662{
3663 return 0x00410108;
3664}
3665static inline u32 gr_bes_crop_debug3_r(void)
3666{
3667 return 0x00408908;
3668}
3669static inline u32 gr_bes_crop_debug3_comp_vdc_4to2_disable_m(void)
3670{
3671 return 0x1 << 31;
3672}
3673static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_m(void)
3674{
3675 return 0x1 << 1;
3676}
3677static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_disabled_f(void)
3678{
3679 return 0x0;
3680}
3681static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_enabled_f(void)
3682{
3683 return 0x2;
3684}
3685static inline u32 gr_bes_crop_debug3_blendopt_fill_override_m(void)
3686{
3687 return 0x1 << 2;
3688}
3689static inline u32 gr_bes_crop_debug3_blendopt_fill_override_disabled_f(void)
3690{
3691 return 0x0;
3692}
3693static inline u32 gr_bes_crop_debug3_blendopt_fill_override_enabled_f(void)
3694{
3695 return 0x4;
3696}
3697static inline u32 gr_bes_crop_settings_r(void)
3698{
3699 return 0x00408958;
3700}
3701static inline u32 gr_bes_crop_settings_num_active_ltcs_f(u32 v)
3702{
3703 return (v & 0xf) << 0;
3704}
3705static inline u32 gr_zcull_bytes_per_aliquot_per_gpu_v(void)
3706{
3707 return 0x00000020;
3708}
3709static inline u32 gr_zcull_save_restore_header_bytes_per_gpc_v(void)
3710{
3711 return 0x00000020;
3712}
3713static inline u32 gr_zcull_save_restore_subregion_header_bytes_per_gpc_v(void)
3714{
3715 return 0x000000c0;
3716}
3717static inline u32 gr_zcull_subregion_qty_v(void)
3718{
3719 return 0x00000010;
3720}
3721static inline u32 gr_gpcs_tpcs_tex_in_dbg_r(void)
3722{
3723 return 0x00419a00;
3724}
3725static inline u32 gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_f(u32 v)
3726{
3727 return (v & 0x1) << 19;
3728}
3729static inline u32 gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_m(void)
3730{
3731 return 0x1 << 19;
3732}
3733static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_r(void)
3734{
3735 return 0x00419bf0;
3736}
3737static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_f(u32 v)
3738{
3739 return (v & 0x1) << 5;
3740}
3741static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_m(void)
3742{
3743 return 0x1 << 5;
3744}
3745static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_f(u32 v)
3746{
3747 return (v & 0x1) << 10;
3748}
3749static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_m(void)
3750{
3751 return 0x1 << 10;
3752}
3753static inline u32 gr_fe_pwr_mode_r(void)
3754{
3755 return 0x00404170;
3756}
3757static inline u32 gr_fe_pwr_mode_mode_auto_f(void)
3758{
3759 return 0x0;
3760}
3761static inline u32 gr_fe_pwr_mode_mode_force_on_f(void)
3762{
3763 return 0x2;
3764}
3765static inline u32 gr_fe_pwr_mode_req_v(u32 r)
3766{
3767 return (r >> 4) & 0x1;
3768}
3769static inline u32 gr_fe_pwr_mode_req_send_f(void)
3770{
3771 return 0x10;
3772}
3773static inline u32 gr_fe_pwr_mode_req_done_v(void)
3774{
3775 return 0x00000000;
3776}
3777static inline u32 gr_gpcs_pri_mmu_ctrl_r(void)
3778{
3779 return 0x00418880;
3780}
3781static inline u32 gr_gpcs_pri_mmu_ctrl_vm_pg_size_m(void)
3782{
3783 return 0x1 << 0;
3784}
3785static inline u32 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m(void)
3786{
3787 return 0x1 << 11;
3788}
3789static inline u32 gr_gpcs_pri_mmu_ctrl_vol_fault_m(void)
3790{
3791 return 0x1 << 1;
3792}
3793static inline u32 gr_gpcs_pri_mmu_ctrl_comp_fault_m(void)
3794{
3795 return 0x1 << 2;
3796}
3797static inline u32 gr_gpcs_pri_mmu_ctrl_miss_gran_m(void)
3798{
3799 return 0x3 << 3;
3800}
3801static inline u32 gr_gpcs_pri_mmu_ctrl_cache_mode_m(void)
3802{
3803 return 0x3 << 5;
3804}
3805static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_aperture_m(void)
3806{
3807 return 0x3 << 28;
3808}
3809static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_vol_m(void)
3810{
3811 return 0x1 << 30;
3812}
3813static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void)
3814{
3815 return 0x1 << 31;
3816}
3817static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void)
3818{
3819 return 0x00418890;
3820}
3821static inline u32 gr_gpcs_pri_mmu_pm_req_mask_r(void)
3822{
3823 return 0x00418894;
3824}
3825static inline u32 gr_gpcs_pri_mmu_debug_ctrl_r(void)
3826{
3827 return 0x004188b0;
3828}
3829static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_v(u32 r)
3830{
3831 return (r >> 16) & 0x1;
3832}
3833static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(void)
3834{
3835 return 0x00000001;
3836}
3837static inline u32 gr_gpcs_pri_mmu_debug_wr_r(void)
3838{
3839 return 0x004188b4;
3840}
3841static inline u32 gr_gpcs_pri_mmu_debug_rd_r(void)
3842{
3843 return 0x004188b8;
3844}
3845static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void)
3846{
3847 return 0x004188ac;
3848}
3849static inline u32 gr_gpcs_tpcs_sms_dbgr_control0_r(void)
3850{
3851 return 0x00419e84;
3852}
3853static inline u32 gr_fe_gfxp_wfi_timeout_r(void)
3854{
3855 return 0x004041c0;
3856}
3857static inline u32 gr_fe_gfxp_wfi_timeout_count_f(u32 v)
3858{
3859 return (v & 0xffffffff) << 0;
3860}
3861static inline u32 gr_fe_gfxp_wfi_timeout_count_disabled_f(void)
3862{
3863 return 0x0;
3864}
3865static inline u32 gr_gpcs_tpcs_sm_texio_control_r(void)
3866{
3867 return 0x00419bd8;
3868}
3869static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(u32 v)
3870{
3871 return (v & 0x7) << 8;
3872}
3873static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m(void)
3874{
3875 return 0x7 << 8;
3876}
3877static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f(void)
3878{
3879 return 0x100;
3880}
3881static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_r(void)
3882{
3883 return 0x00419ba4;
3884}
3885static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(void)
3886{
3887 return 0x3 << 11;
3888}
3889static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f(void)
3890{
3891 return 0x1000;
3892}
3893static inline u32 gr_gpcs_tc_debug0_r(void)
3894{
3895 return 0x00418708;
3896}
3897static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(u32 v)
3898{
3899 return (v & 0x1ff) << 0;
3900}
3901static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(void)
3902{
3903 return 0x1ff << 0;
3904}
3905#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ltc_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ltc_gv100.h
new file mode 100644
index 00000000..f1d977d4
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ltc_gv100.h
@@ -0,0 +1,613 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_ltc_gv100_h_
51#define _hw_ltc_gv100_h_
52
53static inline u32 ltc_pltcg_base_v(void)
54{
55 return 0x00140000;
56}
57static inline u32 ltc_pltcg_extent_v(void)
58{
59 return 0x0017ffff;
60}
61static inline u32 ltc_ltc0_ltss_v(void)
62{
63 return 0x00140200;
64}
65static inline u32 ltc_ltc0_lts0_v(void)
66{
67 return 0x00140400;
68}
69static inline u32 ltc_ltcs_ltss_v(void)
70{
71 return 0x0017e200;
72}
73static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void)
74{
75 return 0x0014046c;
76}
77static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void)
78{
79 return 0x00140518;
80}
81static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void)
82{
83 return 0x0017e318;
84}
85static inline u32 ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m(void)
86{
87 return 0x1 << 15;
88}
89static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void)
90{
91 return 0x00140494;
92}
93static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r)
94{
95 return (r >> 0) & 0xffff;
96}
97static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r)
98{
99 return (r >> 16) & 0x3;
100}
101static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void)
102{
103 return 0x00000000;
104}
105static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void)
106{
107 return 0x00000001;
108}
109static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void)
110{
111 return 0x00000002;
112}
113static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void)
114{
115 return 0x0017e26c;
116}
117static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void)
118{
119 return 0x1;
120}
121static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void)
122{
123 return 0x2;
124}
125static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r)
126{
127 return (r >> 2) & 0x1;
128}
129static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void)
130{
131 return 0x00000001;
132}
133static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void)
134{
135 return 0x4;
136}
137static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void)
138{
139 return 0x0014046c;
140}
141static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void)
142{
143 return 0x0017e270;
144}
145static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v)
146{
147 return (v & 0x3ffff) << 0;
148}
149static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void)
150{
151 return 0x0017e274;
152}
153static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v)
154{
155 return (v & 0x3ffff) << 0;
156}
157static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void)
158{
159 return 0x0003ffff;
160}
161static inline u32 ltc_ltcs_ltss_cbc_base_r(void)
162{
163 return 0x0017e278;
164}
165static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void)
166{
167 return 0x0000000b;
168}
169static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r)
170{
171 return (r >> 0) & 0x3ffffff;
172}
173static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_r(void)
174{
175 return 0x0017e27c;
176}
177static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs__v(u32 r)
178{
179 return (r >> 0) & 0x1f;
180}
181static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_f(u32 v)
182{
183 return (v & 0x1) << 24;
184}
185static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_v(u32 r)
186{
187 return (r >> 24) & 0x1;
188}
189static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_f(u32 v)
190{
191 return (v & 0x1) << 25;
192}
193static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_v(u32 r)
194{
195 return (r >> 25) & 0x1;
196}
197static inline u32 ltc_ltcs_misc_ltc_num_active_ltcs_r(void)
198{
199 return 0x0017e000;
200}
201static inline u32 ltc_ltcs_ltss_cbc_param_r(void)
202{
203 return 0x0017e280;
204}
205static inline u32 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(u32 r)
206{
207 return (r >> 0) & 0xffff;
208}
209static inline u32 ltc_ltcs_ltss_cbc_param_cache_line_size_v(u32 r)
210{
211 return (r >> 24) & 0xf;
212}
213static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(u32 r)
214{
215 return (r >> 28) & 0xf;
216}
217static inline u32 ltc_ltcs_ltss_cbc_param2_r(void)
218{
219 return 0x0017e3f4;
220}
221static inline u32 ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(u32 r)
222{
223 return (r >> 0) & 0xffff;
224}
225static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void)
226{
227 return 0x0017e2ac;
228}
229static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v)
230{
231 return (v & 0x1f) << 16;
232}
233static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void)
234{
235 return 0x0017e338;
236}
237static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v)
238{
239 return (v & 0xf) << 0;
240}
241static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i)
242{
243 return 0x0017e33c + i*4;
244}
245static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void)
246{
247 return 0x00000004;
248}
249static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void)
250{
251 return 0x0017e34c;
252}
253static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void)
254{
255 return 32;
256}
257static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v)
258{
259 return (v & 0xffffffff) << 0;
260}
261static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void)
262{
263 return 0xffffffff << 0;
264}
265static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r)
266{
267 return (r >> 0) & 0xffffffff;
268}
269static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_r(void)
270{
271 return 0x0017e204;
272}
273static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_s(void)
274{
275 return 8;
276}
277static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_f(u32 v)
278{
279 return (v & 0xff) << 0;
280}
281static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_m(void)
282{
283 return 0xff << 0;
284}
285static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_v(u32 r)
286{
287 return (r >> 0) & 0xff;
288}
289static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void)
290{
291 return 0x0017e2b0;
292}
293static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void)
294{
295 return 0x10000000;
296}
297static inline u32 ltc_ltcs_ltss_g_elpg_r(void)
298{
299 return 0x0017e214;
300}
301static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r)
302{
303 return (r >> 0) & 0x1;
304}
305static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void)
306{
307 return 0x00000001;
308}
309static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void)
310{
311 return 0x1;
312}
313static inline u32 ltc_ltc0_ltss_g_elpg_r(void)
314{
315 return 0x00140214;
316}
317static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r)
318{
319 return (r >> 0) & 0x1;
320}
321static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void)
322{
323 return 0x00000001;
324}
325static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void)
326{
327 return 0x1;
328}
329static inline u32 ltc_ltc1_ltss_g_elpg_r(void)
330{
331 return 0x00142214;
332}
333static inline u32 ltc_ltc1_ltss_g_elpg_flush_v(u32 r)
334{
335 return (r >> 0) & 0x1;
336}
337static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_v(void)
338{
339 return 0x00000001;
340}
341static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_f(void)
342{
343 return 0x1;
344}
345static inline u32 ltc_ltcs_ltss_intr_r(void)
346{
347 return 0x0017e20c;
348}
349static inline u32 ltc_ltcs_ltss_intr_ecc_sec_error_pending_f(void)
350{
351 return 0x100;
352}
353static inline u32 ltc_ltcs_ltss_intr_ecc_ded_error_pending_f(void)
354{
355 return 0x200;
356}
357static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void)
358{
359 return 0x1 << 20;
360}
361static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(void)
362{
363 return 0x1 << 30;
364}
365static inline u32 ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f(void)
366{
367 return 0x1000000;
368}
369static inline u32 ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f(void)
370{
371 return 0x2000000;
372}
373static inline u32 ltc_ltc0_lts0_intr_r(void)
374{
375 return 0x0014040c;
376}
377static inline u32 ltc_ltc0_lts0_dstg_ecc_report_r(void)
378{
379 return 0x0014051c;
380}
381static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_m(void)
382{
383 return 0xff << 0;
384}
385static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(u32 r)
386{
387 return (r >> 0) & 0xff;
388}
389static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_m(void)
390{
391 return 0xff << 16;
392}
393static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(u32 r)
394{
395 return (r >> 16) & 0xff;
396}
397static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void)
398{
399 return 0x0017e2a0;
400}
401static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r)
402{
403 return (r >> 0) & 0x1;
404}
405static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void)
406{
407 return 0x00000001;
408}
409static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void)
410{
411 return 0x1;
412}
413static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r)
414{
415 return (r >> 8) & 0xf;
416}
417static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void)
418{
419 return 0x00000003;
420}
421static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void)
422{
423 return 0x300;
424}
425static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r)
426{
427 return (r >> 28) & 0x1;
428}
429static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void)
430{
431 return 0x00000001;
432}
433static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void)
434{
435 return 0x10000000;
436}
437static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r)
438{
439 return (r >> 29) & 0x1;
440}
441static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void)
442{
443 return 0x00000001;
444}
445static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void)
446{
447 return 0x20000000;
448}
449static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r)
450{
451 return (r >> 30) & 0x1;
452}
453static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void)
454{
455 return 0x00000001;
456}
457static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void)
458{
459 return 0x40000000;
460}
461static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void)
462{
463 return 0x0017e2a4;
464}
465static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r)
466{
467 return (r >> 0) & 0x1;
468}
469static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void)
470{
471 return 0x00000001;
472}
473static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void)
474{
475 return 0x1;
476}
477static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r)
478{
479 return (r >> 8) & 0xf;
480}
481static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void)
482{
483 return 0x00000003;
484}
485static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void)
486{
487 return 0x300;
488}
489static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r)
490{
491 return (r >> 16) & 0x1;
492}
493static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void)
494{
495 return 0x00000001;
496}
497static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void)
498{
499 return 0x10000;
500}
501static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r)
502{
503 return (r >> 28) & 0x1;
504}
505static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void)
506{
507 return 0x00000001;
508}
509static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void)
510{
511 return 0x10000000;
512}
513static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r)
514{
515 return (r >> 29) & 0x1;
516}
517static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void)
518{
519 return 0x00000001;
520}
521static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void)
522{
523 return 0x20000000;
524}
525static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r)
526{
527 return (r >> 30) & 0x1;
528}
529static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void)
530{
531 return 0x00000001;
532}
533static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void)
534{
535 return 0x40000000;
536}
537static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void)
538{
539 return 0x001402a0;
540}
541static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r)
542{
543 return (r >> 0) & 0x1;
544}
545static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void)
546{
547 return 0x00000001;
548}
549static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void)
550{
551 return 0x1;
552}
553static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void)
554{
555 return 0x001402a4;
556}
557static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r)
558{
559 return (r >> 0) & 0x1;
560}
561static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void)
562{
563 return 0x00000001;
564}
565static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void)
566{
567 return 0x1;
568}
569static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_r(void)
570{
571 return 0x001422a0;
572}
573static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_v(u32 r)
574{
575 return (r >> 0) & 0x1;
576}
577static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_v(void)
578{
579 return 0x00000001;
580}
581static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_f(void)
582{
583 return 0x1;
584}
585static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_r(void)
586{
587 return 0x001422a4;
588}
589static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_v(u32 r)
590{
591 return (r >> 0) & 0x1;
592}
593static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_v(void)
594{
595 return 0x00000001;
596}
597static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_f(void)
598{
599 return 0x1;
600}
601static inline u32 ltc_ltc0_lts0_tstg_info_1_r(void)
602{
603 return 0x0014058c;
604}
605static inline u32 ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(u32 r)
606{
607 return (r >> 0) & 0xffff;
608}
609static inline u32 ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(u32 r)
610{
611 return (r >> 16) & 0x1f;
612}
613#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h
new file mode 100644
index 00000000..0cd59c3b
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h
@@ -0,0 +1,245 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_mc_gv100_h_
51#define _hw_mc_gv100_h_
52
53static inline u32 mc_boot_0_r(void)
54{
55 return 0x00000000;
56}
57static inline u32 mc_boot_0_architecture_v(u32 r)
58{
59 return (r >> 24) & 0x1f;
60}
61static inline u32 mc_boot_0_implementation_v(u32 r)
62{
63 return (r >> 20) & 0xf;
64}
65static inline u32 mc_boot_0_major_revision_v(u32 r)
66{
67 return (r >> 4) & 0xf;
68}
69static inline u32 mc_boot_0_minor_revision_v(u32 r)
70{
71 return (r >> 0) & 0xf;
72}
73static inline u32 mc_intr_r(u32 i)
74{
75 return 0x00000100 + i*4;
76}
77static inline u32 mc_intr_pfifo_pending_f(void)
78{
79 return 0x100;
80}
81static inline u32 mc_intr_hub_pending_f(void)
82{
83 return 0x200;
84}
85static inline u32 mc_intr_pgraph_pending_f(void)
86{
87 return 0x1000;
88}
89static inline u32 mc_intr_pmu_pending_f(void)
90{
91 return 0x1000000;
92}
93static inline u32 mc_intr_ltc_pending_f(void)
94{
95 return 0x2000000;
96}
97static inline u32 mc_intr_priv_ring_pending_f(void)
98{
99 return 0x40000000;
100}
101static inline u32 mc_intr_pbus_pending_f(void)
102{
103 return 0x10000000;
104}
105static inline u32 mc_intr_en_r(u32 i)
106{
107 return 0x00000140 + i*4;
108}
109static inline u32 mc_intr_en_set_r(u32 i)
110{
111 return 0x00000160 + i*4;
112}
113static inline u32 mc_intr_en_clear_r(u32 i)
114{
115 return 0x00000180 + i*4;
116}
117static inline u32 mc_enable_r(void)
118{
119 return 0x00000200;
120}
121static inline u32 mc_enable_xbar_enabled_f(void)
122{
123 return 0x4;
124}
125static inline u32 mc_enable_l2_enabled_f(void)
126{
127 return 0x8;
128}
129static inline u32 mc_enable_pmedia_s(void)
130{
131 return 1;
132}
133static inline u32 mc_enable_pmedia_f(u32 v)
134{
135 return (v & 0x1) << 4;
136}
137static inline u32 mc_enable_pmedia_m(void)
138{
139 return 0x1 << 4;
140}
141static inline u32 mc_enable_pmedia_v(u32 r)
142{
143 return (r >> 4) & 0x1;
144}
145static inline u32 mc_enable_ce0_m(void)
146{
147 return 0x1 << 6;
148}
149static inline u32 mc_enable_pfifo_enabled_f(void)
150{
151 return 0x100;
152}
153static inline u32 mc_enable_pgraph_enabled_f(void)
154{
155 return 0x1000;
156}
157static inline u32 mc_enable_pwr_v(u32 r)
158{
159 return (r >> 13) & 0x1;
160}
161static inline u32 mc_enable_pwr_disabled_v(void)
162{
163 return 0x00000000;
164}
165static inline u32 mc_enable_pwr_enabled_f(void)
166{
167 return 0x2000;
168}
169static inline u32 mc_enable_pfb_enabled_f(void)
170{
171 return 0x100000;
172}
173static inline u32 mc_enable_ce2_m(void)
174{
175 return 0x1 << 21;
176}
177static inline u32 mc_enable_ce2_enabled_f(void)
178{
179 return 0x200000;
180}
181static inline u32 mc_enable_blg_enabled_f(void)
182{
183 return 0x8000000;
184}
185static inline u32 mc_enable_perfmon_enabled_f(void)
186{
187 return 0x10000000;
188}
189static inline u32 mc_enable_hub_enabled_f(void)
190{
191 return 0x20000000;
192}
193static inline u32 mc_intr_ltc_r(void)
194{
195 return 0x000001c0;
196}
197static inline u32 mc_enable_pb_r(void)
198{
199 return 0x00000204;
200}
201static inline u32 mc_enable_pb_0_s(void)
202{
203 return 1;
204}
205static inline u32 mc_enable_pb_0_f(u32 v)
206{
207 return (v & 0x1) << 0;
208}
209static inline u32 mc_enable_pb_0_m(void)
210{
211 return 0x1 << 0;
212}
213static inline u32 mc_enable_pb_0_v(u32 r)
214{
215 return (r >> 0) & 0x1;
216}
217static inline u32 mc_enable_pb_0_enabled_v(void)
218{
219 return 0x00000001;
220}
221static inline u32 mc_enable_pb_sel_f(u32 v, u32 i)
222{
223 return (v & 0x1) << (0 + i*1);
224}
225static inline u32 mc_elpg_enable_r(void)
226{
227 return 0x0000020c;
228}
229static inline u32 mc_elpg_enable_xbar_enabled_f(void)
230{
231 return 0x4;
232}
233static inline u32 mc_elpg_enable_pfb_enabled_f(void)
234{
235 return 0x100000;
236}
237static inline u32 mc_elpg_enable_hub_enabled_f(void)
238{
239 return 0x20000000;
240}
241static inline u32 mc_elpg_enable_l2_enabled_f(void)
242{
243 return 0x8;
244}
245#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h
new file mode 100644
index 00000000..ab363e94
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h
@@ -0,0 +1,645 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_pbdma_gv100_h_
51#define _hw_pbdma_gv100_h_
52
53static inline u32 pbdma_gp_entry1_r(void)
54{
55 return 0x10000004;
56}
57static inline u32 pbdma_gp_entry1_get_hi_v(u32 r)
58{
59 return (r >> 0) & 0xff;
60}
61static inline u32 pbdma_gp_entry1_length_f(u32 v)
62{
63 return (v & 0x1fffff) << 10;
64}
65static inline u32 pbdma_gp_entry1_length_v(u32 r)
66{
67 return (r >> 10) & 0x1fffff;
68}
69static inline u32 pbdma_gp_base_r(u32 i)
70{
71 return 0x00040048 + i*8192;
72}
73static inline u32 pbdma_gp_base__size_1_v(void)
74{
75 return 0x0000000e;
76}
77static inline u32 pbdma_gp_base_offset_f(u32 v)
78{
79 return (v & 0x1fffffff) << 3;
80}
81static inline u32 pbdma_gp_base_rsvd_s(void)
82{
83 return 3;
84}
85static inline u32 pbdma_gp_base_hi_r(u32 i)
86{
87 return 0x0004004c + i*8192;
88}
89static inline u32 pbdma_gp_base_hi_offset_f(u32 v)
90{
91 return (v & 0xff) << 0;
92}
93static inline u32 pbdma_gp_base_hi_limit2_f(u32 v)
94{
95 return (v & 0x1f) << 16;
96}
97static inline u32 pbdma_gp_fetch_r(u32 i)
98{
99 return 0x00040050 + i*8192;
100}
101static inline u32 pbdma_gp_get_r(u32 i)
102{
103 return 0x00040014 + i*8192;
104}
105static inline u32 pbdma_gp_put_r(u32 i)
106{
107 return 0x00040000 + i*8192;
108}
109static inline u32 pbdma_pb_fetch_r(u32 i)
110{
111 return 0x00040054 + i*8192;
112}
113static inline u32 pbdma_pb_fetch_hi_r(u32 i)
114{
115 return 0x00040058 + i*8192;
116}
117static inline u32 pbdma_get_r(u32 i)
118{
119 return 0x00040018 + i*8192;
120}
121static inline u32 pbdma_get_hi_r(u32 i)
122{
123 return 0x0004001c + i*8192;
124}
125static inline u32 pbdma_put_r(u32 i)
126{
127 return 0x0004005c + i*8192;
128}
129static inline u32 pbdma_put_hi_r(u32 i)
130{
131 return 0x00040060 + i*8192;
132}
133static inline u32 pbdma_pb_header_r(u32 i)
134{
135 return 0x00040084 + i*8192;
136}
137static inline u32 pbdma_pb_header_priv_user_f(void)
138{
139 return 0x0;
140}
141static inline u32 pbdma_pb_header_method_zero_f(void)
142{
143 return 0x0;
144}
145static inline u32 pbdma_pb_header_subchannel_zero_f(void)
146{
147 return 0x0;
148}
149static inline u32 pbdma_pb_header_level_main_f(void)
150{
151 return 0x0;
152}
153static inline u32 pbdma_pb_header_first_true_f(void)
154{
155 return 0x400000;
156}
157static inline u32 pbdma_pb_header_type_inc_f(void)
158{
159 return 0x20000000;
160}
161static inline u32 pbdma_pb_header_type_non_inc_f(void)
162{
163 return 0x60000000;
164}
165static inline u32 pbdma_hdr_shadow_r(u32 i)
166{
167 return 0x00040118 + i*8192;
168}
169static inline u32 pbdma_subdevice_r(u32 i)
170{
171 return 0x00040094 + i*8192;
172}
173static inline u32 pbdma_subdevice_id_f(u32 v)
174{
175 return (v & 0xfff) << 0;
176}
177static inline u32 pbdma_subdevice_status_active_f(void)
178{
179 return 0x10000000;
180}
181static inline u32 pbdma_subdevice_channel_dma_enable_f(void)
182{
183 return 0x20000000;
184}
185static inline u32 pbdma_method0_r(u32 i)
186{
187 return 0x000400c0 + i*8192;
188}
189static inline u32 pbdma_method0_fifo_size_v(void)
190{
191 return 0x00000004;
192}
193static inline u32 pbdma_method0_addr_f(u32 v)
194{
195 return (v & 0xfff) << 2;
196}
197static inline u32 pbdma_method0_addr_v(u32 r)
198{
199 return (r >> 2) & 0xfff;
200}
201static inline u32 pbdma_method0_subch_v(u32 r)
202{
203 return (r >> 16) & 0x7;
204}
205static inline u32 pbdma_method0_first_true_f(void)
206{
207 return 0x400000;
208}
209static inline u32 pbdma_method0_valid_true_f(void)
210{
211 return 0x80000000;
212}
213static inline u32 pbdma_method1_r(u32 i)
214{
215 return 0x000400c8 + i*8192;
216}
217static inline u32 pbdma_method2_r(u32 i)
218{
219 return 0x000400d0 + i*8192;
220}
221static inline u32 pbdma_method3_r(u32 i)
222{
223 return 0x000400d8 + i*8192;
224}
225static inline u32 pbdma_data0_r(u32 i)
226{
227 return 0x000400c4 + i*8192;
228}
229static inline u32 pbdma_acquire_r(u32 i)
230{
231 return 0x00040030 + i*8192;
232}
233static inline u32 pbdma_acquire_retry_man_2_f(void)
234{
235 return 0x2;
236}
237static inline u32 pbdma_acquire_retry_exp_2_f(void)
238{
239 return 0x100;
240}
241static inline u32 pbdma_acquire_timeout_exp_f(u32 v)
242{
243 return (v & 0xf) << 11;
244}
245static inline u32 pbdma_acquire_timeout_exp_max_v(void)
246{
247 return 0x0000000f;
248}
249static inline u32 pbdma_acquire_timeout_exp_max_f(void)
250{
251 return 0x7800;
252}
253static inline u32 pbdma_acquire_timeout_man_f(u32 v)
254{
255 return (v & 0xffff) << 15;
256}
257static inline u32 pbdma_acquire_timeout_man_max_v(void)
258{
259 return 0x0000ffff;
260}
261static inline u32 pbdma_acquire_timeout_man_max_f(void)
262{
263 return 0x7fff8000;
264}
265static inline u32 pbdma_acquire_timeout_en_enable_f(void)
266{
267 return 0x80000000;
268}
269static inline u32 pbdma_acquire_timeout_en_disable_f(void)
270{
271 return 0x0;
272}
273static inline u32 pbdma_status_r(u32 i)
274{
275 return 0x00040100 + i*8192;
276}
277static inline u32 pbdma_channel_r(u32 i)
278{
279 return 0x00040120 + i*8192;
280}
281static inline u32 pbdma_signature_r(u32 i)
282{
283 return 0x00040010 + i*8192;
284}
285static inline u32 pbdma_signature_hw_valid_f(void)
286{
287 return 0xface;
288}
289static inline u32 pbdma_signature_sw_zero_f(void)
290{
291 return 0x0;
292}
293static inline u32 pbdma_userd_r(u32 i)
294{
295 return 0x00040008 + i*8192;
296}
297static inline u32 pbdma_userd_target_vid_mem_f(void)
298{
299 return 0x0;
300}
301static inline u32 pbdma_userd_target_sys_mem_coh_f(void)
302{
303 return 0x2;
304}
305static inline u32 pbdma_userd_target_sys_mem_ncoh_f(void)
306{
307 return 0x3;
308}
309static inline u32 pbdma_userd_addr_f(u32 v)
310{
311 return (v & 0x7fffff) << 9;
312}
313static inline u32 pbdma_config_r(u32 i)
314{
315 return 0x000400f4 + i*8192;
316}
317static inline u32 pbdma_config_l2_evict_first_f(void)
318{
319 return 0x0;
320}
321static inline u32 pbdma_config_l2_evict_normal_f(void)
322{
323 return 0x1;
324}
325static inline u32 pbdma_config_l2_evict_last_f(void)
326{
327 return 0x2;
328}
329static inline u32 pbdma_config_ce_split_enable_f(void)
330{
331 return 0x0;
332}
333static inline u32 pbdma_config_ce_split_disable_f(void)
334{
335 return 0x10;
336}
337static inline u32 pbdma_config_auth_level_non_privileged_f(void)
338{
339 return 0x0;
340}
341static inline u32 pbdma_config_auth_level_privileged_f(void)
342{
343 return 0x100;
344}
345static inline u32 pbdma_config_userd_writeback_disable_f(void)
346{
347 return 0x0;
348}
349static inline u32 pbdma_config_userd_writeback_enable_f(void)
350{
351 return 0x1000;
352}
353static inline u32 pbdma_userd_hi_r(u32 i)
354{
355 return 0x0004000c + i*8192;
356}
357static inline u32 pbdma_userd_hi_addr_f(u32 v)
358{
359 return (v & 0xff) << 0;
360}
361static inline u32 pbdma_hce_ctrl_r(u32 i)
362{
363 return 0x000400e4 + i*8192;
364}
365static inline u32 pbdma_hce_ctrl_hce_priv_mode_yes_f(void)
366{
367 return 0x20;
368}
369static inline u32 pbdma_intr_0_r(u32 i)
370{
371 return 0x00040108 + i*8192;
372}
373static inline u32 pbdma_intr_0_memreq_v(u32 r)
374{
375 return (r >> 0) & 0x1;
376}
377static inline u32 pbdma_intr_0_memreq_pending_f(void)
378{
379 return 0x1;
380}
381static inline u32 pbdma_intr_0_memack_timeout_pending_f(void)
382{
383 return 0x2;
384}
385static inline u32 pbdma_intr_0_memack_extra_pending_f(void)
386{
387 return 0x4;
388}
389static inline u32 pbdma_intr_0_memdat_timeout_pending_f(void)
390{
391 return 0x8;
392}
393static inline u32 pbdma_intr_0_memdat_extra_pending_f(void)
394{
395 return 0x10;
396}
397static inline u32 pbdma_intr_0_memflush_pending_f(void)
398{
399 return 0x20;
400}
401static inline u32 pbdma_intr_0_memop_pending_f(void)
402{
403 return 0x40;
404}
405static inline u32 pbdma_intr_0_lbconnect_pending_f(void)
406{
407 return 0x80;
408}
409static inline u32 pbdma_intr_0_lbreq_pending_f(void)
410{
411 return 0x100;
412}
413static inline u32 pbdma_intr_0_lback_timeout_pending_f(void)
414{
415 return 0x200;
416}
417static inline u32 pbdma_intr_0_lback_extra_pending_f(void)
418{
419 return 0x400;
420}
421static inline u32 pbdma_intr_0_lbdat_timeout_pending_f(void)
422{
423 return 0x800;
424}
425static inline u32 pbdma_intr_0_lbdat_extra_pending_f(void)
426{
427 return 0x1000;
428}
429static inline u32 pbdma_intr_0_gpfifo_pending_f(void)
430{
431 return 0x2000;
432}
433static inline u32 pbdma_intr_0_gpptr_pending_f(void)
434{
435 return 0x4000;
436}
437static inline u32 pbdma_intr_0_gpentry_pending_f(void)
438{
439 return 0x8000;
440}
441static inline u32 pbdma_intr_0_gpcrc_pending_f(void)
442{
443 return 0x10000;
444}
445static inline u32 pbdma_intr_0_pbptr_pending_f(void)
446{
447 return 0x20000;
448}
449static inline u32 pbdma_intr_0_pbentry_pending_f(void)
450{
451 return 0x40000;
452}
453static inline u32 pbdma_intr_0_pbcrc_pending_f(void)
454{
455 return 0x80000;
456}
457static inline u32 pbdma_intr_0_clear_faulted_error_pending_f(void)
458{
459 return 0x100000;
460}
461static inline u32 pbdma_intr_0_method_pending_f(void)
462{
463 return 0x200000;
464}
465static inline u32 pbdma_intr_0_methodcrc_pending_f(void)
466{
467 return 0x400000;
468}
469static inline u32 pbdma_intr_0_device_pending_f(void)
470{
471 return 0x800000;
472}
473static inline u32 pbdma_intr_0_eng_reset_pending_f(void)
474{
475 return 0x1000000;
476}
477static inline u32 pbdma_intr_0_semaphore_pending_f(void)
478{
479 return 0x2000000;
480}
481static inline u32 pbdma_intr_0_acquire_pending_f(void)
482{
483 return 0x4000000;
484}
485static inline u32 pbdma_intr_0_pri_pending_f(void)
486{
487 return 0x8000000;
488}
489static inline u32 pbdma_intr_0_no_ctxsw_seg_pending_f(void)
490{
491 return 0x20000000;
492}
493static inline u32 pbdma_intr_0_pbseg_pending_f(void)
494{
495 return 0x40000000;
496}
497static inline u32 pbdma_intr_0_signature_pending_f(void)
498{
499 return 0x80000000;
500}
501static inline u32 pbdma_intr_1_r(u32 i)
502{
503 return 0x00040148 + i*8192;
504}
505static inline u32 pbdma_intr_1_ctxnotvalid_m(void)
506{
507 return 0x1 << 31;
508}
509static inline u32 pbdma_intr_1_ctxnotvalid_pending_f(void)
510{
511 return 0x80000000;
512}
513static inline u32 pbdma_intr_en_0_r(u32 i)
514{
515 return 0x0004010c + i*8192;
516}
517static inline u32 pbdma_intr_en_0_lbreq_enabled_f(void)
518{
519 return 0x100;
520}
521static inline u32 pbdma_intr_en_1_r(u32 i)
522{
523 return 0x0004014c + i*8192;
524}
525static inline u32 pbdma_intr_stall_r(u32 i)
526{
527 return 0x0004013c + i*8192;
528}
529static inline u32 pbdma_intr_stall_lbreq_enabled_f(void)
530{
531 return 0x100;
532}
533static inline u32 pbdma_intr_stall_1_r(u32 i)
534{
535 return 0x00040140 + i*8192;
536}
537static inline u32 pbdma_udma_nop_r(void)
538{
539 return 0x00000008;
540}
541static inline u32 pbdma_runlist_timeslice_r(u32 i)
542{
543 return 0x000400f8 + i*8192;
544}
545static inline u32 pbdma_runlist_timeslice_timeout_128_f(void)
546{
547 return 0x80;
548}
549static inline u32 pbdma_runlist_timeslice_timescale_3_f(void)
550{
551 return 0x3000;
552}
553static inline u32 pbdma_runlist_timeslice_enable_true_f(void)
554{
555 return 0x10000000;
556}
557static inline u32 pbdma_target_r(u32 i)
558{
559 return 0x000400ac + i*8192;
560}
561static inline u32 pbdma_target_engine_sw_f(void)
562{
563 return 0x1f;
564}
565static inline u32 pbdma_target_eng_ctx_valid_true_f(void)
566{
567 return 0x10000;
568}
569static inline u32 pbdma_target_eng_ctx_valid_false_f(void)
570{
571 return 0x0;
572}
573static inline u32 pbdma_target_ce_ctx_valid_true_f(void)
574{
575 return 0x20000;
576}
577static inline u32 pbdma_target_ce_ctx_valid_false_f(void)
578{
579 return 0x0;
580}
581static inline u32 pbdma_target_host_tsg_event_reason_pbdma_idle_f(void)
582{
583 return 0x0;
584}
585static inline u32 pbdma_target_host_tsg_event_reason_semaphore_acquire_failure_f(void)
586{
587 return 0x1000000;
588}
589static inline u32 pbdma_target_host_tsg_event_reason_tsg_yield_f(void)
590{
591 return 0x2000000;
592}
593static inline u32 pbdma_target_host_tsg_event_reason_host_subchannel_switch_f(void)
594{
595 return 0x3000000;
596}
597static inline u32 pbdma_target_should_send_tsg_event_true_f(void)
598{
599 return 0x20000000;
600}
601static inline u32 pbdma_target_should_send_tsg_event_false_f(void)
602{
603 return 0x0;
604}
605static inline u32 pbdma_target_needs_host_tsg_event_true_f(void)
606{
607 return 0x80000000;
608}
609static inline u32 pbdma_target_needs_host_tsg_event_false_f(void)
610{
611 return 0x0;
612}
613static inline u32 pbdma_set_channel_info_r(u32 i)
614{
615 return 0x000400fc + i*8192;
616}
617static inline u32 pbdma_set_channel_info_scg_type_graphics_compute0_f(void)
618{
619 return 0x0;
620}
621static inline u32 pbdma_set_channel_info_scg_type_compute1_f(void)
622{
623 return 0x1;
624}
625static inline u32 pbdma_set_channel_info_veid_f(u32 v)
626{
627 return (v & 0x3f) << 8;
628}
629static inline u32 pbdma_timeout_r(u32 i)
630{
631 return 0x0004012c + i*8192;
632}
633static inline u32 pbdma_timeout_period_m(void)
634{
635 return 0xffffffff << 0;
636}
637static inline u32 pbdma_timeout_period_max_f(void)
638{
639 return 0xffffffff;
640}
641static inline u32 pbdma_timeout_period_init_f(void)
642{
643 return 0x10000;
644}
645#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h
new file mode 100644
index 00000000..f8e7c2a4
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h
@@ -0,0 +1,205 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_perf_gv100_h_
51#define _hw_perf_gv100_h_
52
53static inline u32 perf_pmasys_control_r(void)
54{
55 return 0x0024a000;
56}
57static inline u32 perf_pmasys_control_membuf_status_v(u32 r)
58{
59 return (r >> 4) & 0x1;
60}
61static inline u32 perf_pmasys_control_membuf_status_overflowed_v(void)
62{
63 return 0x00000001;
64}
65static inline u32 perf_pmasys_control_membuf_status_overflowed_f(void)
66{
67 return 0x10;
68}
69static inline u32 perf_pmasys_control_membuf_clear_status_f(u32 v)
70{
71 return (v & 0x1) << 5;
72}
73static inline u32 perf_pmasys_control_membuf_clear_status_v(u32 r)
74{
75 return (r >> 5) & 0x1;
76}
77static inline u32 perf_pmasys_control_membuf_clear_status_doit_v(void)
78{
79 return 0x00000001;
80}
81static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void)
82{
83 return 0x20;
84}
85static inline u32 perf_pmasys_mem_block_r(void)
86{
87 return 0x0024a070;
88}
89static inline u32 perf_pmasys_mem_block_base_f(u32 v)
90{
91 return (v & 0xfffffff) << 0;
92}
93static inline u32 perf_pmasys_mem_block_target_f(u32 v)
94{
95 return (v & 0x3) << 28;
96}
97static inline u32 perf_pmasys_mem_block_target_v(u32 r)
98{
99 return (r >> 28) & 0x3;
100}
101static inline u32 perf_pmasys_mem_block_target_lfb_v(void)
102{
103 return 0x00000000;
104}
105static inline u32 perf_pmasys_mem_block_target_lfb_f(void)
106{
107 return 0x0;
108}
109static inline u32 perf_pmasys_mem_block_target_sys_coh_v(void)
110{
111 return 0x00000002;
112}
113static inline u32 perf_pmasys_mem_block_target_sys_coh_f(void)
114{
115 return 0x20000000;
116}
117static inline u32 perf_pmasys_mem_block_target_sys_ncoh_v(void)
118{
119 return 0x00000003;
120}
121static inline u32 perf_pmasys_mem_block_target_sys_ncoh_f(void)
122{
123 return 0x30000000;
124}
125static inline u32 perf_pmasys_mem_block_valid_f(u32 v)
126{
127 return (v & 0x1) << 31;
128}
129static inline u32 perf_pmasys_mem_block_valid_v(u32 r)
130{
131 return (r >> 31) & 0x1;
132}
133static inline u32 perf_pmasys_mem_block_valid_true_v(void)
134{
135 return 0x00000001;
136}
137static inline u32 perf_pmasys_mem_block_valid_true_f(void)
138{
139 return 0x80000000;
140}
141static inline u32 perf_pmasys_mem_block_valid_false_v(void)
142{
143 return 0x00000000;
144}
145static inline u32 perf_pmasys_mem_block_valid_false_f(void)
146{
147 return 0x0;
148}
149static inline u32 perf_pmasys_outbase_r(void)
150{
151 return 0x0024a074;
152}
153static inline u32 perf_pmasys_outbase_ptr_f(u32 v)
154{
155 return (v & 0x7ffffff) << 5;
156}
157static inline u32 perf_pmasys_outbaseupper_r(void)
158{
159 return 0x0024a078;
160}
161static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v)
162{
163 return (v & 0xff) << 0;
164}
165static inline u32 perf_pmasys_outsize_r(void)
166{
167 return 0x0024a07c;
168}
169static inline u32 perf_pmasys_outsize_numbytes_f(u32 v)
170{
171 return (v & 0x7ffffff) << 5;
172}
173static inline u32 perf_pmasys_mem_bytes_r(void)
174{
175 return 0x0024a084;
176}
177static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v)
178{
179 return (v & 0xfffffff) << 4;
180}
181static inline u32 perf_pmasys_mem_bump_r(void)
182{
183 return 0x0024a088;
184}
185static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v)
186{
187 return (v & 0xfffffff) << 4;
188}
189static inline u32 perf_pmasys_enginestatus_r(void)
190{
191 return 0x0024a0a4;
192}
193static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v)
194{
195 return (v & 0x1) << 4;
196}
197static inline u32 perf_pmasys_enginestatus_rbufempty_empty_v(void)
198{
199 return 0x00000001;
200}
201static inline u32 perf_pmasys_enginestatus_rbufempty_empty_f(void)
202{
203 return 0x10;
204}
205#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pram_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pram_gv100.h
new file mode 100644
index 00000000..88c70f53
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pram_gv100.h
@@ -0,0 +1,57 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_pram_gv100_h_
51#define _hw_pram_gv100_h_
52
53static inline u32 pram_data032_r(u32 i)
54{
55 return 0x00700000 + i*4;
56}
57#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h
new file mode 100644
index 00000000..197fe550
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h
@@ -0,0 +1,161 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_pri_ringmaster_gv100_h_
51#define _hw_pri_ringmaster_gv100_h_
52
53static inline u32 pri_ringmaster_command_r(void)
54{
55 return 0x0012004c;
56}
57static inline u32 pri_ringmaster_command_cmd_m(void)
58{
59 return 0x3f << 0;
60}
61static inline u32 pri_ringmaster_command_cmd_v(u32 r)
62{
63 return (r >> 0) & 0x3f;
64}
65static inline u32 pri_ringmaster_command_cmd_no_cmd_v(void)
66{
67 return 0x00000000;
68}
69static inline u32 pri_ringmaster_command_cmd_start_ring_f(void)
70{
71 return 0x1;
72}
73static inline u32 pri_ringmaster_command_cmd_ack_interrupt_f(void)
74{
75 return 0x2;
76}
77static inline u32 pri_ringmaster_command_cmd_enumerate_stations_f(void)
78{
79 return 0x3;
80}
81static inline u32 pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f(void)
82{
83 return 0x0;
84}
85static inline u32 pri_ringmaster_command_data_r(void)
86{
87 return 0x00120048;
88}
89static inline u32 pri_ringmaster_start_results_r(void)
90{
91 return 0x00120050;
92}
93static inline u32 pri_ringmaster_start_results_connectivity_v(u32 r)
94{
95 return (r >> 0) & 0x1;
96}
97static inline u32 pri_ringmaster_start_results_connectivity_pass_v(void)
98{
99 return 0x00000001;
100}
101static inline u32 pri_ringmaster_intr_status0_r(void)
102{
103 return 0x00120058;
104}
105static inline u32 pri_ringmaster_intr_status0_ring_start_conn_fault_v(u32 r)
106{
107 return (r >> 0) & 0x1;
108}
109static inline u32 pri_ringmaster_intr_status0_disconnect_fault_v(u32 r)
110{
111 return (r >> 1) & 0x1;
112}
113static inline u32 pri_ringmaster_intr_status0_overflow_fault_v(u32 r)
114{
115 return (r >> 2) & 0x1;
116}
117static inline u32 pri_ringmaster_intr_status0_gbl_write_error_sys_v(u32 r)
118{
119 return (r >> 8) & 0x1;
120}
121static inline u32 pri_ringmaster_intr_status1_r(void)
122{
123 return 0x0012005c;
124}
125static inline u32 pri_ringmaster_global_ctl_r(void)
126{
127 return 0x00120060;
128}
129static inline u32 pri_ringmaster_global_ctl_ring_reset_asserted_f(void)
130{
131 return 0x1;
132}
133static inline u32 pri_ringmaster_global_ctl_ring_reset_deasserted_f(void)
134{
135 return 0x0;
136}
137static inline u32 pri_ringmaster_enum_fbp_r(void)
138{
139 return 0x00120074;
140}
141static inline u32 pri_ringmaster_enum_fbp_count_v(u32 r)
142{
143 return (r >> 0) & 0x1f;
144}
145static inline u32 pri_ringmaster_enum_gpc_r(void)
146{
147 return 0x00120078;
148}
149static inline u32 pri_ringmaster_enum_gpc_count_v(u32 r)
150{
151 return (r >> 0) & 0x1f;
152}
153static inline u32 pri_ringmaster_enum_ltc_r(void)
154{
155 return 0x0012006c;
156}
157static inline u32 pri_ringmaster_enum_ltc_count_v(u32 r)
158{
159 return (r >> 0) & 0x1f;
160}
161#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h
new file mode 100644
index 00000000..eb77b4c0
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h
@@ -0,0 +1,73 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_pri_ringstation_gpc_gv100_h_
51#define _hw_pri_ringstation_gpc_gv100_h_
52
53static inline u32 pri_ringstation_gpc_master_config_r(u32 i)
54{
55 return 0x00128300 + i*4;
56}
57static inline u32 pri_ringstation_gpc_gpc0_priv_error_adr_r(void)
58{
59 return 0x00128120;
60}
61static inline u32 pri_ringstation_gpc_gpc0_priv_error_wrdat_r(void)
62{
63 return 0x00128124;
64}
65static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_r(void)
66{
67 return 0x00128128;
68}
69static inline u32 pri_ringstation_gpc_gpc0_priv_error_code_r(void)
70{
71 return 0x0012812c;
72}
73#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h
new file mode 100644
index 00000000..27feb5e9
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h
@@ -0,0 +1,85 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_pri_ringstation_sys_gv100_h_
51#define _hw_pri_ringstation_sys_gv100_h_
52
53static inline u32 pri_ringstation_sys_master_config_r(u32 i)
54{
55 return 0x00122300 + i*4;
56}
57static inline u32 pri_ringstation_sys_decode_config_r(void)
58{
59 return 0x00122204;
60}
61static inline u32 pri_ringstation_sys_decode_config_ring_m(void)
62{
63 return 0x7 << 0;
64}
65static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void)
66{
67 return 0x1;
68}
69static inline u32 pri_ringstation_sys_priv_error_adr_r(void)
70{
71 return 0x00122120;
72}
73static inline u32 pri_ringstation_sys_priv_error_wrdat_r(void)
74{
75 return 0x00122124;
76}
77static inline u32 pri_ringstation_sys_priv_error_info_r(void)
78{
79 return 0x00122128;
80}
81static inline u32 pri_ringstation_sys_priv_error_code_r(void)
82{
83 return 0x0012212c;
84}
85#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h
new file mode 100644
index 00000000..44e804e7
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h
@@ -0,0 +1,161 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_proj_gv100_h_
51#define _hw_proj_gv100_h_
52
53static inline u32 proj_gpc_base_v(void)
54{
55 return 0x00500000;
56}
57static inline u32 proj_gpc_shared_base_v(void)
58{
59 return 0x00418000;
60}
61static inline u32 proj_gpc_stride_v(void)
62{
63 return 0x00008000;
64}
65static inline u32 proj_ltc_stride_v(void)
66{
67 return 0x00002000;
68}
69static inline u32 proj_lts_stride_v(void)
70{
71 return 0x00000200;
72}
73static inline u32 proj_fbpa_stride_v(void)
74{
75 return 0x00004000;
76}
77static inline u32 proj_ppc_in_gpc_base_v(void)
78{
79 return 0x00003000;
80}
81static inline u32 proj_ppc_in_gpc_stride_v(void)
82{
83 return 0x00000200;
84}
85static inline u32 proj_rop_base_v(void)
86{
87 return 0x00410000;
88}
89static inline u32 proj_rop_shared_base_v(void)
90{
91 return 0x00408800;
92}
93static inline u32 proj_rop_stride_v(void)
94{
95 return 0x00000400;
96}
97static inline u32 proj_tpc_in_gpc_base_v(void)
98{
99 return 0x00004000;
100}
101static inline u32 proj_tpc_in_gpc_stride_v(void)
102{
103 return 0x00000800;
104}
105static inline u32 proj_tpc_in_gpc_shared_base_v(void)
106{
107 return 0x00001800;
108}
109static inline u32 proj_host_num_engines_v(void)
110{
111 return 0x0000000f;
112}
113static inline u32 proj_host_num_pbdma_v(void)
114{
115 return 0x0000000e;
116}
117static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void)
118{
119 return 0x00000007;
120}
121static inline u32 proj_scal_litter_num_fbps_v(void)
122{
123 return 0x00000008;
124}
125static inline u32 proj_scal_litter_num_fbpas_v(void)
126{
127 return 0x00000010;
128}
129static inline u32 proj_scal_litter_num_gpcs_v(void)
130{
131 return 0x00000006;
132}
133static inline u32 proj_scal_litter_num_pes_per_gpc_v(void)
134{
135 return 0x00000003;
136}
137static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void)
138{
139 return 0x00000003;
140}
141static inline u32 proj_scal_litter_num_zcull_banks_v(void)
142{
143 return 0x00000004;
144}
145static inline u32 proj_scal_litter_num_sm_per_tpc_v(void)
146{
147 return 0x00000002;
148}
149static inline u32 proj_scal_max_gpcs_v(void)
150{
151 return 0x00000020;
152}
153static inline u32 proj_scal_max_tpc_per_gpc_v(void)
154{
155 return 0x00000008;
156}
157static inline u32 proj_sm_stride_v(void)
158{
159 return 0x00000080;
160}
161#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h
new file mode 100644
index 00000000..7d83b4ae
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h
@@ -0,0 +1,929 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_pwr_gv100_h_
51#define _hw_pwr_gv100_h_
52
53static inline u32 pwr_falcon_irqsset_r(void)
54{
55 return 0x0010a000;
56}
57static inline u32 pwr_falcon_irqsset_swgen0_set_f(void)
58{
59 return 0x40;
60}
61static inline u32 pwr_falcon_irqsclr_r(void)
62{
63 return 0x0010a004;
64}
65static inline u32 pwr_falcon_irqstat_r(void)
66{
67 return 0x0010a008;
68}
69static inline u32 pwr_falcon_irqstat_halt_true_f(void)
70{
71 return 0x10;
72}
73static inline u32 pwr_falcon_irqstat_exterr_true_f(void)
74{
75 return 0x20;
76}
77static inline u32 pwr_falcon_irqstat_swgen0_true_f(void)
78{
79 return 0x40;
80}
81static inline u32 pwr_falcon_irqstat_ext_second_true_f(void)
82{
83 return 0x800;
84}
85static inline u32 pwr_falcon_irqmode_r(void)
86{
87 return 0x0010a00c;
88}
89static inline u32 pwr_falcon_irqmset_r(void)
90{
91 return 0x0010a010;
92}
93static inline u32 pwr_falcon_irqmset_gptmr_f(u32 v)
94{
95 return (v & 0x1) << 0;
96}
97static inline u32 pwr_falcon_irqmset_wdtmr_f(u32 v)
98{
99 return (v & 0x1) << 1;
100}
101static inline u32 pwr_falcon_irqmset_mthd_f(u32 v)
102{
103 return (v & 0x1) << 2;
104}
105static inline u32 pwr_falcon_irqmset_ctxsw_f(u32 v)
106{
107 return (v & 0x1) << 3;
108}
109static inline u32 pwr_falcon_irqmset_halt_f(u32 v)
110{
111 return (v & 0x1) << 4;
112}
113static inline u32 pwr_falcon_irqmset_exterr_f(u32 v)
114{
115 return (v & 0x1) << 5;
116}
117static inline u32 pwr_falcon_irqmset_swgen0_f(u32 v)
118{
119 return (v & 0x1) << 6;
120}
121static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v)
122{
123 return (v & 0x1) << 7;
124}
125static inline u32 pwr_falcon_irqmset_ext_f(u32 v)
126{
127 return (v & 0xff) << 8;
128}
129static inline u32 pwr_falcon_irqmset_ext_ctxe_f(u32 v)
130{
131 return (v & 0x1) << 8;
132}
133static inline u32 pwr_falcon_irqmset_ext_limitv_f(u32 v)
134{
135 return (v & 0x1) << 9;
136}
137static inline u32 pwr_falcon_irqmset_ext_second_f(u32 v)
138{
139 return (v & 0x1) << 11;
140}
141static inline u32 pwr_falcon_irqmset_ext_therm_f(u32 v)
142{
143 return (v & 0x1) << 12;
144}
145static inline u32 pwr_falcon_irqmset_ext_miscio_f(u32 v)
146{
147 return (v & 0x1) << 13;
148}
149static inline u32 pwr_falcon_irqmset_ext_rttimer_f(u32 v)
150{
151 return (v & 0x1) << 14;
152}
153static inline u32 pwr_falcon_irqmclr_r(void)
154{
155 return 0x0010a014;
156}
157static inline u32 pwr_falcon_irqmclr_gptmr_f(u32 v)
158{
159 return (v & 0x1) << 0;
160}
161static inline u32 pwr_falcon_irqmclr_wdtmr_f(u32 v)
162{
163 return (v & 0x1) << 1;
164}
165static inline u32 pwr_falcon_irqmclr_mthd_f(u32 v)
166{
167 return (v & 0x1) << 2;
168}
169static inline u32 pwr_falcon_irqmclr_ctxsw_f(u32 v)
170{
171 return (v & 0x1) << 3;
172}
173static inline u32 pwr_falcon_irqmclr_halt_f(u32 v)
174{
175 return (v & 0x1) << 4;
176}
177static inline u32 pwr_falcon_irqmclr_exterr_f(u32 v)
178{
179 return (v & 0x1) << 5;
180}
181static inline u32 pwr_falcon_irqmclr_swgen0_f(u32 v)
182{
183 return (v & 0x1) << 6;
184}
185static inline u32 pwr_falcon_irqmclr_swgen1_f(u32 v)
186{
187 return (v & 0x1) << 7;
188}
189static inline u32 pwr_falcon_irqmclr_ext_f(u32 v)
190{
191 return (v & 0xff) << 8;
192}
193static inline u32 pwr_falcon_irqmclr_ext_ctxe_f(u32 v)
194{
195 return (v & 0x1) << 8;
196}
197static inline u32 pwr_falcon_irqmclr_ext_limitv_f(u32 v)
198{
199 return (v & 0x1) << 9;
200}
201static inline u32 pwr_falcon_irqmclr_ext_second_f(u32 v)
202{
203 return (v & 0x1) << 11;
204}
205static inline u32 pwr_falcon_irqmclr_ext_therm_f(u32 v)
206{
207 return (v & 0x1) << 12;
208}
209static inline u32 pwr_falcon_irqmclr_ext_miscio_f(u32 v)
210{
211 return (v & 0x1) << 13;
212}
213static inline u32 pwr_falcon_irqmclr_ext_rttimer_f(u32 v)
214{
215 return (v & 0x1) << 14;
216}
217static inline u32 pwr_falcon_irqmask_r(void)
218{
219 return 0x0010a018;
220}
221static inline u32 pwr_falcon_irqdest_r(void)
222{
223 return 0x0010a01c;
224}
225static inline u32 pwr_falcon_irqdest_host_gptmr_f(u32 v)
226{
227 return (v & 0x1) << 0;
228}
229static inline u32 pwr_falcon_irqdest_host_wdtmr_f(u32 v)
230{
231 return (v & 0x1) << 1;
232}
233static inline u32 pwr_falcon_irqdest_host_mthd_f(u32 v)
234{
235 return (v & 0x1) << 2;
236}
237static inline u32 pwr_falcon_irqdest_host_ctxsw_f(u32 v)
238{
239 return (v & 0x1) << 3;
240}
241static inline u32 pwr_falcon_irqdest_host_halt_f(u32 v)
242{
243 return (v & 0x1) << 4;
244}
245static inline u32 pwr_falcon_irqdest_host_exterr_f(u32 v)
246{
247 return (v & 0x1) << 5;
248}
249static inline u32 pwr_falcon_irqdest_host_swgen0_f(u32 v)
250{
251 return (v & 0x1) << 6;
252}
253static inline u32 pwr_falcon_irqdest_host_swgen1_f(u32 v)
254{
255 return (v & 0x1) << 7;
256}
257static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v)
258{
259 return (v & 0xff) << 8;
260}
261static inline u32 pwr_falcon_irqdest_host_ext_ctxe_f(u32 v)
262{
263 return (v & 0x1) << 8;
264}
265static inline u32 pwr_falcon_irqdest_host_ext_limitv_f(u32 v)
266{
267 return (v & 0x1) << 9;
268}
269static inline u32 pwr_falcon_irqdest_host_ext_second_f(u32 v)
270{
271 return (v & 0x1) << 11;
272}
273static inline u32 pwr_falcon_irqdest_host_ext_therm_f(u32 v)
274{
275 return (v & 0x1) << 12;
276}
277static inline u32 pwr_falcon_irqdest_host_ext_miscio_f(u32 v)
278{
279 return (v & 0x1) << 13;
280}
281static inline u32 pwr_falcon_irqdest_host_ext_rttimer_f(u32 v)
282{
283 return (v & 0x1) << 14;
284}
285static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v)
286{
287 return (v & 0x1) << 16;
288}
289static inline u32 pwr_falcon_irqdest_target_wdtmr_f(u32 v)
290{
291 return (v & 0x1) << 17;
292}
293static inline u32 pwr_falcon_irqdest_target_mthd_f(u32 v)
294{
295 return (v & 0x1) << 18;
296}
297static inline u32 pwr_falcon_irqdest_target_ctxsw_f(u32 v)
298{
299 return (v & 0x1) << 19;
300}
301static inline u32 pwr_falcon_irqdest_target_halt_f(u32 v)
302{
303 return (v & 0x1) << 20;
304}
305static inline u32 pwr_falcon_irqdest_target_exterr_f(u32 v)
306{
307 return (v & 0x1) << 21;
308}
309static inline u32 pwr_falcon_irqdest_target_swgen0_f(u32 v)
310{
311 return (v & 0x1) << 22;
312}
313static inline u32 pwr_falcon_irqdest_target_swgen1_f(u32 v)
314{
315 return (v & 0x1) << 23;
316}
317static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v)
318{
319 return (v & 0xff) << 24;
320}
321static inline u32 pwr_falcon_irqdest_target_ext_ctxe_f(u32 v)
322{
323 return (v & 0x1) << 24;
324}
325static inline u32 pwr_falcon_irqdest_target_ext_limitv_f(u32 v)
326{
327 return (v & 0x1) << 25;
328}
329static inline u32 pwr_falcon_irqdest_target_ext_second_f(u32 v)
330{
331 return (v & 0x1) << 27;
332}
333static inline u32 pwr_falcon_irqdest_target_ext_therm_f(u32 v)
334{
335 return (v & 0x1) << 28;
336}
337static inline u32 pwr_falcon_irqdest_target_ext_miscio_f(u32 v)
338{
339 return (v & 0x1) << 29;
340}
341static inline u32 pwr_falcon_irqdest_target_ext_rttimer_f(u32 v)
342{
343 return (v & 0x1) << 30;
344}
345static inline u32 pwr_falcon_curctx_r(void)
346{
347 return 0x0010a050;
348}
349static inline u32 pwr_falcon_nxtctx_r(void)
350{
351 return 0x0010a054;
352}
353static inline u32 pwr_falcon_mailbox0_r(void)
354{
355 return 0x0010a040;
356}
357static inline u32 pwr_falcon_mailbox1_r(void)
358{
359 return 0x0010a044;
360}
361static inline u32 pwr_falcon_itfen_r(void)
362{
363 return 0x0010a048;
364}
365static inline u32 pwr_falcon_itfen_ctxen_enable_f(void)
366{
367 return 0x1;
368}
369static inline u32 pwr_falcon_idlestate_r(void)
370{
371 return 0x0010a04c;
372}
373static inline u32 pwr_falcon_idlestate_falcon_busy_v(u32 r)
374{
375 return (r >> 0) & 0x1;
376}
377static inline u32 pwr_falcon_idlestate_ext_busy_v(u32 r)
378{
379 return (r >> 1) & 0x7fff;
380}
381static inline u32 pwr_falcon_os_r(void)
382{
383 return 0x0010a080;
384}
385static inline u32 pwr_falcon_engctl_r(void)
386{
387 return 0x0010a0a4;
388}
389static inline u32 pwr_falcon_cpuctl_r(void)
390{
391 return 0x0010a100;
392}
393static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v)
394{
395 return (v & 0x1) << 1;
396}
397static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v)
398{
399 return (v & 0x1) << 4;
400}
401static inline u32 pwr_falcon_cpuctl_halt_intr_m(void)
402{
403 return 0x1 << 4;
404}
405static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r)
406{
407 return (r >> 4) & 0x1;
408}
409static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_f(u32 v)
410{
411 return (v & 0x1) << 6;
412}
413static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_m(void)
414{
415 return 0x1 << 6;
416}
417static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_v(u32 r)
418{
419 return (r >> 6) & 0x1;
420}
421static inline u32 pwr_falcon_cpuctl_alias_r(void)
422{
423 return 0x0010a130;
424}
425static inline u32 pwr_falcon_cpuctl_alias_startcpu_f(u32 v)
426{
427 return (v & 0x1) << 1;
428}
429static inline u32 pwr_pmu_scpctl_stat_r(void)
430{
431 return 0x0010ac08;
432}
433static inline u32 pwr_pmu_scpctl_stat_debug_mode_f(u32 v)
434{
435 return (v & 0x1) << 20;
436}
437static inline u32 pwr_pmu_scpctl_stat_debug_mode_m(void)
438{
439 return 0x1 << 20;
440}
441static inline u32 pwr_pmu_scpctl_stat_debug_mode_v(u32 r)
442{
443 return (r >> 20) & 0x1;
444}
445static inline u32 pwr_falcon_imemc_r(u32 i)
446{
447 return 0x0010a180 + i*16;
448}
449static inline u32 pwr_falcon_imemc_offs_f(u32 v)
450{
451 return (v & 0x3f) << 2;
452}
453static inline u32 pwr_falcon_imemc_blk_f(u32 v)
454{
455 return (v & 0xff) << 8;
456}
457static inline u32 pwr_falcon_imemc_aincw_f(u32 v)
458{
459 return (v & 0x1) << 24;
460}
461static inline u32 pwr_falcon_imemd_r(u32 i)
462{
463 return 0x0010a184 + i*16;
464}
465static inline u32 pwr_falcon_imemt_r(u32 i)
466{
467 return 0x0010a188 + i*16;
468}
469static inline u32 pwr_falcon_sctl_r(void)
470{
471 return 0x0010a240;
472}
473static inline u32 pwr_falcon_mmu_phys_sec_r(void)
474{
475 return 0x00100ce4;
476}
477static inline u32 pwr_falcon_bootvec_r(void)
478{
479 return 0x0010a104;
480}
481static inline u32 pwr_falcon_bootvec_vec_f(u32 v)
482{
483 return (v & 0xffffffff) << 0;
484}
485static inline u32 pwr_falcon_dmactl_r(void)
486{
487 return 0x0010a10c;
488}
489static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void)
490{
491 return 0x1 << 1;
492}
493static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void)
494{
495 return 0x1 << 2;
496}
497static inline u32 pwr_falcon_hwcfg_r(void)
498{
499 return 0x0010a108;
500}
501static inline u32 pwr_falcon_hwcfg_imem_size_v(u32 r)
502{
503 return (r >> 0) & 0x1ff;
504}
505static inline u32 pwr_falcon_hwcfg_dmem_size_v(u32 r)
506{
507 return (r >> 9) & 0x1ff;
508}
509static inline u32 pwr_falcon_dmatrfbase_r(void)
510{
511 return 0x0010a110;
512}
513static inline u32 pwr_falcon_dmatrfbase1_r(void)
514{
515 return 0x0010a128;
516}
517static inline u32 pwr_falcon_dmatrfmoffs_r(void)
518{
519 return 0x0010a114;
520}
521static inline u32 pwr_falcon_dmatrfcmd_r(void)
522{
523 return 0x0010a118;
524}
525static inline u32 pwr_falcon_dmatrfcmd_imem_f(u32 v)
526{
527 return (v & 0x1) << 4;
528}
529static inline u32 pwr_falcon_dmatrfcmd_write_f(u32 v)
530{
531 return (v & 0x1) << 5;
532}
533static inline u32 pwr_falcon_dmatrfcmd_size_f(u32 v)
534{
535 return (v & 0x7) << 8;
536}
537static inline u32 pwr_falcon_dmatrfcmd_ctxdma_f(u32 v)
538{
539 return (v & 0x7) << 12;
540}
541static inline u32 pwr_falcon_dmatrffboffs_r(void)
542{
543 return 0x0010a11c;
544}
545static inline u32 pwr_falcon_exterraddr_r(void)
546{
547 return 0x0010a168;
548}
549static inline u32 pwr_falcon_exterrstat_r(void)
550{
551 return 0x0010a16c;
552}
553static inline u32 pwr_falcon_exterrstat_valid_m(void)
554{
555 return 0x1 << 31;
556}
557static inline u32 pwr_falcon_exterrstat_valid_v(u32 r)
558{
559 return (r >> 31) & 0x1;
560}
561static inline u32 pwr_falcon_exterrstat_valid_true_v(void)
562{
563 return 0x00000001;
564}
565static inline u32 pwr_pmu_falcon_icd_cmd_r(void)
566{
567 return 0x0010a200;
568}
569static inline u32 pwr_pmu_falcon_icd_cmd_opc_s(void)
570{
571 return 4;
572}
573static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v)
574{
575 return (v & 0xf) << 0;
576}
577static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void)
578{
579 return 0xf << 0;
580}
581static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r)
582{
583 return (r >> 0) & 0xf;
584}
585static inline u32 pwr_pmu_falcon_icd_cmd_opc_rreg_f(void)
586{
587 return 0x8;
588}
589static inline u32 pwr_pmu_falcon_icd_cmd_opc_rstat_f(void)
590{
591 return 0xe;
592}
593static inline u32 pwr_pmu_falcon_icd_cmd_idx_f(u32 v)
594{
595 return (v & 0x1f) << 8;
596}
597static inline u32 pwr_pmu_falcon_icd_rdata_r(void)
598{
599 return 0x0010a20c;
600}
601static inline u32 pwr_falcon_dmemc_r(u32 i)
602{
603 return 0x0010a1c0 + i*8;
604}
605static inline u32 pwr_falcon_dmemc_offs_f(u32 v)
606{
607 return (v & 0x3f) << 2;
608}
609static inline u32 pwr_falcon_dmemc_offs_m(void)
610{
611 return 0x3f << 2;
612}
613static inline u32 pwr_falcon_dmemc_blk_f(u32 v)
614{
615 return (v & 0xff) << 8;
616}
617static inline u32 pwr_falcon_dmemc_blk_m(void)
618{
619 return 0xff << 8;
620}
621static inline u32 pwr_falcon_dmemc_aincw_f(u32 v)
622{
623 return (v & 0x1) << 24;
624}
625static inline u32 pwr_falcon_dmemc_aincr_f(u32 v)
626{
627 return (v & 0x1) << 25;
628}
629static inline u32 pwr_falcon_dmemd_r(u32 i)
630{
631 return 0x0010a1c4 + i*8;
632}
633static inline u32 pwr_pmu_new_instblk_r(void)
634{
635 return 0x0010a480;
636}
637static inline u32 pwr_pmu_new_instblk_ptr_f(u32 v)
638{
639 return (v & 0xfffffff) << 0;
640}
641static inline u32 pwr_pmu_new_instblk_target_fb_f(void)
642{
643 return 0x0;
644}
645static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void)
646{
647 return 0x20000000;
648}
649static inline u32 pwr_pmu_new_instblk_target_sys_ncoh_f(void)
650{
651 return 0x30000000;
652}
653static inline u32 pwr_pmu_new_instblk_valid_f(u32 v)
654{
655 return (v & 0x1) << 30;
656}
657static inline u32 pwr_pmu_mutex_id_r(void)
658{
659 return 0x0010a488;
660}
661static inline u32 pwr_pmu_mutex_id_value_v(u32 r)
662{
663 return (r >> 0) & 0xff;
664}
665static inline u32 pwr_pmu_mutex_id_value_init_v(void)
666{
667 return 0x00000000;
668}
669static inline u32 pwr_pmu_mutex_id_value_not_avail_v(void)
670{
671 return 0x000000ff;
672}
673static inline u32 pwr_pmu_mutex_id_release_r(void)
674{
675 return 0x0010a48c;
676}
677static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v)
678{
679 return (v & 0xff) << 0;
680}
681static inline u32 pwr_pmu_mutex_id_release_value_m(void)
682{
683 return 0xff << 0;
684}
685static inline u32 pwr_pmu_mutex_id_release_value_init_v(void)
686{
687 return 0x00000000;
688}
689static inline u32 pwr_pmu_mutex_id_release_value_init_f(void)
690{
691 return 0x0;
692}
693static inline u32 pwr_pmu_mutex_r(u32 i)
694{
695 return 0x0010a580 + i*4;
696}
697static inline u32 pwr_pmu_mutex__size_1_v(void)
698{
699 return 0x00000010;
700}
701static inline u32 pwr_pmu_mutex_value_f(u32 v)
702{
703 return (v & 0xff) << 0;
704}
705static inline u32 pwr_pmu_mutex_value_v(u32 r)
706{
707 return (r >> 0) & 0xff;
708}
709static inline u32 pwr_pmu_mutex_value_initial_lock_f(void)
710{
711 return 0x0;
712}
713static inline u32 pwr_pmu_queue_head_r(u32 i)
714{
715 return 0x0010a800 + i*4;
716}
717static inline u32 pwr_pmu_queue_head__size_1_v(void)
718{
719 return 0x00000008;
720}
721static inline u32 pwr_pmu_queue_head_address_f(u32 v)
722{
723 return (v & 0xffffffff) << 0;
724}
725static inline u32 pwr_pmu_queue_head_address_v(u32 r)
726{
727 return (r >> 0) & 0xffffffff;
728}
729static inline u32 pwr_pmu_queue_tail_r(u32 i)
730{
731 return 0x0010a820 + i*4;
732}
733static inline u32 pwr_pmu_queue_tail__size_1_v(void)
734{
735 return 0x00000008;
736}
737static inline u32 pwr_pmu_queue_tail_address_f(u32 v)
738{
739 return (v & 0xffffffff) << 0;
740}
741static inline u32 pwr_pmu_queue_tail_address_v(u32 r)
742{
743 return (r >> 0) & 0xffffffff;
744}
745static inline u32 pwr_pmu_msgq_head_r(void)
746{
747 return 0x0010a4c8;
748}
749static inline u32 pwr_pmu_msgq_head_val_f(u32 v)
750{
751 return (v & 0xffffffff) << 0;
752}
753static inline u32 pwr_pmu_msgq_head_val_v(u32 r)
754{
755 return (r >> 0) & 0xffffffff;
756}
757static inline u32 pwr_pmu_msgq_tail_r(void)
758{
759 return 0x0010a4cc;
760}
761static inline u32 pwr_pmu_msgq_tail_val_f(u32 v)
762{
763 return (v & 0xffffffff) << 0;
764}
765static inline u32 pwr_pmu_msgq_tail_val_v(u32 r)
766{
767 return (r >> 0) & 0xffffffff;
768}
769static inline u32 pwr_pmu_idle_mask_r(u32 i)
770{
771 return 0x0010a504 + i*16;
772}
773static inline u32 pwr_pmu_idle_mask_gr_enabled_f(void)
774{
775 return 0x1;
776}
777static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void)
778{
779 return 0x200000;
780}
781static inline u32 pwr_pmu_idle_count_r(u32 i)
782{
783 return 0x0010a508 + i*16;
784}
785static inline u32 pwr_pmu_idle_count_value_f(u32 v)
786{
787 return (v & 0x7fffffff) << 0;
788}
789static inline u32 pwr_pmu_idle_count_value_v(u32 r)
790{
791 return (r >> 0) & 0x7fffffff;
792}
793static inline u32 pwr_pmu_idle_count_reset_f(u32 v)
794{
795 return (v & 0x1) << 31;
796}
797static inline u32 pwr_pmu_idle_ctrl_r(u32 i)
798{
799 return 0x0010a50c + i*16;
800}
801static inline u32 pwr_pmu_idle_ctrl_value_m(void)
802{
803 return 0x3 << 0;
804}
805static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void)
806{
807 return 0x2;
808}
809static inline u32 pwr_pmu_idle_ctrl_value_always_f(void)
810{
811 return 0x3;
812}
813static inline u32 pwr_pmu_idle_ctrl_filter_m(void)
814{
815 return 0x1 << 2;
816}
817static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void)
818{
819 return 0x0;
820}
821static inline u32 pwr_pmu_idle_mask_supp_r(u32 i)
822{
823 return 0x0010a9f0 + i*8;
824}
825static inline u32 pwr_pmu_idle_mask_1_supp_r(u32 i)
826{
827 return 0x0010a9f4 + i*8;
828}
829static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i)
830{
831 return 0x0010aa30 + i*8;
832}
833static inline u32 pwr_pmu_debug_r(u32 i)
834{
835 return 0x0010a5c0 + i*4;
836}
837static inline u32 pwr_pmu_debug__size_1_v(void)
838{
839 return 0x00000004;
840}
841static inline u32 pwr_pmu_mailbox_r(u32 i)
842{
843 return 0x0010a450 + i*4;
844}
845static inline u32 pwr_pmu_mailbox__size_1_v(void)
846{
847 return 0x0000000c;
848}
849static inline u32 pwr_pmu_bar0_addr_r(void)
850{
851 return 0x0010a7a0;
852}
853static inline u32 pwr_pmu_bar0_data_r(void)
854{
855 return 0x0010a7a4;
856}
857static inline u32 pwr_pmu_bar0_ctl_r(void)
858{
859 return 0x0010a7ac;
860}
861static inline u32 pwr_pmu_bar0_timeout_r(void)
862{
863 return 0x0010a7a8;
864}
865static inline u32 pwr_pmu_bar0_fecs_error_r(void)
866{
867 return 0x0010a988;
868}
869static inline u32 pwr_pmu_bar0_error_status_r(void)
870{
871 return 0x0010a7b0;
872}
873static inline u32 pwr_pmu_pg_idlefilth_r(u32 i)
874{
875 return 0x0010a6c0 + i*4;
876}
877static inline u32 pwr_pmu_pg_ppuidlefilth_r(u32 i)
878{
879 return 0x0010a6e8 + i*4;
880}
881static inline u32 pwr_pmu_pg_idle_cnt_r(u32 i)
882{
883 return 0x0010a710 + i*4;
884}
885static inline u32 pwr_pmu_pg_intren_r(u32 i)
886{
887 return 0x0010a760 + i*4;
888}
889static inline u32 pwr_fbif_transcfg_r(u32 i)
890{
891 return 0x0010ae00 + i*4;
892}
893static inline u32 pwr_fbif_transcfg_target_local_fb_f(void)
894{
895 return 0x0;
896}
897static inline u32 pwr_fbif_transcfg_target_coherent_sysmem_f(void)
898{
899 return 0x1;
900}
901static inline u32 pwr_fbif_transcfg_target_noncoherent_sysmem_f(void)
902{
903 return 0x2;
904}
905static inline u32 pwr_fbif_transcfg_mem_type_s(void)
906{
907 return 1;
908}
909static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v)
910{
911 return (v & 0x1) << 2;
912}
913static inline u32 pwr_fbif_transcfg_mem_type_m(void)
914{
915 return 0x1 << 2;
916}
917static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r)
918{
919 return (r >> 2) & 0x1;
920}
921static inline u32 pwr_fbif_transcfg_mem_type_virtual_f(void)
922{
923 return 0x0;
924}
925static inline u32 pwr_fbif_transcfg_mem_type_physical_f(void)
926{
927 return 0x4;
928}
929#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h
new file mode 100644
index 00000000..7fff981b
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h
@@ -0,0 +1,761 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_ram_gv100_h_
51#define _hw_ram_gv100_h_
52
53static inline u32 ram_in_ramfc_s(void)
54{
55 return 4096;
56}
57static inline u32 ram_in_ramfc_w(void)
58{
59 return 0;
60}
61static inline u32 ram_in_page_dir_base_target_f(u32 v)
62{
63 return (v & 0x3) << 0;
64}
65static inline u32 ram_in_page_dir_base_target_w(void)
66{
67 return 128;
68}
69static inline u32 ram_in_page_dir_base_target_vid_mem_f(void)
70{
71 return 0x0;
72}
73static inline u32 ram_in_page_dir_base_target_sys_mem_coh_f(void)
74{
75 return 0x2;
76}
77static inline u32 ram_in_page_dir_base_target_sys_mem_ncoh_f(void)
78{
79 return 0x3;
80}
81static inline u32 ram_in_page_dir_base_vol_w(void)
82{
83 return 128;
84}
85static inline u32 ram_in_page_dir_base_vol_true_f(void)
86{
87 return 0x4;
88}
89static inline u32 ram_in_page_dir_base_vol_false_f(void)
90{
91 return 0x0;
92}
93static inline u32 ram_in_page_dir_base_fault_replay_tex_f(u32 v)
94{
95 return (v & 0x1) << 4;
96}
97static inline u32 ram_in_page_dir_base_fault_replay_tex_m(void)
98{
99 return 0x1 << 4;
100}
101static inline u32 ram_in_page_dir_base_fault_replay_tex_w(void)
102{
103 return 128;
104}
105static inline u32 ram_in_page_dir_base_fault_replay_tex_true_f(void)
106{
107 return 0x10;
108}
109static inline u32 ram_in_page_dir_base_fault_replay_gcc_f(u32 v)
110{
111 return (v & 0x1) << 5;
112}
113static inline u32 ram_in_page_dir_base_fault_replay_gcc_m(void)
114{
115 return 0x1 << 5;
116}
117static inline u32 ram_in_page_dir_base_fault_replay_gcc_w(void)
118{
119 return 128;
120}
121static inline u32 ram_in_page_dir_base_fault_replay_gcc_true_f(void)
122{
123 return 0x20;
124}
125static inline u32 ram_in_big_page_size_f(u32 v)
126{
127 return (v & 0x1) << 11;
128}
129static inline u32 ram_in_big_page_size_m(void)
130{
131 return 0x1 << 11;
132}
133static inline u32 ram_in_big_page_size_w(void)
134{
135 return 128;
136}
137static inline u32 ram_in_big_page_size_128kb_f(void)
138{
139 return 0x0;
140}
141static inline u32 ram_in_big_page_size_64kb_f(void)
142{
143 return 0x800;
144}
145static inline u32 ram_in_page_dir_base_lo_f(u32 v)
146{
147 return (v & 0xfffff) << 12;
148}
149static inline u32 ram_in_page_dir_base_lo_w(void)
150{
151 return 128;
152}
153static inline u32 ram_in_page_dir_base_hi_f(u32 v)
154{
155 return (v & 0xffffffff) << 0;
156}
157static inline u32 ram_in_page_dir_base_hi_w(void)
158{
159 return 129;
160}
161static inline u32 ram_in_engine_cs_w(void)
162{
163 return 132;
164}
165static inline u32 ram_in_engine_cs_wfi_v(void)
166{
167 return 0x00000000;
168}
169static inline u32 ram_in_engine_cs_wfi_f(void)
170{
171 return 0x0;
172}
173static inline u32 ram_in_engine_cs_fg_v(void)
174{
175 return 0x00000001;
176}
177static inline u32 ram_in_engine_cs_fg_f(void)
178{
179 return 0x8;
180}
181static inline u32 ram_in_engine_wfi_mode_f(u32 v)
182{
183 return (v & 0x1) << 2;
184}
185static inline u32 ram_in_engine_wfi_mode_w(void)
186{
187 return 132;
188}
189static inline u32 ram_in_engine_wfi_mode_physical_v(void)
190{
191 return 0x00000000;
192}
193static inline u32 ram_in_engine_wfi_mode_virtual_v(void)
194{
195 return 0x00000001;
196}
197static inline u32 ram_in_engine_wfi_target_f(u32 v)
198{
199 return (v & 0x3) << 0;
200}
201static inline u32 ram_in_engine_wfi_target_w(void)
202{
203 return 132;
204}
205static inline u32 ram_in_engine_wfi_target_sys_mem_coh_v(void)
206{
207 return 0x00000002;
208}
209static inline u32 ram_in_engine_wfi_target_sys_mem_ncoh_v(void)
210{
211 return 0x00000003;
212}
213static inline u32 ram_in_engine_wfi_target_local_mem_v(void)
214{
215 return 0x00000000;
216}
217static inline u32 ram_in_engine_wfi_ptr_lo_f(u32 v)
218{
219 return (v & 0xfffff) << 12;
220}
221static inline u32 ram_in_engine_wfi_ptr_lo_w(void)
222{
223 return 132;
224}
225static inline u32 ram_in_engine_wfi_ptr_hi_f(u32 v)
226{
227 return (v & 0xff) << 0;
228}
229static inline u32 ram_in_engine_wfi_ptr_hi_w(void)
230{
231 return 133;
232}
233static inline u32 ram_in_engine_wfi_veid_f(u32 v)
234{
235 return (v & 0x3f) << 0;
236}
237static inline u32 ram_in_engine_wfi_veid_w(void)
238{
239 return 134;
240}
241static inline u32 ram_in_eng_method_buffer_addr_lo_f(u32 v)
242{
243 return (v & 0xffffffff) << 0;
244}
245static inline u32 ram_in_eng_method_buffer_addr_lo_w(void)
246{
247 return 136;
248}
249static inline u32 ram_in_eng_method_buffer_addr_hi_f(u32 v)
250{
251 return (v & 0x1ffff) << 0;
252}
253static inline u32 ram_in_eng_method_buffer_addr_hi_w(void)
254{
255 return 137;
256}
257static inline u32 ram_in_sc_page_dir_base_target_f(u32 v, u32 i)
258{
259 return (v & 0x3) << (0 + i*0);
260}
261static inline u32 ram_in_sc_page_dir_base_target__size_1_v(void)
262{
263 return 0x00000040;
264}
265static inline u32 ram_in_sc_page_dir_base_target_vid_mem_v(void)
266{
267 return 0x00000000;
268}
269static inline u32 ram_in_sc_page_dir_base_target_invalid_v(void)
270{
271 return 0x00000001;
272}
273static inline u32 ram_in_sc_page_dir_base_target_sys_mem_coh_v(void)
274{
275 return 0x00000002;
276}
277static inline u32 ram_in_sc_page_dir_base_target_sys_mem_ncoh_v(void)
278{
279 return 0x00000003;
280}
281static inline u32 ram_in_sc_page_dir_base_vol_f(u32 v, u32 i)
282{
283 return (v & 0x1) << (2 + i*0);
284}
285static inline u32 ram_in_sc_page_dir_base_vol__size_1_v(void)
286{
287 return 0x00000040;
288}
289static inline u32 ram_in_sc_page_dir_base_vol_true_v(void)
290{
291 return 0x00000001;
292}
293static inline u32 ram_in_sc_page_dir_base_vol_false_v(void)
294{
295 return 0x00000000;
296}
297static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_f(u32 v, u32 i)
298{
299 return (v & 0x1) << (4 + i*0);
300}
301static inline u32 ram_in_sc_page_dir_base_fault_replay_tex__size_1_v(void)
302{
303 return 0x00000040;
304}
305static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_enabled_v(void)
306{
307 return 0x00000001;
308}
309static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_disabled_v(void)
310{
311 return 0x00000000;
312}
313static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_f(u32 v, u32 i)
314{
315 return (v & 0x1) << (5 + i*0);
316}
317static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc__size_1_v(void)
318{
319 return 0x00000040;
320}
321static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_enabled_v(void)
322{
323 return 0x00000001;
324}
325static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_disabled_v(void)
326{
327 return 0x00000000;
328}
329static inline u32 ram_in_sc_use_ver2_pt_format_f(u32 v, u32 i)
330{
331 return (v & 0x1) << (10 + i*0);
332}
333static inline u32 ram_in_sc_use_ver2_pt_format__size_1_v(void)
334{
335 return 0x00000040;
336}
337static inline u32 ram_in_sc_use_ver2_pt_format_false_v(void)
338{
339 return 0x00000000;
340}
341static inline u32 ram_in_sc_use_ver2_pt_format_true_v(void)
342{
343 return 0x00000001;
344}
345static inline u32 ram_in_sc_big_page_size_f(u32 v, u32 i)
346{
347 return (v & 0x1) << (11 + i*0);
348}
349static inline u32 ram_in_sc_big_page_size__size_1_v(void)
350{
351 return 0x00000040;
352}
353static inline u32 ram_in_sc_big_page_size_64kb_v(void)
354{
355 return 0x00000001;
356}
357static inline u32 ram_in_sc_page_dir_base_lo_f(u32 v, u32 i)
358{
359 return (v & 0xfffff) << (12 + i*0);
360}
361static inline u32 ram_in_sc_page_dir_base_lo__size_1_v(void)
362{
363 return 0x00000040;
364}
365static inline u32 ram_in_sc_page_dir_base_hi_f(u32 v, u32 i)
366{
367 return (v & 0xffffffff) << (0 + i*0);
368}
369static inline u32 ram_in_sc_page_dir_base_hi__size_1_v(void)
370{
371 return 0x00000040;
372}
373static inline u32 ram_in_sc_page_dir_base_target_0_f(u32 v)
374{
375 return (v & 0x3) << 0;
376}
377static inline u32 ram_in_sc_page_dir_base_target_0_w(void)
378{
379 return 168;
380}
381static inline u32 ram_in_sc_page_dir_base_vol_0_f(u32 v)
382{
383 return (v & 0x1) << 2;
384}
385static inline u32 ram_in_sc_page_dir_base_vol_0_w(void)
386{
387 return 168;
388}
389static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_0_f(u32 v)
390{
391 return (v & 0x1) << 4;
392}
393static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_0_w(void)
394{
395 return 168;
396}
397static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_0_f(u32 v)
398{
399 return (v & 0x1) << 5;
400}
401static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_0_w(void)
402{
403 return 168;
404}
405static inline u32 ram_in_sc_use_ver2_pt_format_0_f(u32 v)
406{
407 return (v & 0x1) << 10;
408}
409static inline u32 ram_in_sc_use_ver2_pt_format_0_w(void)
410{
411 return 168;
412}
413static inline u32 ram_in_sc_big_page_size_0_f(u32 v)
414{
415 return (v & 0x1) << 11;
416}
417static inline u32 ram_in_sc_big_page_size_0_w(void)
418{
419 return 168;
420}
421static inline u32 ram_in_sc_page_dir_base_lo_0_f(u32 v)
422{
423 return (v & 0xfffff) << 12;
424}
425static inline u32 ram_in_sc_page_dir_base_lo_0_w(void)
426{
427 return 168;
428}
429static inline u32 ram_in_sc_page_dir_base_hi_0_f(u32 v)
430{
431 return (v & 0xffffffff) << 0;
432}
433static inline u32 ram_in_sc_page_dir_base_hi_0_w(void)
434{
435 return 169;
436}
437static inline u32 ram_in_base_shift_v(void)
438{
439 return 0x0000000c;
440}
441static inline u32 ram_in_alloc_size_v(void)
442{
443 return 0x00001000;
444}
445static inline u32 ram_fc_size_val_v(void)
446{
447 return 0x00000200;
448}
449static inline u32 ram_fc_gp_put_w(void)
450{
451 return 0;
452}
453static inline u32 ram_fc_userd_w(void)
454{
455 return 2;
456}
457static inline u32 ram_fc_userd_hi_w(void)
458{
459 return 3;
460}
461static inline u32 ram_fc_signature_w(void)
462{
463 return 4;
464}
465static inline u32 ram_fc_gp_get_w(void)
466{
467 return 5;
468}
469static inline u32 ram_fc_pb_get_w(void)
470{
471 return 6;
472}
473static inline u32 ram_fc_pb_get_hi_w(void)
474{
475 return 7;
476}
477static inline u32 ram_fc_pb_top_level_get_w(void)
478{
479 return 8;
480}
481static inline u32 ram_fc_pb_top_level_get_hi_w(void)
482{
483 return 9;
484}
485static inline u32 ram_fc_acquire_w(void)
486{
487 return 12;
488}
489static inline u32 ram_fc_sem_addr_hi_w(void)
490{
491 return 14;
492}
493static inline u32 ram_fc_sem_addr_lo_w(void)
494{
495 return 15;
496}
497static inline u32 ram_fc_sem_payload_lo_w(void)
498{
499 return 16;
500}
501static inline u32 ram_fc_sem_payload_hi_w(void)
502{
503 return 39;
504}
505static inline u32 ram_fc_sem_execute_w(void)
506{
507 return 17;
508}
509static inline u32 ram_fc_gp_base_w(void)
510{
511 return 18;
512}
513static inline u32 ram_fc_gp_base_hi_w(void)
514{
515 return 19;
516}
517static inline u32 ram_fc_gp_fetch_w(void)
518{
519 return 20;
520}
521static inline u32 ram_fc_pb_fetch_w(void)
522{
523 return 21;
524}
525static inline u32 ram_fc_pb_fetch_hi_w(void)
526{
527 return 22;
528}
529static inline u32 ram_fc_pb_put_w(void)
530{
531 return 23;
532}
533static inline u32 ram_fc_pb_put_hi_w(void)
534{
535 return 24;
536}
537static inline u32 ram_fc_pb_header_w(void)
538{
539 return 33;
540}
541static inline u32 ram_fc_pb_count_w(void)
542{
543 return 34;
544}
545static inline u32 ram_fc_subdevice_w(void)
546{
547 return 37;
548}
549static inline u32 ram_fc_target_w(void)
550{
551 return 43;
552}
553static inline u32 ram_fc_hce_ctrl_w(void)
554{
555 return 57;
556}
557static inline u32 ram_fc_chid_w(void)
558{
559 return 58;
560}
561static inline u32 ram_fc_chid_id_f(u32 v)
562{
563 return (v & 0xfff) << 0;
564}
565static inline u32 ram_fc_chid_id_w(void)
566{
567 return 0;
568}
569static inline u32 ram_fc_config_w(void)
570{
571 return 61;
572}
573static inline u32 ram_fc_runlist_timeslice_w(void)
574{
575 return 62;
576}
577static inline u32 ram_fc_set_channel_info_w(void)
578{
579 return 63;
580}
581static inline u32 ram_userd_base_shift_v(void)
582{
583 return 0x00000009;
584}
585static inline u32 ram_userd_chan_size_v(void)
586{
587 return 0x00000200;
588}
589static inline u32 ram_userd_put_w(void)
590{
591 return 16;
592}
593static inline u32 ram_userd_get_w(void)
594{
595 return 17;
596}
597static inline u32 ram_userd_ref_w(void)
598{
599 return 18;
600}
601static inline u32 ram_userd_put_hi_w(void)
602{
603 return 19;
604}
605static inline u32 ram_userd_ref_threshold_w(void)
606{
607 return 20;
608}
609static inline u32 ram_userd_top_level_get_w(void)
610{
611 return 22;
612}
613static inline u32 ram_userd_top_level_get_hi_w(void)
614{
615 return 23;
616}
617static inline u32 ram_userd_get_hi_w(void)
618{
619 return 24;
620}
621static inline u32 ram_userd_gp_get_w(void)
622{
623 return 34;
624}
625static inline u32 ram_userd_gp_put_w(void)
626{
627 return 35;
628}
629static inline u32 ram_userd_gp_top_level_get_w(void)
630{
631 return 22;
632}
633static inline u32 ram_userd_gp_top_level_get_hi_w(void)
634{
635 return 23;
636}
637static inline u32 ram_rl_entry_size_v(void)
638{
639 return 0x00000010;
640}
641static inline u32 ram_rl_entry_type_f(u32 v)
642{
643 return (v & 0x1) << 0;
644}
645static inline u32 ram_rl_entry_type_channel_v(void)
646{
647 return 0x00000000;
648}
649static inline u32 ram_rl_entry_type_tsg_v(void)
650{
651 return 0x00000001;
652}
653static inline u32 ram_rl_entry_id_f(u32 v)
654{
655 return (v & 0xfff) << 0;
656}
657static inline u32 ram_rl_entry_chan_runqueue_selector_f(u32 v)
658{
659 return (v & 0x1) << 1;
660}
661static inline u32 ram_rl_entry_chan_inst_target_f(u32 v)
662{
663 return (v & 0x3) << 4;
664}
665static inline u32 ram_rl_entry_chan_inst_target_sys_mem_ncoh_v(void)
666{
667 return 0x00000003;
668}
669static inline u32 ram_rl_entry_chan_userd_target_f(u32 v)
670{
671 return (v & 0x3) << 6;
672}
673static inline u32 ram_rl_entry_chan_userd_target_vid_mem_v(void)
674{
675 return 0x00000000;
676}
677static inline u32 ram_rl_entry_chan_userd_target_vid_mem_nvlink_coh_v(void)
678{
679 return 0x00000001;
680}
681static inline u32 ram_rl_entry_chan_userd_target_sys_mem_coh_v(void)
682{
683 return 0x00000002;
684}
685static inline u32 ram_rl_entry_chan_userd_target_sys_mem_ncoh_v(void)
686{
687 return 0x00000003;
688}
689static inline u32 ram_rl_entry_chan_userd_ptr_lo_f(u32 v)
690{
691 return (v & 0xffffff) << 8;
692}
693static inline u32 ram_rl_entry_chan_userd_ptr_hi_f(u32 v)
694{
695 return (v & 0xffffffff) << 0;
696}
697static inline u32 ram_rl_entry_chid_f(u32 v)
698{
699 return (v & 0xfff) << 0;
700}
701static inline u32 ram_rl_entry_chan_inst_ptr_lo_f(u32 v)
702{
703 return (v & 0xfffff) << 12;
704}
705static inline u32 ram_rl_entry_chan_inst_ptr_hi_f(u32 v)
706{
707 return (v & 0xffffffff) << 0;
708}
709static inline u32 ram_rl_entry_tsg_timeslice_scale_f(u32 v)
710{
711 return (v & 0xf) << 16;
712}
713static inline u32 ram_rl_entry_tsg_timeslice_scale_3_v(void)
714{
715 return 0x00000003;
716}
717static inline u32 ram_rl_entry_tsg_timeslice_timeout_f(u32 v)
718{
719 return (v & 0xff) << 24;
720}
721static inline u32 ram_rl_entry_tsg_timeslice_timeout_128_v(void)
722{
723 return 0x00000080;
724}
725static inline u32 ram_rl_entry_tsg_timeslice_timeout_disable_v(void)
726{
727 return 0x00000000;
728}
729static inline u32 ram_rl_entry_tsg_length_f(u32 v)
730{
731 return (v & 0xff) << 0;
732}
733static inline u32 ram_rl_entry_tsg_length_init_v(void)
734{
735 return 0x00000000;
736}
737static inline u32 ram_rl_entry_tsg_length_min_v(void)
738{
739 return 0x00000001;
740}
741static inline u32 ram_rl_entry_tsg_length_max_v(void)
742{
743 return 0x00000080;
744}
745static inline u32 ram_rl_entry_tsg_tsgid_f(u32 v)
746{
747 return (v & 0xfff) << 0;
748}
749static inline u32 ram_rl_entry_chan_userd_ptr_align_shift_v(void)
750{
751 return 0x00000008;
752}
753static inline u32 ram_rl_entry_chan_userd_align_shift_v(void)
754{
755 return 0x00000008;
756}
757static inline u32 ram_rl_entry_chan_inst_ptr_align_shift_v(void)
758{
759 return 0x0000000c;
760}
761#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_therm_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_therm_gv100.h
new file mode 100644
index 00000000..d98002c0
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_therm_gv100.h
@@ -0,0 +1,293 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_therm_gv100_h_
51#define _hw_therm_gv100_h_
52
53static inline u32 therm_weight_1_r(void)
54{
55 return 0x00020024;
56}
57static inline u32 therm_config1_r(void)
58{
59 return 0x00020050;
60}
61static inline u32 therm_config2_r(void)
62{
63 return 0x00020130;
64}
65static inline u32 therm_config2_slowdown_factor_extended_f(u32 v)
66{
67 return (v & 0x1) << 24;
68}
69static inline u32 therm_config2_grad_enable_f(u32 v)
70{
71 return (v & 0x1) << 31;
72}
73static inline u32 therm_gate_ctrl_r(u32 i)
74{
75 return 0x00020200 + i*4;
76}
77static inline u32 therm_gate_ctrl_eng_clk_m(void)
78{
79 return 0x3 << 0;
80}
81static inline u32 therm_gate_ctrl_eng_clk_run_f(void)
82{
83 return 0x0;
84}
85static inline u32 therm_gate_ctrl_eng_clk_auto_f(void)
86{
87 return 0x1;
88}
89static inline u32 therm_gate_ctrl_eng_clk_stop_f(void)
90{
91 return 0x2;
92}
93static inline u32 therm_gate_ctrl_blk_clk_m(void)
94{
95 return 0x3 << 2;
96}
97static inline u32 therm_gate_ctrl_blk_clk_run_f(void)
98{
99 return 0x0;
100}
101static inline u32 therm_gate_ctrl_blk_clk_auto_f(void)
102{
103 return 0x4;
104}
105static inline u32 therm_gate_ctrl_idle_holdoff_m(void)
106{
107 return 0x1 << 4;
108}
109static inline u32 therm_gate_ctrl_idle_holdoff_off_f(void)
110{
111 return 0x0;
112}
113static inline u32 therm_gate_ctrl_idle_holdoff_on_f(void)
114{
115 return 0x10;
116}
117static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v)
118{
119 return (v & 0x1f) << 8;
120}
121static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void)
122{
123 return 0x1f << 8;
124}
125static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v)
126{
127 return (v & 0x7) << 13;
128}
129static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void)
130{
131 return 0x7 << 13;
132}
133static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v)
134{
135 return (v & 0xf) << 16;
136}
137static inline u32 therm_gate_ctrl_eng_delay_before_m(void)
138{
139 return 0xf << 16;
140}
141static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v)
142{
143 return (v & 0xf) << 20;
144}
145static inline u32 therm_gate_ctrl_eng_delay_after_m(void)
146{
147 return 0xf << 20;
148}
149static inline u32 therm_fecs_idle_filter_r(void)
150{
151 return 0x00020288;
152}
153static inline u32 therm_fecs_idle_filter_value_m(void)
154{
155 return 0xffffffff << 0;
156}
157static inline u32 therm_hubmmu_idle_filter_r(void)
158{
159 return 0x0002028c;
160}
161static inline u32 therm_hubmmu_idle_filter_value_m(void)
162{
163 return 0xffffffff << 0;
164}
165static inline u32 therm_clk_slowdown_r(u32 i)
166{
167 return 0x00020160 + i*4;
168}
169static inline u32 therm_clk_slowdown_idle_factor_f(u32 v)
170{
171 return (v & 0x3f) << 16;
172}
173static inline u32 therm_clk_slowdown_idle_factor_m(void)
174{
175 return 0x3f << 16;
176}
177static inline u32 therm_clk_slowdown_idle_factor_v(u32 r)
178{
179 return (r >> 16) & 0x3f;
180}
181static inline u32 therm_clk_slowdown_idle_factor_disabled_f(void)
182{
183 return 0x0;
184}
185static inline u32 therm_grad_stepping_table_r(u32 i)
186{
187 return 0x000202c8 + i*4;
188}
189static inline u32 therm_grad_stepping_table_slowdown_factor0_f(u32 v)
190{
191 return (v & 0x3f) << 0;
192}
193static inline u32 therm_grad_stepping_table_slowdown_factor0_m(void)
194{
195 return 0x3f << 0;
196}
197static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f(void)
198{
199 return 0x1;
200}
201static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f(void)
202{
203 return 0x2;
204}
205static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f(void)
206{
207 return 0x6;
208}
209static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f(void)
210{
211 return 0xe;
212}
213static inline u32 therm_grad_stepping_table_slowdown_factor1_f(u32 v)
214{
215 return (v & 0x3f) << 6;
216}
217static inline u32 therm_grad_stepping_table_slowdown_factor1_m(void)
218{
219 return 0x3f << 6;
220}
221static inline u32 therm_grad_stepping_table_slowdown_factor2_f(u32 v)
222{
223 return (v & 0x3f) << 12;
224}
225static inline u32 therm_grad_stepping_table_slowdown_factor2_m(void)
226{
227 return 0x3f << 12;
228}
229static inline u32 therm_grad_stepping_table_slowdown_factor3_f(u32 v)
230{
231 return (v & 0x3f) << 18;
232}
233static inline u32 therm_grad_stepping_table_slowdown_factor3_m(void)
234{
235 return 0x3f << 18;
236}
237static inline u32 therm_grad_stepping_table_slowdown_factor4_f(u32 v)
238{
239 return (v & 0x3f) << 24;
240}
241static inline u32 therm_grad_stepping_table_slowdown_factor4_m(void)
242{
243 return 0x3f << 24;
244}
245static inline u32 therm_grad_stepping0_r(void)
246{
247 return 0x000202c0;
248}
249static inline u32 therm_grad_stepping0_feature_s(void)
250{
251 return 1;
252}
253static inline u32 therm_grad_stepping0_feature_f(u32 v)
254{
255 return (v & 0x1) << 0;
256}
257static inline u32 therm_grad_stepping0_feature_m(void)
258{
259 return 0x1 << 0;
260}
261static inline u32 therm_grad_stepping0_feature_v(u32 r)
262{
263 return (r >> 0) & 0x1;
264}
265static inline u32 therm_grad_stepping0_feature_enable_f(void)
266{
267 return 0x1;
268}
269static inline u32 therm_grad_stepping1_r(void)
270{
271 return 0x000202c4;
272}
273static inline u32 therm_grad_stepping1_pdiv_duration_f(u32 v)
274{
275 return (v & 0x1ffff) << 0;
276}
277static inline u32 therm_clk_timing_r(u32 i)
278{
279 return 0x000203c0 + i*4;
280}
281static inline u32 therm_clk_timing_grad_slowdown_f(u32 v)
282{
283 return (v & 0x1) << 16;
284}
285static inline u32 therm_clk_timing_grad_slowdown_m(void)
286{
287 return 0x1 << 16;
288}
289static inline u32 therm_clk_timing_grad_slowdown_enabled_f(void)
290{
291 return 0x10000;
292}
293#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_timer_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_timer_gv100.h
new file mode 100644
index 00000000..c71e9a7d
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_timer_gv100.h
@@ -0,0 +1,109 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_timer_gv100_h_
51#define _hw_timer_gv100_h_
52
53static inline u32 timer_pri_timeout_r(void)
54{
55 return 0x00009080;
56}
57static inline u32 timer_pri_timeout_period_f(u32 v)
58{
59 return (v & 0xffffff) << 0;
60}
61static inline u32 timer_pri_timeout_period_m(void)
62{
63 return 0xffffff << 0;
64}
65static inline u32 timer_pri_timeout_period_v(u32 r)
66{
67 return (r >> 0) & 0xffffff;
68}
69static inline u32 timer_pri_timeout_en_f(u32 v)
70{
71 return (v & 0x1) << 31;
72}
73static inline u32 timer_pri_timeout_en_m(void)
74{
75 return 0x1 << 31;
76}
77static inline u32 timer_pri_timeout_en_v(u32 r)
78{
79 return (r >> 31) & 0x1;
80}
81static inline u32 timer_pri_timeout_en_en_enabled_f(void)
82{
83 return 0x80000000;
84}
85static inline u32 timer_pri_timeout_en_en_disabled_f(void)
86{
87 return 0x0;
88}
89static inline u32 timer_pri_timeout_save_0_r(void)
90{
91 return 0x00009084;
92}
93static inline u32 timer_pri_timeout_save_1_r(void)
94{
95 return 0x00009088;
96}
97static inline u32 timer_pri_timeout_fecs_errcode_r(void)
98{
99 return 0x0000908c;
100}
101static inline u32 timer_time_0_r(void)
102{
103 return 0x00009400;
104}
105static inline u32 timer_time_1_r(void)
106{
107 return 0x00009410;
108}
109#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h
new file mode 100644
index 00000000..d993bddc
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h
@@ -0,0 +1,229 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_top_gv100_h_
51#define _hw_top_gv100_h_
52
53static inline u32 top_num_gpcs_r(void)
54{
55 return 0x00022430;
56}
57static inline u32 top_num_gpcs_value_v(u32 r)
58{
59 return (r >> 0) & 0x1f;
60}
61static inline u32 top_tpc_per_gpc_r(void)
62{
63 return 0x00022434;
64}
65static inline u32 top_tpc_per_gpc_value_v(u32 r)
66{
67 return (r >> 0) & 0x1f;
68}
69static inline u32 top_num_fbps_r(void)
70{
71 return 0x00022438;
72}
73static inline u32 top_num_fbps_value_v(u32 r)
74{
75 return (r >> 0) & 0x1f;
76}
77static inline u32 top_ltc_per_fbp_r(void)
78{
79 return 0x00022450;
80}
81static inline u32 top_ltc_per_fbp_value_v(u32 r)
82{
83 return (r >> 0) & 0x1f;
84}
85static inline u32 top_slices_per_ltc_r(void)
86{
87 return 0x0002245c;
88}
89static inline u32 top_slices_per_ltc_value_v(u32 r)
90{
91 return (r >> 0) & 0x1f;
92}
93static inline u32 top_num_ltcs_r(void)
94{
95 return 0x00022454;
96}
97static inline u32 top_num_ces_r(void)
98{
99 return 0x00022444;
100}
101static inline u32 top_num_ces_value_v(u32 r)
102{
103 return (r >> 0) & 0x1f;
104}
105static inline u32 top_device_info_r(u32 i)
106{
107 return 0x00022700 + i*4;
108}
109static inline u32 top_device_info__size_1_v(void)
110{
111 return 0x00000040;
112}
113static inline u32 top_device_info_chain_v(u32 r)
114{
115 return (r >> 31) & 0x1;
116}
117static inline u32 top_device_info_chain_enable_v(void)
118{
119 return 0x00000001;
120}
121static inline u32 top_device_info_engine_enum_v(u32 r)
122{
123 return (r >> 26) & 0xf;
124}
125static inline u32 top_device_info_runlist_enum_v(u32 r)
126{
127 return (r >> 21) & 0xf;
128}
129static inline u32 top_device_info_intr_enum_v(u32 r)
130{
131 return (r >> 15) & 0x1f;
132}
133static inline u32 top_device_info_reset_enum_v(u32 r)
134{
135 return (r >> 9) & 0x1f;
136}
137static inline u32 top_device_info_type_enum_v(u32 r)
138{
139 return (r >> 2) & 0x1fffffff;
140}
141static inline u32 top_device_info_type_enum_graphics_v(void)
142{
143 return 0x00000000;
144}
145static inline u32 top_device_info_type_enum_graphics_f(void)
146{
147 return 0x0;
148}
149static inline u32 top_device_info_type_enum_copy2_v(void)
150{
151 return 0x00000003;
152}
153static inline u32 top_device_info_type_enum_copy2_f(void)
154{
155 return 0xc;
156}
157static inline u32 top_device_info_type_enum_lce_v(void)
158{
159 return 0x00000013;
160}
161static inline u32 top_device_info_type_enum_lce_f(void)
162{
163 return 0x4c;
164}
165static inline u32 top_device_info_engine_v(u32 r)
166{
167 return (r >> 5) & 0x1;
168}
169static inline u32 top_device_info_runlist_v(u32 r)
170{
171 return (r >> 4) & 0x1;
172}
173static inline u32 top_device_info_intr_v(u32 r)
174{
175 return (r >> 3) & 0x1;
176}
177static inline u32 top_device_info_reset_v(u32 r)
178{
179 return (r >> 2) & 0x1;
180}
181static inline u32 top_device_info_entry_v(u32 r)
182{
183 return (r >> 0) & 0x3;
184}
185static inline u32 top_device_info_entry_not_valid_v(void)
186{
187 return 0x00000000;
188}
189static inline u32 top_device_info_entry_enum_v(void)
190{
191 return 0x00000002;
192}
193static inline u32 top_device_info_entry_data_v(void)
194{
195 return 0x00000001;
196}
197static inline u32 top_device_info_data_type_v(u32 r)
198{
199 return (r >> 30) & 0x1;
200}
201static inline u32 top_device_info_data_type_enum2_v(void)
202{
203 return 0x00000000;
204}
205static inline u32 top_device_info_data_inst_id_v(u32 r)
206{
207 return (r >> 26) & 0xf;
208}
209static inline u32 top_device_info_data_pri_base_v(u32 r)
210{
211 return (r >> 12) & 0xfff;
212}
213static inline u32 top_device_info_data_pri_base_align_v(void)
214{
215 return 0x0000000c;
216}
217static inline u32 top_device_info_data_fault_id_enum_v(u32 r)
218{
219 return (r >> 3) & 0x7f;
220}
221static inline u32 top_device_info_data_fault_id_v(u32 r)
222{
223 return (r >> 2) & 0x1;
224}
225static inline u32 top_device_info_data_fault_id_valid_v(void)
226{
227 return 0x00000001;
228}
229#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_usermode_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_usermode_gv100.h
new file mode 100644
index 00000000..86045e51
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_usermode_gv100.h
@@ -0,0 +1,89 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_usermode_gv100_h_
51#define _hw_usermode_gv100_h_
52
53static inline u32 usermode_cfg0_r(void)
54{
55 return 0x00810000;
56}
57static inline u32 usermode_cfg0_class_id_f(u32 v)
58{
59 return (v & 0xffff) << 0;
60}
61static inline u32 usermode_cfg0_class_id_value_v(void)
62{
63 return 0x0000c361;
64}
65static inline u32 usermode_time_0_r(void)
66{
67 return 0x00810080;
68}
69static inline u32 usermode_time_0_nsec_f(u32 v)
70{
71 return (v & 0x7ffffff) << 5;
72}
73static inline u32 usermode_time_1_r(void)
74{
75 return 0x00810084;
76}
77static inline u32 usermode_time_1_nsec_f(u32 v)
78{
79 return (v & 0x1fffffff) << 0;
80}
81static inline u32 usermode_notify_channel_pending_r(void)
82{
83 return 0x00810090;
84}
85static inline u32 usermode_notify_channel_pending_id_f(u32 v)
86{
87 return (v & 0xffffffff) << 0;
88}
89#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xp_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xp_gv100.h
new file mode 100644
index 00000000..4f15b39d
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xp_gv100.h
@@ -0,0 +1,137 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_xp_gv100_h_
51#define _hw_xp_gv100_h_
52
53static inline u32 xp_dl_mgr_r(u32 i)
54{
55 return 0x0008b8c0 + i*4;
56}
57static inline u32 xp_dl_mgr_safe_timing_f(u32 v)
58{
59 return (v & 0x1) << 2;
60}
61static inline u32 xp_pl_link_config_r(u32 i)
62{
63 return 0x0008c040 + i*4;
64}
65static inline u32 xp_pl_link_config_ltssm_status_f(u32 v)
66{
67 return (v & 0x1) << 4;
68}
69static inline u32 xp_pl_link_config_ltssm_status_idle_v(void)
70{
71 return 0x00000000;
72}
73static inline u32 xp_pl_link_config_ltssm_directive_f(u32 v)
74{
75 return (v & 0xf) << 0;
76}
77static inline u32 xp_pl_link_config_ltssm_directive_m(void)
78{
79 return 0xf << 0;
80}
81static inline u32 xp_pl_link_config_ltssm_directive_normal_operations_v(void)
82{
83 return 0x00000000;
84}
85static inline u32 xp_pl_link_config_ltssm_directive_change_speed_v(void)
86{
87 return 0x00000001;
88}
89static inline u32 xp_pl_link_config_max_link_rate_f(u32 v)
90{
91 return (v & 0x3) << 18;
92}
93static inline u32 xp_pl_link_config_max_link_rate_m(void)
94{
95 return 0x3 << 18;
96}
97static inline u32 xp_pl_link_config_max_link_rate_2500_mtps_v(void)
98{
99 return 0x00000002;
100}
101static inline u32 xp_pl_link_config_max_link_rate_5000_mtps_v(void)
102{
103 return 0x00000001;
104}
105static inline u32 xp_pl_link_config_max_link_rate_8000_mtps_v(void)
106{
107 return 0x00000000;
108}
109static inline u32 xp_pl_link_config_target_tx_width_f(u32 v)
110{
111 return (v & 0x7) << 20;
112}
113static inline u32 xp_pl_link_config_target_tx_width_m(void)
114{
115 return 0x7 << 20;
116}
117static inline u32 xp_pl_link_config_target_tx_width_x1_v(void)
118{
119 return 0x00000007;
120}
121static inline u32 xp_pl_link_config_target_tx_width_x2_v(void)
122{
123 return 0x00000006;
124}
125static inline u32 xp_pl_link_config_target_tx_width_x4_v(void)
126{
127 return 0x00000005;
128}
129static inline u32 xp_pl_link_config_target_tx_width_x8_v(void)
130{
131 return 0x00000004;
132}
133static inline u32 xp_pl_link_config_target_tx_width_x16_v(void)
134{
135 return 0x00000000;
136}
137#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xve_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xve_gv100.h
new file mode 100644
index 00000000..f082fdc7
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xve_gv100.h
@@ -0,0 +1,201 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_xve_gv100_h_
51#define _hw_xve_gv100_h_
52
53static inline u32 xve_rom_ctrl_r(void)
54{
55 return 0x00000050;
56}
57static inline u32 xve_rom_ctrl_rom_shadow_f(u32 v)
58{
59 return (v & 0x1) << 0;
60}
61static inline u32 xve_rom_ctrl_rom_shadow_disabled_f(void)
62{
63 return 0x0;
64}
65static inline u32 xve_rom_ctrl_rom_shadow_enabled_f(void)
66{
67 return 0x1;
68}
69static inline u32 xve_link_control_status_r(void)
70{
71 return 0x00000088;
72}
73static inline u32 xve_link_control_status_link_speed_m(void)
74{
75 return 0xf << 16;
76}
77static inline u32 xve_link_control_status_link_speed_v(u32 r)
78{
79 return (r >> 16) & 0xf;
80}
81static inline u32 xve_link_control_status_link_speed_link_speed_2p5_v(void)
82{
83 return 0x00000001;
84}
85static inline u32 xve_link_control_status_link_speed_link_speed_5p0_v(void)
86{
87 return 0x00000002;
88}
89static inline u32 xve_link_control_status_link_speed_link_speed_8p0_v(void)
90{
91 return 0x00000003;
92}
93static inline u32 xve_link_control_status_link_width_m(void)
94{
95 return 0x3f << 20;
96}
97static inline u32 xve_link_control_status_link_width_v(u32 r)
98{
99 return (r >> 20) & 0x3f;
100}
101static inline u32 xve_link_control_status_link_width_x1_v(void)
102{
103 return 0x00000001;
104}
105static inline u32 xve_link_control_status_link_width_x2_v(void)
106{
107 return 0x00000002;
108}
109static inline u32 xve_link_control_status_link_width_x4_v(void)
110{
111 return 0x00000004;
112}
113static inline u32 xve_link_control_status_link_width_x8_v(void)
114{
115 return 0x00000008;
116}
117static inline u32 xve_link_control_status_link_width_x16_v(void)
118{
119 return 0x00000010;
120}
121static inline u32 xve_priv_xv_r(void)
122{
123 return 0x00000150;
124}
125static inline u32 xve_priv_xv_cya_l0s_enable_f(u32 v)
126{
127 return (v & 0x1) << 7;
128}
129static inline u32 xve_priv_xv_cya_l0s_enable_m(void)
130{
131 return 0x1 << 7;
132}
133static inline u32 xve_priv_xv_cya_l0s_enable_v(u32 r)
134{
135 return (r >> 7) & 0x1;
136}
137static inline u32 xve_priv_xv_cya_l1_enable_f(u32 v)
138{
139 return (v & 0x1) << 8;
140}
141static inline u32 xve_priv_xv_cya_l1_enable_m(void)
142{
143 return 0x1 << 8;
144}
145static inline u32 xve_priv_xv_cya_l1_enable_v(u32 r)
146{
147 return (r >> 8) & 0x1;
148}
149static inline u32 xve_cya_2_r(void)
150{
151 return 0x00000704;
152}
153static inline u32 xve_reset_r(void)
154{
155 return 0x00000718;
156}
157static inline u32 xve_reset_reset_m(void)
158{
159 return 0x1 << 0;
160}
161static inline u32 xve_reset_gpu_on_sw_reset_m(void)
162{
163 return 0x1 << 1;
164}
165static inline u32 xve_reset_counter_en_m(void)
166{
167 return 0x1 << 2;
168}
169static inline u32 xve_reset_counter_val_f(u32 v)
170{
171 return (v & 0x7ff) << 4;
172}
173static inline u32 xve_reset_counter_val_m(void)
174{
175 return 0x7ff << 4;
176}
177static inline u32 xve_reset_counter_val_v(u32 r)
178{
179 return (r >> 4) & 0x7ff;
180}
181static inline u32 xve_reset_clock_on_sw_reset_m(void)
182{
183 return 0x1 << 15;
184}
185static inline u32 xve_reset_clock_counter_en_m(void)
186{
187 return 0x1 << 16;
188}
189static inline u32 xve_reset_clock_counter_val_f(u32 v)
190{
191 return (v & 0x7ff) << 17;
192}
193static inline u32 xve_reset_clock_counter_val_m(void)
194{
195 return 0x7ff << 17;
196}
197static inline u32 xve_reset_clock_counter_val_v(u32 r)
198{
199 return (r >> 17) & 0x7ff;
200}
201#endif
diff --git a/drivers/gpu/nvgpu/nvgpu_gpuid_t19x.h b/drivers/gpu/nvgpu/nvgpu_gpuid_t19x.h
index 63901445..71841484 100644
--- a/drivers/gpu/nvgpu/nvgpu_gpuid_t19x.h
+++ b/drivers/gpu/nvgpu/nvgpu_gpuid_t19x.h
@@ -17,16 +17,25 @@
17 17
18#define NVGPU_GPUID_GV11B \ 18#define NVGPU_GPUID_GV11B \
19 GK20A_GPUID(NVGPU_GPU_ARCH_GV110, NVGPU_GPU_IMPL_GV11B) 19 GK20A_GPUID(NVGPU_GPU_ARCH_GV110, NVGPU_GPU_IMPL_GV11B)
20#define NVGPU_GPUID_GV100 \
21 GK20A_GPUID(NVGPU_GPU_ARCH_GV100, NVGPU_GPU_IMPL_GV100)
22
20 23
21#define NVGPU_COMPAT_TEGRA_GV11B "nvidia,gv11b" 24#define NVGPU_COMPAT_TEGRA_GV11B "nvidia,gv11b"
22#define NVGPU_COMPAT_GENERIC_GV11B "nvidia,generic-gv11b" 25#define NVGPU_COMPAT_GENERIC_GV11B "nvidia,generic-gv11b"
23 26
27
24#define TEGRA_19x_GPUID NVGPU_GPUID_GV11B 28#define TEGRA_19x_GPUID NVGPU_GPUID_GV11B
25#define TEGRA_19x_GPUID_HAL gv11b_init_hal 29#define TEGRA_19x_GPUID_HAL gv11b_init_hal
26#define TEGRA_19x_GPU_COMPAT_TEGRA NVGPU_COMPAT_TEGRA_GV11B 30#define TEGRA_19x_GPU_COMPAT_TEGRA NVGPU_COMPAT_TEGRA_GV11B
27#define TEGRA_19x_GPU_COMPAT_GENERIC NVGPU_COMPAT_GENERIC_GV11B 31#define TEGRA_19x_GPU_COMPAT_GENERIC NVGPU_COMPAT_GENERIC_GV11B
32
33#define BIGGPU_19x_GPUID NVGPU_GPUID_GV100
34#define BIGGPU_19x_GPUID_HAL gv100_init_hal
35
28struct gpu_ops; 36struct gpu_ops;
29extern int gv11b_init_hal(struct gk20a *); 37extern int gv11b_init_hal(struct gk20a *);
38extern int gv100_init_hal(struct gk20a *);
30extern struct gk20a_platform t19x_gpu_tegra_platform; 39extern struct gk20a_platform t19x_gpu_tegra_platform;
31 40
32#endif 41#endif
diff --git a/include/uapi/linux/nvgpu-t19x.h b/include/uapi/linux/nvgpu-t19x.h
index bc37bc7c..f56bc9d7 100644
--- a/include/uapi/linux/nvgpu-t19x.h
+++ b/include/uapi/linux/nvgpu-t19x.h
@@ -25,7 +25,9 @@
25#define _UAPI__LINUX_NVGPU_T19X_IOCTL_H_ 25#define _UAPI__LINUX_NVGPU_T19X_IOCTL_H_
26 26
27#define NVGPU_GPU_ARCH_GV110 0x00000150 27#define NVGPU_GPU_ARCH_GV110 0x00000150
28#define NVGPU_GPU_ARCH_GV100 0x00000140
28#define NVGPU_GPU_IMPL_GV11B 0x0000000B 29#define NVGPU_GPU_IMPL_GV11B 0x0000000B
30#define NVGPU_GPU_IMPL_GV100 0x00000000
29 31
30/* 32/*
31 * this flag is used in struct nvgpu_as_map_buffer_ex_args 33 * this flag is used in struct nvgpu_as_map_buffer_ex_args
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-05 00:20:22 -0400