From de8e057f7eebcfe676278826ab457bf86b1b36fd Mon Sep 17 00:00:00 2001 From: David Nieto Date: Thu, 3 Aug 2017 21:43:50 -0700 Subject: gpu: nvgpu: GV100 support Adds support of GV100 up to devinit. JIRA: EVLR-1693 Change-Id: Ic7aa5f1c20714e05954139f143abb6a3459858fc Signed-off-by: David Nieto Reviewed-on: https://git-master.nvidia.com/r/1532747 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/Makefile | 6 +- drivers/gpu/nvgpu/gv100/fb_gv100.c | 58 + drivers/gpu/nvgpu/gv100/fb_gv100.h | 22 + drivers/gpu/nvgpu/gv100/gr_ctx_gv100.c | 38 + drivers/gpu/nvgpu/gv100/gr_ctx_gv100.h | 28 + drivers/gpu/nvgpu/gv100/gv100.h | 26 + drivers/gpu/nvgpu/gv100/hal_gv100.c | 441 +++ drivers/gpu/nvgpu/gv100/hal_gv100.h | 21 + drivers/gpu/nvgpu/gv100/mm_gv100.c | 41 + drivers/gpu/nvgpu/gv100/mm_gv100.h | 23 + .../nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h | 217 ++ .../nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h | 133 + .../gpu/nvgpu/include/nvgpu/hw/gv100/hw_ce_gv100.h | 101 + .../include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h | 449 +++ .../gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h | 1469 ++++++++ .../nvgpu/include/nvgpu/hw/gv100/hw_fifo_gv100.h | 545 +++ .../nvgpu/include/nvgpu/hw/gv100/hw_flush_gv100.h | 181 + .../nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h | 137 + .../nvgpu/include/nvgpu/hw/gv100/hw_gmmu_gv100.h | 1281 +++++++ .../gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h | 3905 ++++++++++++++++++++ .../nvgpu/include/nvgpu/hw/gv100/hw_ltc_gv100.h | 613 +++ .../gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h | 245 ++ .../nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h | 645 ++++ .../nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h | 205 + .../nvgpu/include/nvgpu/hw/gv100/hw_pram_gv100.h | 57 + .../nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h | 161 + .../nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h | 73 + .../nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h | 85 + .../nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h | 161 + .../nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h | 929 +++++ .../nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h | 761 ++++ .../nvgpu/include/nvgpu/hw/gv100/hw_therm_gv100.h | 293 ++ .../nvgpu/include/nvgpu/hw/gv100/hw_timer_gv100.h | 109 + .../nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h | 229 ++ .../include/nvgpu/hw/gv100/hw_usermode_gv100.h | 89 + .../gpu/nvgpu/include/nvgpu/hw/gv100/hw_xp_gv100.h | 137 + .../nvgpu/include/nvgpu/hw/gv100/hw_xve_gv100.h | 201 + drivers/gpu/nvgpu/nvgpu_gpuid_t19x.h | 9 + include/uapi/linux/nvgpu-t19x.h | 2 + 39 files changed, 14125 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/nvgpu/gv100/fb_gv100.c create mode 100644 drivers/gpu/nvgpu/gv100/fb_gv100.h create mode 100644 drivers/gpu/nvgpu/gv100/gr_ctx_gv100.c create mode 100644 drivers/gpu/nvgpu/gv100/gr_ctx_gv100.h create mode 100644 drivers/gpu/nvgpu/gv100/gv100.h create mode 100644 drivers/gpu/nvgpu/gv100/hal_gv100.c create mode 100644 drivers/gpu/nvgpu/gv100/hal_gv100.h create mode 100644 drivers/gpu/nvgpu/gv100/mm_gv100.c create mode 100644 drivers/gpu/nvgpu/gv100/mm_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ce_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fifo_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_flush_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gmmu_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ltc_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pram_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_therm_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_timer_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_usermode_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xp_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xve_gv100.h diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 1d2feba4..e91b4e69 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -16,7 +16,11 @@ nvgpu-y += \ $(nvgpu-t19x)/gv11b/gr_ctx_gv11b.o \ $(nvgpu-t19x)/gv11b/pmu_gv11b.o \ $(nvgpu-t19x)/gv11b/subctx_gv11b.o \ - $(nvgpu-t19x)/gv11b/regops_gv11b.o + $(nvgpu-t19x)/gv11b/regops_gv11b.o \ + $(nvgpu-t19x)/gv100/mm_gv100.o \ + $(nvgpu-t19x)/gv100/gr_ctx_gv100.o \ + $(nvgpu-t19x)/gv100/fb_gv100.o \ + $(nvgpu-t19x)/gv100/hal_gv100.o nvgpu-$(CONFIG_TEGRA_GK20A) += $(nvgpu-t19x)/gv11b/platform_gv11b_tegra.o nvgpu-$(CONFIG_TEGRA_GK20A_NVHOST) += $(nvgpu-t19x)/common/linux/nvhost_t19x.o diff --git a/drivers/gpu/nvgpu/gv100/fb_gv100.c b/drivers/gpu/nvgpu/gv100/fb_gv100.c new file mode 100644 index 00000000..a3785266 --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/fb_gv100.c @@ -0,0 +1,58 @@ +/* + * GV100 FB + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include + +#include +#include +#include +#include + +#include "gk20a/gk20a.h" +#include "gv11b/fb_gv11b.h" +#include "gv100/fb_gv100.h" + +#include + +#define HW_SCRUB_TIMEOUT_DEFAULT 100 /* usec */ +#define HW_SCRUB_TIMEOUT_MAX 2000000 /* usec */ + +static void gv100_fb_reset(struct gk20a *g) +{ + u32 val; + int retries = HW_SCRUB_TIMEOUT_MAX / HW_SCRUB_TIMEOUT_DEFAULT; + + nvgpu_info(g, "reset gv100 fb"); + + /* wait for memory to be accessible */ + do { + u32 w = gk20a_readl(g, fb_niso_scrub_status_r()); + if (fb_niso_scrub_status_flag_v(w)) { + nvgpu_info(g, "done"); + break; + } + nvgpu_udelay(HW_SCRUB_TIMEOUT_DEFAULT); + } while (--retries); + + val = gk20a_readl(g, fb_mmu_priv_level_mask_r()); + val &= ~fb_mmu_priv_level_mask_write_violation_m(); + gk20a_writel(g, fb_mmu_priv_level_mask_r(), val); +} + +void gv100_init_fb(struct gpu_ops *gops) +{ + gv11b_init_fb(gops); + gops->fb.reset = gv100_fb_reset; +} diff --git a/drivers/gpu/nvgpu/gv100/fb_gv100.h b/drivers/gpu/nvgpu/gv100/fb_gv100.h new file mode 100644 index 00000000..b234fa13 --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/fb_gv100.h @@ -0,0 +1,22 @@ +/* + * GV100 FB + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _NVGPU_GV100_FB +#define _NVGPU_GV100_FB + +struct gpu_ops; + +void gv100_init_fb(struct gpu_ops *gops); +#endif diff --git a/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.c b/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.c new file mode 100644 index 00000000..2e605cce --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.c @@ -0,0 +1,38 @@ +/* + * GV100 Graphics Context + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "gk20a/gk20a.h" +#include "gr_ctx_gv100.h" + +int gr_gv100_get_netlist_name(struct gk20a *g, int index, char *name) +{ + u32 ver = g->gpu_characteristics.arch + g->gpu_characteristics.impl; + + switch (ver) { + case NVGPU_GPUID_GV100: + sprintf(name, "%s/%s", "gv100", + GV100_NETLIST_IMAGE_FW_NAME); + break; + default: + nvgpu_err(g, "no support for GPUID %x", ver); + } + + return 0; +} + +bool gr_gv100_is_firmware_defined(void) +{ + return true; +} diff --git a/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.h b/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.h new file mode 100644 index 00000000..122e750f --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#ifndef __GR_CTX_GV100_H__ +#define __GR_CTX_GV100_H__ + +#include "gk20a/gr_ctx_gk20a.h" +#include "nvgpu_gpuid_t19x.h" + +/* production netlist, one and only one from below */ +#define GV100_NETLIST_IMAGE_FW_NAME GK20A_NETLIST_IMAGE_D + +int gr_gv100_get_netlist_name(struct gk20a *g, int index, char *name); +bool gr_gv100_is_firmware_defined(void); + +#endif /*__GR_CTX_GV100_H__*/ diff --git a/drivers/gpu/nvgpu/gv100/gv100.h b/drivers/gpu/nvgpu/gv100/gv100.h new file mode 100644 index 00000000..eeea64a4 --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/gv100.h @@ -0,0 +1,26 @@ +/* + * GV100 Graphics + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef GV100_H +#define GV100_H + +#include "gk20a/gk20a.h" + +int gv100_init_gpu_characteristics(struct gk20a *g); + +#endif /* GV11B_H */ diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c new file mode 100644 index 00000000..337c607f --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -0,0 +1,441 @@ +/* + * GV100 Tegra HAL interface + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include + +#include +#include + +#include "gk20a/gk20a.h" +#include "gk20a/fifo_gk20a.h" +#include "gk20a/ctxsw_trace_gk20a.h" +#include "gk20a/fecs_trace_gk20a.h" +#include "gk20a/css_gr_gk20a.h" +#include "gk20a/mc_gk20a.h" +#include "gk20a/dbg_gpu_gk20a.h" +#include "gk20a/bus_gk20a.h" +#include "gk20a/pramin_gk20a.h" +#include "gk20a/flcn_gk20a.h" +#include "gk20a/regops_gk20a.h" + +#include "gm20b/ltc_gm20b.h" +#include "gm20b/gr_gm20b.h" +#include "gm20b/fifo_gm20b.h" + +#include "gp106/clk_gp106.h" +#include "gp106/clk_arb_gp106.h" +#include "gp106/pmu_gp106.h" + +#include "gm206/bios_gm206.h" +#include "gp106/therm_gp106.h" +#include "gp106/xve_gp106.h" +#include "gp106/clk_gp106.h" +#include "gp106/flcn_gp106.h" +#include "gp10b/ltc_gp10b.h" +#include "gp10b/therm_gp10b.h" +#include "gp10b/mc_gp10b.h" +#include "gp10b/ce_gp10b.h" +#include "gp10b/priv_ring_gp10b.h" +#include "gp10b/fifo_gp10b.h" +#include "gp10b/fecs_trace_gp10b.h" + +#include "gv11b/hal_gv11b.h" +#include "gv11b/gr_gv11b.h" +#include "gv11b/mc_gv11b.h" +#include "gv11b/ltc_gv11b.h" +#include "gv11b/gv11b.h" +#include "gv11b/ce_gv11b.h" +#include "gv100/gr_ctx_gv100.h" +#include "gv100/mm_gv100.h" +#include "gv11b/pmu_gv11b.h" +#include "gv100/fb_gv100.h" +#include "gv11b/fifo_gv11b.h" +#include "gv11b/gv11b_gating_reglist.h" +#include "gv11b/regops_gv11b.h" +#include "gv11b/subctx_gv11b.h" + +#include "gv100.h" +#include "hal_gv100.h" + +#include +#include + +#include +#include +#include +#include +#include + +static int gv100_get_litter_value(struct gk20a *g, int value) +{ + int ret = EINVAL; + switch (value) { + case GPU_LIT_NUM_GPCS: + ret = proj_scal_litter_num_gpcs_v(); + break; + case GPU_LIT_NUM_PES_PER_GPC: + ret = proj_scal_litter_num_pes_per_gpc_v(); + break; + case GPU_LIT_NUM_ZCULL_BANKS: + ret = proj_scal_litter_num_zcull_banks_v(); + break; + case GPU_LIT_NUM_TPC_PER_GPC: + ret = proj_scal_litter_num_tpc_per_gpc_v(); + break; + case GPU_LIT_NUM_SM_PER_TPC: + ret = proj_scal_litter_num_sm_per_tpc_v(); + break; + case GPU_LIT_NUM_FBPS: + ret = proj_scal_litter_num_fbps_v(); + break; + case GPU_LIT_GPC_BASE: + ret = proj_gpc_base_v(); + break; + case GPU_LIT_GPC_STRIDE: + ret = proj_gpc_stride_v(); + break; + case GPU_LIT_GPC_SHARED_BASE: + ret = proj_gpc_shared_base_v(); + break; + case GPU_LIT_TPC_IN_GPC_BASE: + ret = proj_tpc_in_gpc_base_v(); + break; + case GPU_LIT_TPC_IN_GPC_STRIDE: + ret = proj_tpc_in_gpc_stride_v(); + break; + case GPU_LIT_TPC_IN_GPC_SHARED_BASE: + ret = proj_tpc_in_gpc_shared_base_v(); + break; + case GPU_LIT_PPC_IN_GPC_BASE: + ret = proj_ppc_in_gpc_base_v(); + case GPU_LIT_PPC_IN_GPC_STRIDE: + ret = proj_ppc_in_gpc_stride_v(); + break; + case GPU_LIT_ROP_BASE: + ret = proj_rop_base_v(); + break; + case GPU_LIT_ROP_STRIDE: + ret = proj_rop_stride_v(); + break; + case GPU_LIT_ROP_SHARED_BASE: + ret = proj_rop_shared_base_v(); + break; + case GPU_LIT_HOST_NUM_ENGINES: + ret = proj_host_num_engines_v(); + break; + case GPU_LIT_HOST_NUM_PBDMA: + ret = proj_host_num_pbdma_v(); + break; + case GPU_LIT_LTC_STRIDE: + ret = proj_ltc_stride_v(); + break; + case GPU_LIT_LTS_STRIDE: + ret = proj_lts_stride_v(); + break; + case GPU_LIT_NUM_FBPAS: + ret = proj_scal_litter_num_fbpas_v(); + break; + case GPU_LIT_FBPA_STRIDE: + ret = proj_fbpa_stride_v(); + break; + case GPU_LIT_SM_PRI_STRIDE: + ret = proj_sm_stride_v(); + break; + + default: + break; + } + + return ret; +} + +int gv100_init_gpu_characteristics(struct gk20a *g) +{ + struct nvgpu_gpu_characteristics *gpu = &g->gpu_characteristics; + + int err; + + err = gk20a_init_gpu_characteristics(g); + if (err) + return err; + + gpu->flags |= + NVGPU_GPU_FLAGS_SUPPORT_TSG_SUBCONTEXTS; + + return 0; +} + + + +static const struct gpu_ops gv100_ops = { + .ltc = { + .determine_L2_size_bytes = gp10b_determine_L2_size_bytes, + .set_zbc_s_entry = gv11b_ltc_set_zbc_stencil_entry, + .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry, + .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry, + .init_cbc = NULL, + .init_fs_state = gv11b_ltc_init_fs_state, + .init_comptags = gp10b_ltc_init_comptags, + .cbc_ctrl = gm20b_ltc_cbc_ctrl, + .isr = gv11b_ltc_isr, + .cbc_fix_config = gv11b_ltc_cbc_fix_config, + .flush = gm20b_flush_ltc, + .set_enabled = gp10b_ltc_set_enabled, + }, + .ce2 = { + .isr_stall = gv11b_ce_isr, + .isr_nonstall = gp10b_ce_nonstall_isr, + .get_num_pce = gv11b_ce_get_num_pce, + }, + .fifo = { + .init_fifo_setup_hw = gv11b_init_fifo_setup_hw, + .bind_channel = channel_gm20b_bind, + .unbind_channel = channel_gv11b_unbind, + .disable_channel = gk20a_fifo_disable_channel, + .enable_channel = gk20a_fifo_enable_channel, + .alloc_inst = gk20a_fifo_alloc_inst, + .free_inst = gk20a_fifo_free_inst, + .setup_ramfc = channel_gv11b_setup_ramfc, + .channel_set_priority = gk20a_fifo_set_priority, + .channel_set_timeslice = gk20a_fifo_set_timeslice, + .default_timeslice_us = gk20a_fifo_default_timeslice_us, + .setup_userd = gk20a_fifo_setup_userd, + .userd_gp_get = gv11b_userd_gp_get, + .userd_gp_put = gv11b_userd_gp_put, + .userd_pb_get = gv11b_userd_pb_get, + .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val, + .preempt_channel = gv11b_fifo_preempt_channel, + .preempt_tsg = gv11b_fifo_preempt_tsg, + .update_runlist = gk20a_fifo_update_runlist, + .trigger_mmu_fault = NULL, + .get_mmu_fault_info = NULL, + .wait_engine_idle = gk20a_fifo_wait_engine_idle, + .get_num_fifos = gv11b_fifo_get_num_fifos, + .get_pbdma_signature = gp10b_fifo_get_pbdma_signature, + .set_runlist_interleave = gk20a_fifo_set_runlist_interleave, + .tsg_set_timeslice = gk20a_fifo_tsg_set_timeslice, + .force_reset_ch = gk20a_fifo_force_reset_ch, + .engine_enum_from_type = gp10b_fifo_engine_enum_from_type, + .device_info_data_parse = gp10b_device_info_data_parse, + .eng_runlist_base_size = fifo_eng_runlist_base__size_1_v, + .init_engine_info = gk20a_fifo_init_engine_info, + .runlist_entry_size = ram_rl_entry_size_v, + .get_tsg_runlist_entry = gv11b_get_tsg_runlist_entry, + .get_ch_runlist_entry = gv11b_get_ch_runlist_entry, + .is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc, + .dump_pbdma_status = gk20a_dump_pbdma_status, + .dump_eng_status = gv11b_dump_eng_status, + .dump_channel_status_ramfc = gv11b_dump_channel_status_ramfc, + .intr_0_error_mask = gv11b_fifo_intr_0_error_mask, + .is_preempt_pending = gv11b_fifo_is_preempt_pending, + .init_pbdma_intr_descs = gv11b_fifo_init_pbdma_intr_descs, + .reset_enable_hw = gv11b_init_fifo_reset_enable_hw, + .teardown_ch_tsg = gv11b_fifo_teardown_ch_tsg, + .handle_sched_error = gv11b_fifo_handle_sched_error, + .handle_pbdma_intr_0 = gv11b_fifo_handle_pbdma_intr_0, + .handle_pbdma_intr_1 = gv11b_fifo_handle_pbdma_intr_1, + .init_eng_method_buffers = gv11b_fifo_init_eng_method_buffers, + .deinit_eng_method_buffers = + gv11b_fifo_deinit_eng_method_buffers, + .tsg_bind_channel = gk20a_tsg_bind_channel, + .tsg_unbind_channel = gk20a_tsg_unbind_channel, +#ifdef CONFIG_TEGRA_GK20A_NVHOST + .alloc_syncpt_buf = gv11b_fifo_alloc_syncpt_buf, + .free_syncpt_buf = gv11b_fifo_free_syncpt_buf, + .add_syncpt_wait_cmd = gv11b_fifo_add_syncpt_wait_cmd, + .get_syncpt_wait_cmd_size = gv11b_fifo_get_syncpt_wait_cmd_size, + .add_syncpt_incr_cmd = gv11b_fifo_add_syncpt_incr_cmd, + .get_syncpt_incr_cmd_size = gv11b_fifo_get_syncpt_incr_cmd_size, +#endif + .resetup_ramfc = NULL, + .device_info_fault_id = top_device_info_data_fault_id_enum_v, + .free_channel_ctx_header = gv11b_free_subctx_header, + .preempt_ch_tsg = gv11b_fifo_preempt_ch_tsg, + .handle_ctxsw_timeout = gv11b_fifo_handle_ctxsw_timeout, + }, + .gr_ctx = { + .get_netlist_name = gr_gv100_get_netlist_name, + .is_fw_defined = gr_gv100_is_firmware_defined, + }, +#ifdef CONFIG_GK20A_CTXSW_TRACE + .fecs_trace = { + .alloc_user_buffer = gk20a_ctxsw_dev_ring_alloc, + .free_user_buffer = gk20a_ctxsw_dev_ring_free, + .mmap_user_buffer = gk20a_ctxsw_dev_mmap_buffer, + .init = gk20a_fecs_trace_init, + .deinit = gk20a_fecs_trace_deinit, + .enable = gk20a_fecs_trace_enable, + .disable = gk20a_fecs_trace_disable, + .is_enabled = gk20a_fecs_trace_is_enabled, + .reset = gk20a_fecs_trace_reset, + .flush = gp10b_fecs_trace_flush, + .poll = gk20a_fecs_trace_poll, + .bind_channel = gk20a_fecs_trace_bind_channel, + .unbind_channel = gk20a_fecs_trace_unbind_channel, + .max_entries = gk20a_gr_max_entries, + }, +#endif /* CONFIG_GK20A_CTXSW_TRACE */ + .pramin = { + .enter = gk20a_pramin_enter, + .exit = gk20a_pramin_exit, + .data032_r = pram_data032_r, + }, + .clk = { + .init_clk_support = gp106_init_clk_support, + .get_crystal_clk_hz = gp106_crystal_clk_hz, + .measure_freq = gp106_clk_measure_freq, + .suspend_clk_support = gp106_suspend_clk_support, + }, + .clk_arb = { + .get_arbiter_clk_domains = gp106_get_arbiter_clk_domains, + .get_arbiter_clk_range = gp106_get_arbiter_clk_range, + .get_arbiter_clk_default = gp106_get_arbiter_clk_default, + .get_current_pstate = nvgpu_clk_arb_get_current_pstate, + }, + .mc = { + .intr_enable = mc_gv11b_intr_enable, + .intr_unit_config = mc_gp10b_intr_unit_config, + .isr_stall = mc_gp10b_isr_stall, + .intr_stall = mc_gp10b_intr_stall, + .intr_stall_pause = mc_gp10b_intr_stall_pause, + .intr_stall_resume = mc_gp10b_intr_stall_resume, + .intr_nonstall = mc_gp10b_intr_nonstall, + .intr_nonstall_pause = mc_gp10b_intr_nonstall_pause, + .intr_nonstall_resume = mc_gp10b_intr_nonstall_resume, + .enable = gk20a_mc_enable, + .disable = gk20a_mc_disable, + .reset = gk20a_mc_reset, + .boot_0 = gk20a_mc_boot_0, + .is_intr1_pending = mc_gp10b_is_intr1_pending, + .is_intr_hub_pending = gv11b_mc_is_intr_hub_pending, + }, + .debug = { + .show_dump = gk20a_debug_show_dump, + }, + .dbg_session_ops = { + .exec_reg_ops = exec_regops_gk20a, + .dbg_set_powergate = dbg_set_powergate, + .check_and_set_global_reservation = + nvgpu_check_and_set_global_reservation, + .check_and_set_context_reservation = + nvgpu_check_and_set_context_reservation, + .release_profiler_reservation = + nvgpu_release_profiler_reservation, + .perfbuffer_enable = gk20a_perfbuf_enable_locked, + .perfbuffer_disable = gk20a_perfbuf_disable_locked, + }, + .bus = { + .init_hw = gk20a_bus_init_hw, + .isr = gk20a_bus_isr, + .read_ptimer = gk20a_read_ptimer, + .bar1_bind = NULL, + }, +#if defined(CONFIG_GK20A_CYCLE_STATS) + .css = { + .enable_snapshot = css_hw_enable_snapshot, + .disable_snapshot = css_hw_disable_snapshot, + .check_data_available = css_hw_check_data_available, + .set_handled_snapshots = css_hw_set_handled_snapshots, + .allocate_perfmon_ids = css_gr_allocate_perfmon_ids, + .release_perfmon_ids = css_gr_release_perfmon_ids, + }, +#endif + .xve = { + .sw_init = xve_sw_init_gp106, + .get_speed = xve_get_speed_gp106, + .set_speed = xve_set_speed_gp106, + .available_speeds = xve_available_speeds_gp106, + .xve_readl = xve_xve_readl_gp106, + .xve_writel = xve_xve_writel_gp106, + .disable_aspm = xve_disable_aspm_gp106, + .reset_gpu = xve_reset_gpu_gp106, +#if defined(CONFIG_PCI_MSI) + .rearm_msi = xve_rearm_msi_gp106, +#endif + .enable_shadow_rom = xve_enable_shadow_rom_gp106, + .disable_shadow_rom = xve_disable_shadow_rom_gp106, + }, + .falcon = { + .falcon_hal_sw_init = gp106_falcon_hal_sw_init, + }, + .priv_ring = { + .isr = gp10b_priv_ring_isr, + }, + .chip_init_gpu_characteristics = gv100_init_gpu_characteristics, + .get_litter_value = gv100_get_litter_value, + .bios_init = gm206_bios_init, +}; + +int gv100_init_hal(struct gk20a *g) +{ + struct gpu_ops *gops = &g->ops; + struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; + + gops->ltc = gv100_ops.ltc; + gops->ce2 = gv100_ops.ce2; + gops->clock_gating = gv100_ops.clock_gating; + gops->fifo = gv100_ops.fifo; + gops->gr_ctx = gv100_ops.gr_ctx; + gops->fecs_trace = gv100_ops.fecs_trace; + gops->pramin = gv100_ops.pramin; + gops->therm = gv100_ops.therm; + gops->mc = gv100_ops.mc; + gops->debug = gv100_ops.debug; + gops->dbg_session_ops = gv100_ops.dbg_session_ops; + gops->bus = gv100_ops.bus; +#if defined(CONFIG_GK20A_CYCLE_STATS) + gops->css = gv100_ops.css; +#endif + gops->xve = gv100_ops.xve; + gops->falcon = gv100_ops.falcon; + gops->priv_ring = gv100_ops.priv_ring; + + /* clocks */ + gops->clk.init_clk_support = gv100_ops.clk.init_clk_support; + gops->clk.get_crystal_clk_hz = gv100_ops.clk.get_crystal_clk_hz; + gops->clk.measure_freq = gv100_ops.clk.measure_freq; + gops->clk.suspend_clk_support = gv100_ops.clk.suspend_clk_support; + + /* Lone functions */ + gops->chip_init_gpu_characteristics = + gv100_ops.chip_init_gpu_characteristics; + gops->get_litter_value = gv100_ops.get_litter_value; + gops->bios_init = gv100_ops.bios_init; + + __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); + __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); + __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); + /* for now */ + __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); + + g->bootstrap_owner = LSF_FALCON_ID_SEC2; + + gv11b_init_gr(g); + gv100_init_fb(gops); + gv100_init_mm(gops); + gp106_init_pmu_ops(g); + + g->name = "gv10x"; + + c->twod_class = FERMI_TWOD_A; + c->threed_class = VOLTA_A; + c->compute_class = VOLTA_COMPUTE_A; + c->gpfifo_class = VOLTA_CHANNEL_GPFIFO_A; + c->inline_to_memory_class = KEPLER_INLINE_TO_MEMORY_B; + c->dma_copy_class = VOLTA_DMA_COPY_A; + + return 0; +} diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.h b/drivers/gpu/nvgpu/gv100/hal_gv100.h new file mode 100644 index 00000000..a7c74db0 --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.h @@ -0,0 +1,21 @@ +/* + * GV100 Tegra HAL interface + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _NVGPU_HAL_GV11B_H +#define _NVGPU_HAL_GV11B_H +struct gk20a; + +int gv100_init_hal(struct gk20a *gops); +#endif diff --git a/drivers/gpu/nvgpu/gv100/mm_gv100.c b/drivers/gpu/nvgpu/gv100/mm_gv100.c new file mode 100644 index 00000000..fbc5df79 --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/mm_gv100.c @@ -0,0 +1,41 @@ +/* + * GV100 memory management + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "gk20a/gk20a.h" +#include "gv11b/mm_gv11b.h" +#include "gv100/mm_gv100.h" + +#include + +static size_t gv100_mm_get_vidmem_size(struct gk20a *g) +{ + u32 range = gk20a_readl(g, fb_mmu_local_memory_range_r()); + u32 mag = fb_mmu_local_memory_range_lower_mag_v(range); + u32 scale = fb_mmu_local_memory_range_lower_scale_v(range); + u32 ecc = fb_mmu_local_memory_range_ecc_mode_v(range); + size_t bytes = ((size_t)mag << scale) * SZ_1M; + + if (ecc) + bytes = bytes / 16 * 15; + + return bytes; +} + +void gv100_init_mm(struct gpu_ops *gops) +{ + gv11b_init_mm(gops); + gops->mm.get_vidmem_size = gv100_mm_get_vidmem_size; + gops->mm.get_physical_addr_bits = NULL; +} diff --git a/drivers/gpu/nvgpu/gv100/mm_gv100.h b/drivers/gpu/nvgpu/gv100/mm_gv100.h new file mode 100644 index 00000000..ff1bc3df --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/mm_gv100.h @@ -0,0 +1,23 @@ +/* + * GV100 memory management + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef MM_GV100_H +#define MM_GV100_H + +struct gpu_ops; + +void gv100_init_mm(struct gpu_ops *gops); + +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h new file mode 100644 index 00000000..c95d5af4 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h @@ -0,0 +1,217 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_bus_gv100_h_ +#define _hw_bus_gv100_h_ + +static inline u32 bus_bar0_window_r(void) +{ + return 0x00001700; +} +static inline u32 bus_bar0_window_base_f(u32 v) +{ + return (v & 0xffffff) << 0; +} +static inline u32 bus_bar0_window_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void) +{ + return 0x2000000; +} +static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void) +{ + return 0x3000000; +} +static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void) +{ + return 0x00000010; +} +static inline u32 bus_bar1_block_r(void) +{ + return 0x00001704; +} +static inline u32 bus_bar1_block_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 bus_bar1_block_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 bus_bar1_block_target_sys_mem_coh_f(void) +{ + return 0x20000000; +} +static inline u32 bus_bar1_block_target_sys_mem_ncoh_f(void) +{ + return 0x30000000; +} +static inline u32 bus_bar1_block_mode_virtual_f(void) +{ + return 0x80000000; +} +static inline u32 bus_bar2_block_r(void) +{ + return 0x00001714; +} +static inline u32 bus_bar2_block_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 bus_bar2_block_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 bus_bar2_block_target_sys_mem_coh_f(void) +{ + return 0x20000000; +} +static inline u32 bus_bar2_block_target_sys_mem_ncoh_f(void) +{ + return 0x30000000; +} +static inline u32 bus_bar2_block_mode_virtual_f(void) +{ + return 0x80000000; +} +static inline u32 bus_bar1_block_ptr_shift_v(void) +{ + return 0x0000000c; +} +static inline u32 bus_bar2_block_ptr_shift_v(void) +{ + return 0x0000000c; +} +static inline u32 bus_bind_status_r(void) +{ + return 0x00001710; +} +static inline u32 bus_bind_status_bar1_pending_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 bus_bind_status_bar1_pending_empty_f(void) +{ + return 0x0; +} +static inline u32 bus_bind_status_bar1_pending_busy_f(void) +{ + return 0x1; +} +static inline u32 bus_bind_status_bar1_outstanding_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 bus_bind_status_bar1_outstanding_false_f(void) +{ + return 0x0; +} +static inline u32 bus_bind_status_bar1_outstanding_true_f(void) +{ + return 0x2; +} +static inline u32 bus_bind_status_bar2_pending_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 bus_bind_status_bar2_pending_empty_f(void) +{ + return 0x0; +} +static inline u32 bus_bind_status_bar2_pending_busy_f(void) +{ + return 0x4; +} +static inline u32 bus_bind_status_bar2_outstanding_v(u32 r) +{ + return (r >> 3) & 0x1; +} +static inline u32 bus_bind_status_bar2_outstanding_false_f(void) +{ + return 0x0; +} +static inline u32 bus_bind_status_bar2_outstanding_true_f(void) +{ + return 0x8; +} +static inline u32 bus_intr_0_r(void) +{ + return 0x00001100; +} +static inline u32 bus_intr_0_pri_squash_m(void) +{ + return 0x1 << 1; +} +static inline u32 bus_intr_0_pri_fecserr_m(void) +{ + return 0x1 << 2; +} +static inline u32 bus_intr_0_pri_timeout_m(void) +{ + return 0x1 << 3; +} +static inline u32 bus_intr_en_0_r(void) +{ + return 0x00001140; +} +static inline u32 bus_intr_en_0_pri_squash_m(void) +{ + return 0x1 << 1; +} +static inline u32 bus_intr_en_0_pri_fecserr_m(void) +{ + return 0x1 << 2; +} +static inline u32 bus_intr_en_0_pri_timeout_m(void) +{ + return 0x1 << 3; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h new file mode 100644 index 00000000..f64f542c --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_ccsr_gv100_h_ +#define _hw_ccsr_gv100_h_ + +static inline u32 ccsr_channel_inst_r(u32 i) +{ + return 0x00800000 + i*8; +} +static inline u32 ccsr_channel_inst__size_1_v(void) +{ + return 0x00001000; +} +static inline u32 ccsr_channel_inst_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 ccsr_channel_inst_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 ccsr_channel_inst_target_sys_mem_coh_f(void) +{ + return 0x20000000; +} +static inline u32 ccsr_channel_inst_target_sys_mem_ncoh_f(void) +{ + return 0x30000000; +} +static inline u32 ccsr_channel_inst_bind_false_f(void) +{ + return 0x0; +} +static inline u32 ccsr_channel_inst_bind_true_f(void) +{ + return 0x80000000; +} +static inline u32 ccsr_channel_r(u32 i) +{ + return 0x00800004 + i*8; +} +static inline u32 ccsr_channel__size_1_v(void) +{ + return 0x00001000; +} +static inline u32 ccsr_channel_enable_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ccsr_channel_enable_set_f(u32 v) +{ + return (v & 0x1) << 10; +} +static inline u32 ccsr_channel_enable_set_true_f(void) +{ + return 0x400; +} +static inline u32 ccsr_channel_enable_clr_true_f(void) +{ + return 0x800; +} +static inline u32 ccsr_channel_status_v(u32 r) +{ + return (r >> 24) & 0xf; +} +static inline u32 ccsr_channel_pbdma_faulted_f(u32 v) +{ + return (v & 0x1) << 22; +} +static inline u32 ccsr_channel_pbdma_faulted_reset_f(void) +{ + return 0x400000; +} +static inline u32 ccsr_channel_eng_faulted_f(u32 v) +{ + return (v & 0x1) << 23; +} +static inline u32 ccsr_channel_eng_faulted_reset_f(void) +{ + return 0x800000; +} +static inline u32 ccsr_channel_busy_v(u32 r) +{ + return (r >> 28) & 0x1; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ce_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ce_gv100.h new file mode 100644 index 00000000..26971f3f --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ce_gv100.h @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_ce_gv100_h_ +#define _hw_ce_gv100_h_ + +static inline u32 ce_intr_status_r(u32 i) +{ + return 0x00104410 + i*128; +} +static inline u32 ce_intr_status_blockpipe_pending_f(void) +{ + return 0x1; +} +static inline u32 ce_intr_status_blockpipe_reset_f(void) +{ + return 0x1; +} +static inline u32 ce_intr_status_nonblockpipe_pending_f(void) +{ + return 0x2; +} +static inline u32 ce_intr_status_nonblockpipe_reset_f(void) +{ + return 0x2; +} +static inline u32 ce_intr_status_launcherr_pending_f(void) +{ + return 0x4; +} +static inline u32 ce_intr_status_launcherr_reset_f(void) +{ + return 0x4; +} +static inline u32 ce_intr_status_invalid_config_pending_f(void) +{ + return 0x8; +} +static inline u32 ce_intr_status_invalid_config_reset_f(void) +{ + return 0x8; +} +static inline u32 ce_intr_status_mthd_buffer_fault_pending_f(void) +{ + return 0x10; +} +static inline u32 ce_intr_status_mthd_buffer_fault_reset_f(void) +{ + return 0x10; +} +static inline u32 ce_pce_map_r(void) +{ + return 0x00104028; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h new file mode 100644 index 00000000..f5593095 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h @@ -0,0 +1,449 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_ctxsw_prog_gv100_h_ +#define _hw_ctxsw_prog_gv100_h_ + +static inline u32 ctxsw_prog_fecs_header_v(void) +{ + return 0x00000100; +} +static inline u32 ctxsw_prog_main_image_num_gpcs_o(void) +{ + return 0x00000008; +} +static inline u32 ctxsw_prog_main_image_ctl_o(void) +{ + return 0x0000000c; +} +static inline u32 ctxsw_prog_main_image_ctl_type_f(u32 v) +{ + return (v & 0x3f) << 0; +} +static inline u32 ctxsw_prog_main_image_ctl_type_undefined_v(void) +{ + return 0x00000000; +} +static inline u32 ctxsw_prog_main_image_ctl_type_opengl_v(void) +{ + return 0x00000008; +} +static inline u32 ctxsw_prog_main_image_ctl_type_dx9_v(void) +{ + return 0x00000010; +} +static inline u32 ctxsw_prog_main_image_ctl_type_dx10_v(void) +{ + return 0x00000011; +} +static inline u32 ctxsw_prog_main_image_ctl_type_dx11_v(void) +{ + return 0x00000012; +} +static inline u32 ctxsw_prog_main_image_ctl_type_compute_v(void) +{ + return 0x00000020; +} +static inline u32 ctxsw_prog_main_image_ctl_type_per_veid_header_v(void) +{ + return 0x00000021; +} +static inline u32 ctxsw_prog_main_image_patch_count_o(void) +{ + return 0x00000010; +} +static inline u32 ctxsw_prog_main_image_context_id_o(void) +{ + return 0x000000f0; +} +static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void) +{ + return 0x00000014; +} +static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void) +{ + return 0x00000018; +} +static inline u32 ctxsw_prog_main_image_zcull_o(void) +{ + return 0x0000001c; +} +static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void) +{ + return 0x00000001; +} +static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void) +{ + return 0x00000002; +} +static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void) +{ + return 0x00000020; +} +static inline u32 ctxsw_prog_main_image_pm_o(void) +{ + return 0x00000028; +} +static inline u32 ctxsw_prog_main_image_pm_mode_m(void) +{ + return 0x7 << 0; +} +static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void) +{ + return 0x0; +} +static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void) +{ + return 0x7 << 3; +} +static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void) +{ + return 0x8; +} +static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void) +{ + return 0x0; +} +static inline u32 ctxsw_prog_main_image_pm_ptr_o(void) +{ + return 0x0000002c; +} +static inline u32 ctxsw_prog_main_image_num_save_ops_o(void) +{ + return 0x000000f4; +} +static inline u32 ctxsw_prog_main_image_num_wfi_save_ops_o(void) +{ + return 0x000000d0; +} +static inline u32 ctxsw_prog_main_image_num_cta_save_ops_o(void) +{ + return 0x000000d4; +} +static inline u32 ctxsw_prog_main_image_num_gfxp_save_ops_o(void) +{ + return 0x000000d8; +} +static inline u32 ctxsw_prog_main_image_num_cilp_save_ops_o(void) +{ + return 0x000000dc; +} +static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void) +{ + return 0x000000f8; +} +static inline u32 ctxsw_prog_main_image_zcull_ptr_hi_o(void) +{ + return 0x00000060; +} +static inline u32 ctxsw_prog_main_image_zcull_ptr_hi_v_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 ctxsw_prog_main_image_pm_ptr_hi_o(void) +{ + return 0x00000094; +} +static inline u32 ctxsw_prog_main_image_full_preemption_ptr_hi_o(void) +{ + return 0x00000064; +} +static inline u32 ctxsw_prog_main_image_full_preemption_ptr_hi_v_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 ctxsw_prog_main_image_full_preemption_ptr_o(void) +{ + return 0x00000068; +} +static inline u32 ctxsw_prog_main_image_full_preemption_ptr_v_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_o(void) +{ + return 0x00000070; +} +static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_v_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_o(void) +{ + return 0x00000074; +} +static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_v_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ctxsw_prog_main_image_context_buffer_ptr_hi_o(void) +{ + return 0x00000078; +} +static inline u32 ctxsw_prog_main_image_context_buffer_ptr_hi_v_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 ctxsw_prog_main_image_context_buffer_ptr_o(void) +{ + return 0x0000007c; +} +static inline u32 ctxsw_prog_main_image_context_buffer_ptr_v_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ctxsw_prog_main_image_magic_value_o(void) +{ + return 0x000000fc; +} +static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void) +{ + return 0x600dc0de; +} +static inline u32 ctxsw_prog_local_priv_register_ctl_o(void) +{ + return 0x0000000c; +} +static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 ctxsw_prog_main_image_global_cb_ptr_o(void) +{ + return 0x000000b8; +} +static inline u32 ctxsw_prog_main_image_global_cb_ptr_v_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ctxsw_prog_main_image_global_cb_ptr_hi_o(void) +{ + return 0x000000bc; +} +static inline u32 ctxsw_prog_main_image_global_cb_ptr_hi_v_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_o(void) +{ + return 0x000000c0; +} +static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_v_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_hi_o(void) +{ + return 0x000000c4; +} +static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_hi_v_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 ctxsw_prog_main_image_control_block_ptr_o(void) +{ + return 0x000000c8; +} +static inline u32 ctxsw_prog_main_image_control_block_ptr_v_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ctxsw_prog_main_image_control_block_ptr_hi_o(void) +{ + return 0x000000cc; +} +static inline u32 ctxsw_prog_main_image_control_block_ptr_hi_v_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_lo_o(void) +{ + return 0x000000e0; +} +static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_lo_v_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_hi_o(void) +{ + return 0x000000e4; +} +static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_hi_v_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 ctxsw_prog_local_image_ppc_info_o(void) +{ + return 0x000000f4; +} +static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r) +{ + return (r >> 16) & 0xffff; +} +static inline u32 ctxsw_prog_local_image_num_tpcs_o(void) +{ + return 0x000000f8; +} +static inline u32 ctxsw_prog_local_magic_value_o(void) +{ + return 0x000000fc; +} +static inline u32 ctxsw_prog_local_magic_value_v_value_v(void) +{ + return 0xad0becab; +} +static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void) +{ + return 0x000000ec; +} +static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r) +{ + return (r >> 16) & 0xff; +} +static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void) +{ + return 0x00000100; +} +static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void) +{ + return 0x00000004; +} +static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void) +{ + return 0x00000000; +} +static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void) +{ + return 0x00000002; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void) +{ + return 0x000000a0; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void) +{ + return 2; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v) +{ + return (v & 0x3) << 0; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void) +{ + return 0x3 << 0; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r) +{ + return (r >> 0) & 0x3; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void) +{ + return 0x0; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void) +{ + return 0x2; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void) +{ + return 0x000000a4; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void) +{ + return 0x000000a8; +} +static inline u32 ctxsw_prog_main_image_misc_options_o(void) +{ + return 0x0000003c; +} +static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void) +{ + return 0x1 << 3; +} +static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void) +{ + return 0x0; +} +static inline u32 ctxsw_prog_main_image_graphics_preemption_options_o(void) +{ + return 0x00000080; +} +static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_f(u32 v) +{ + return (v & 0x3) << 0; +} +static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f(void) +{ + return 0x1; +} +static inline u32 ctxsw_prog_main_image_compute_preemption_options_o(void) +{ + return 0x00000084; +} +static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_f(u32 v) +{ + return (v & 0x3) << 0; +} +static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cta_f(void) +{ + return 0x1; +} +static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cilp_f(void) +{ + return 0x2; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h new file mode 100644 index 00000000..ce726633 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h @@ -0,0 +1,1469 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_fb_gv100_h_ +#define _hw_fb_gv100_h_ + +static inline u32 fb_fbhub_num_active_ltcs_r(void) +{ + return 0x00100800; +} +static inline u32 fb_mmu_ctrl_r(void) +{ + return 0x00100c80; +} +static inline u32 fb_mmu_ctrl_vm_pg_size_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 fb_mmu_ctrl_vm_pg_size_128kb_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_ctrl_vm_pg_size_64kb_f(void) +{ + return 0x1; +} +static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r) +{ + return (r >> 15) & 0x1; +} +static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r) +{ + return (r >> 16) & 0xff; +} +static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_v(u32 r) +{ + return (r >> 11) & 0x1; +} +static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_true_f(void) +{ + return 0x800; +} +static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_false_f(void) +{ + return 0x0; +} +static inline u32 fb_priv_mmu_phy_secure_r(void) +{ + return 0x00100ce4; +} +static inline u32 fb_mmu_invalidate_pdb_r(void) +{ + return 0x00100cb8; +} +static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_invalidate_pdb_aperture_sys_mem_f(void) +{ + return 0x2; +} +static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v) +{ + return (v & 0xfffffff) << 4; +} +static inline u32 fb_mmu_invalidate_r(void) +{ + return 0x00100cbc; +} +static inline u32 fb_mmu_invalidate_all_va_true_f(void) +{ + return 0x1; +} +static inline u32 fb_mmu_invalidate_all_pdb_true_f(void) +{ + return 0x2; +} +static inline u32 fb_mmu_invalidate_hubtlb_only_s(void) +{ + return 1; +} +static inline u32 fb_mmu_invalidate_hubtlb_only_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 fb_mmu_invalidate_hubtlb_only_m(void) +{ + return 0x1 << 2; +} +static inline u32 fb_mmu_invalidate_hubtlb_only_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 fb_mmu_invalidate_hubtlb_only_true_f(void) +{ + return 0x4; +} +static inline u32 fb_mmu_invalidate_replay_s(void) +{ + return 3; +} +static inline u32 fb_mmu_invalidate_replay_f(u32 v) +{ + return (v & 0x7) << 3; +} +static inline u32 fb_mmu_invalidate_replay_m(void) +{ + return 0x7 << 3; +} +static inline u32 fb_mmu_invalidate_replay_v(u32 r) +{ + return (r >> 3) & 0x7; +} +static inline u32 fb_mmu_invalidate_replay_none_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_invalidate_replay_start_f(void) +{ + return 0x8; +} +static inline u32 fb_mmu_invalidate_replay_start_ack_all_f(void) +{ + return 0x10; +} +static inline u32 fb_mmu_invalidate_replay_cancel_global_f(void) +{ + return 0x20; +} +static inline u32 fb_mmu_invalidate_sys_membar_s(void) +{ + return 1; +} +static inline u32 fb_mmu_invalidate_sys_membar_f(u32 v) +{ + return (v & 0x1) << 6; +} +static inline u32 fb_mmu_invalidate_sys_membar_m(void) +{ + return 0x1 << 6; +} +static inline u32 fb_mmu_invalidate_sys_membar_v(u32 r) +{ + return (r >> 6) & 0x1; +} +static inline u32 fb_mmu_invalidate_sys_membar_true_f(void) +{ + return 0x40; +} +static inline u32 fb_mmu_invalidate_ack_s(void) +{ + return 2; +} +static inline u32 fb_mmu_invalidate_ack_f(u32 v) +{ + return (v & 0x3) << 7; +} +static inline u32 fb_mmu_invalidate_ack_m(void) +{ + return 0x3 << 7; +} +static inline u32 fb_mmu_invalidate_ack_v(u32 r) +{ + return (r >> 7) & 0x3; +} +static inline u32 fb_mmu_invalidate_ack_ack_none_required_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_invalidate_ack_ack_intranode_f(void) +{ + return 0x100; +} +static inline u32 fb_mmu_invalidate_ack_ack_globally_f(void) +{ + return 0x80; +} +static inline u32 fb_mmu_invalidate_cancel_client_id_s(void) +{ + return 6; +} +static inline u32 fb_mmu_invalidate_cancel_client_id_f(u32 v) +{ + return (v & 0x3f) << 9; +} +static inline u32 fb_mmu_invalidate_cancel_client_id_m(void) +{ + return 0x3f << 9; +} +static inline u32 fb_mmu_invalidate_cancel_client_id_v(u32 r) +{ + return (r >> 9) & 0x3f; +} +static inline u32 fb_mmu_invalidate_cancel_gpc_id_s(void) +{ + return 5; +} +static inline u32 fb_mmu_invalidate_cancel_gpc_id_f(u32 v) +{ + return (v & 0x1f) << 15; +} +static inline u32 fb_mmu_invalidate_cancel_gpc_id_m(void) +{ + return 0x1f << 15; +} +static inline u32 fb_mmu_invalidate_cancel_gpc_id_v(u32 r) +{ + return (r >> 15) & 0x1f; +} +static inline u32 fb_mmu_invalidate_cancel_client_type_s(void) +{ + return 1; +} +static inline u32 fb_mmu_invalidate_cancel_client_type_f(u32 v) +{ + return (v & 0x1) << 20; +} +static inline u32 fb_mmu_invalidate_cancel_client_type_m(void) +{ + return 0x1 << 20; +} +static inline u32 fb_mmu_invalidate_cancel_client_type_v(u32 r) +{ + return (r >> 20) & 0x1; +} +static inline u32 fb_mmu_invalidate_cancel_client_type_gpc_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_invalidate_cancel_client_type_hub_f(void) +{ + return 0x100000; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_s(void) +{ + return 3; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_f(u32 v) +{ + return (v & 0x7) << 24; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_m(void) +{ + return 0x7 << 24; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_v(u32 r) +{ + return (r >> 24) & 0x7; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_all_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_pte_only_f(void) +{ + return 0x1000000; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde0_f(void) +{ + return 0x2000000; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde1_f(void) +{ + return 0x3000000; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde2_f(void) +{ + return 0x4000000; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde3_f(void) +{ + return 0x5000000; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde4_f(void) +{ + return 0x6000000; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde5_f(void) +{ + return 0x7000000; +} +static inline u32 fb_mmu_invalidate_trigger_s(void) +{ + return 1; +} +static inline u32 fb_mmu_invalidate_trigger_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 fb_mmu_invalidate_trigger_m(void) +{ + return 0x1 << 31; +} +static inline u32 fb_mmu_invalidate_trigger_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 fb_mmu_invalidate_trigger_true_f(void) +{ + return 0x80000000; +} +static inline u32 fb_mmu_debug_wr_r(void) +{ + return 0x00100cc8; +} +static inline u32 fb_mmu_debug_wr_aperture_s(void) +{ + return 2; +} +static inline u32 fb_mmu_debug_wr_aperture_f(u32 v) +{ + return (v & 0x3) << 0; +} +static inline u32 fb_mmu_debug_wr_aperture_m(void) +{ + return 0x3 << 0; +} +static inline u32 fb_mmu_debug_wr_aperture_v(u32 r) +{ + return (r >> 0) & 0x3; +} +static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_debug_wr_aperture_sys_mem_coh_f(void) +{ + return 0x2; +} +static inline u32 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(void) +{ + return 0x3; +} +static inline u32 fb_mmu_debug_wr_vol_false_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_debug_wr_vol_true_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_debug_wr_vol_true_f(void) +{ + return 0x4; +} +static inline u32 fb_mmu_debug_wr_addr_f(u32 v) +{ + return (v & 0xfffffff) << 4; +} +static inline u32 fb_mmu_debug_wr_addr_alignment_v(void) +{ + return 0x0000000c; +} +static inline u32 fb_mmu_debug_rd_r(void) +{ + return 0x00100ccc; +} +static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_debug_rd_aperture_sys_mem_coh_f(void) +{ + return 0x2; +} +static inline u32 fb_mmu_debug_rd_aperture_sys_mem_ncoh_f(void) +{ + return 0x3; +} +static inline u32 fb_mmu_debug_rd_vol_false_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_debug_rd_addr_f(u32 v) +{ + return (v & 0xfffffff) << 4; +} +static inline u32 fb_mmu_debug_rd_addr_alignment_v(void) +{ + return 0x0000000c; +} +static inline u32 fb_mmu_debug_ctrl_r(void) +{ + return 0x00100cc4; +} +static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r) +{ + return (r >> 16) & 0x1; +} +static inline u32 fb_mmu_debug_ctrl_debug_m(void) +{ + return 0x1 << 16; +} +static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void) +{ + return 0x00000000; +} +static inline u32 fb_mmu_vpr_info_r(void) +{ + return 0x00100cd0; +} +static inline u32 fb_mmu_vpr_info_fetch_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 fb_mmu_vpr_info_fetch_false_v(void) +{ + return 0x00000000; +} +static inline u32 fb_mmu_vpr_info_fetch_true_v(void) +{ + return 0x00000001; +} +static inline u32 fb_niso_flush_sysmem_addr_r(void) +{ + return 0x00100c10; +} +static inline u32 fb_niso_intr_r(void) +{ + return 0x00100a20; +} +static inline u32 fb_niso_intr_hub_access_counter_notify_m(void) +{ + return 0x1 << 0; +} +static inline u32 fb_niso_intr_hub_access_counter_notify_pending_f(void) +{ + return 0x1; +} +static inline u32 fb_niso_intr_hub_access_counter_error_m(void) +{ + return 0x1 << 1; +} +static inline u32 fb_niso_intr_hub_access_counter_error_pending_f(void) +{ + return 0x2; +} +static inline u32 fb_niso_intr_mmu_replayable_fault_notify_m(void) +{ + return 0x1 << 27; +} +static inline u32 fb_niso_intr_mmu_replayable_fault_notify_pending_f(void) +{ + return 0x8000000; +} +static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_m(void) +{ + return 0x1 << 28; +} +static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_pending_f(void) +{ + return 0x10000000; +} +static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_m(void) +{ + return 0x1 << 29; +} +static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_pending_f(void) +{ + return 0x20000000; +} +static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_m(void) +{ + return 0x1 << 30; +} +static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_pending_f(void) +{ + return 0x40000000; +} +static inline u32 fb_niso_intr_mmu_other_fault_notify_m(void) +{ + return 0x1 << 31; +} +static inline u32 fb_niso_intr_mmu_other_fault_notify_pending_f(void) +{ + return 0x80000000; +} +static inline u32 fb_niso_intr_en_r(u32 i) +{ + return 0x00100a24 + i*4; +} +static inline u32 fb_niso_intr_en__size_1_v(void) +{ + return 0x00000002; +} +static inline u32 fb_niso_intr_en_hub_access_counter_notify_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 fb_niso_intr_en_hub_access_counter_notify_enabled_f(void) +{ + return 0x1; +} +static inline u32 fb_niso_intr_en_hub_access_counter_error_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 fb_niso_intr_en_hub_access_counter_error_enabled_f(void) +{ + return 0x2; +} +static inline u32 fb_niso_intr_en_mmu_replayable_fault_notify_f(u32 v) +{ + return (v & 0x1) << 27; +} +static inline u32 fb_niso_intr_en_mmu_replayable_fault_notify_enabled_f(void) +{ + return 0x8000000; +} +static inline u32 fb_niso_intr_en_mmu_replayable_fault_overflow_f(u32 v) +{ + return (v & 0x1) << 28; +} +static inline u32 fb_niso_intr_en_mmu_replayable_fault_overflow_enabled_f(void) +{ + return 0x10000000; +} +static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_notify_f(u32 v) +{ + return (v & 0x1) << 29; +} +static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_notify_enabled_f(void) +{ + return 0x20000000; +} +static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_overflow_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_overflow_enabled_f(void) +{ + return 0x40000000; +} +static inline u32 fb_niso_intr_en_mmu_other_fault_notify_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 fb_niso_intr_en_mmu_other_fault_notify_enabled_f(void) +{ + return 0x80000000; +} +static inline u32 fb_niso_intr_en_set_r(u32 i) +{ + return 0x00100a2c + i*4; +} +static inline u32 fb_niso_intr_en_set__size_1_v(void) +{ + return 0x00000002; +} +static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_m(void) +{ + return 0x1 << 0; +} +static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_set_f(void) +{ + return 0x1; +} +static inline u32 fb_niso_intr_en_set_hub_access_counter_error_m(void) +{ + return 0x1 << 1; +} +static inline u32 fb_niso_intr_en_set_hub_access_counter_error_set_f(void) +{ + return 0x2; +} +static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_m(void) +{ + return 0x1 << 27; +} +static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_set_f(void) +{ + return 0x8000000; +} +static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_m(void) +{ + return 0x1 << 28; +} +static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_set_f(void) +{ + return 0x10000000; +} +static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_m(void) +{ + return 0x1 << 29; +} +static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_set_f(void) +{ + return 0x20000000; +} +static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_m(void) +{ + return 0x1 << 30; +} +static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_set_f(void) +{ + return 0x40000000; +} +static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_m(void) +{ + return 0x1 << 31; +} +static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_set_f(void) +{ + return 0x80000000; +} +static inline u32 fb_niso_intr_en_clr_r(u32 i) +{ + return 0x00100a34 + i*4; +} +static inline u32 fb_niso_intr_en_clr__size_1_v(void) +{ + return 0x00000002; +} +static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_m(void) +{ + return 0x1 << 0; +} +static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_set_f(void) +{ + return 0x1; +} +static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_m(void) +{ + return 0x1 << 1; +} +static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_set_f(void) +{ + return 0x2; +} +static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_m(void) +{ + return 0x1 << 27; +} +static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_set_f(void) +{ + return 0x8000000; +} +static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_m(void) +{ + return 0x1 << 28; +} +static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_set_f(void) +{ + return 0x10000000; +} +static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_m(void) +{ + return 0x1 << 29; +} +static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_set_f(void) +{ + return 0x20000000; +} +static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_m(void) +{ + return 0x1 << 30; +} +static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_set_f(void) +{ + return 0x40000000; +} +static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_m(void) +{ + return 0x1 << 31; +} +static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_set_f(void) +{ + return 0x80000000; +} +static inline u32 fb_niso_intr_en_clr_mmu_non_replay_fault_buffer_v(void) +{ + return 0x00000000; +} +static inline u32 fb_niso_intr_en_clr_mmu_replay_fault_buffer_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_lo_r(u32 i) +{ + return 0x00100e24 + i*20; +} +static inline u32 fb_mmu_fault_buffer_lo__size_1_v(void) +{ + return 0x00000002; +} +static inline u32 fb_mmu_fault_buffer_lo_addr_mode_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 fb_mmu_fault_buffer_lo_addr_mode_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 fb_mmu_fault_buffer_lo_addr_mode_virtual_v(void) +{ + return 0x00000000; +} +static inline u32 fb_mmu_fault_buffer_lo_addr_mode_virtual_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_fault_buffer_lo_addr_mode_physical_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_lo_addr_mode_physical_f(void) +{ + return 0x1; +} +static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_f(u32 v) +{ + return (v & 0x3) << 1; +} +static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_v(u32 r) +{ + return (r >> 1) & 0x3; +} +static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_coh_v(void) +{ + return 0x00000002; +} +static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_coh_f(void) +{ + return 0x4; +} +static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_nocoh_v(void) +{ + return 0x00000003; +} +static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_nocoh_f(void) +{ + return 0x6; +} +static inline u32 fb_mmu_fault_buffer_lo_phys_vol_f(u32 v) +{ + return (v & 0x1) << 3; +} +static inline u32 fb_mmu_fault_buffer_lo_phys_vol_v(u32 r) +{ + return (r >> 3) & 0x1; +} +static inline u32 fb_mmu_fault_buffer_lo_addr_f(u32 v) +{ + return (v & 0xfffff) << 12; +} +static inline u32 fb_mmu_fault_buffer_lo_addr_v(u32 r) +{ + return (r >> 12) & 0xfffff; +} +static inline u32 fb_mmu_fault_buffer_hi_r(u32 i) +{ + return 0x00100e28 + i*20; +} +static inline u32 fb_mmu_fault_buffer_hi__size_1_v(void) +{ + return 0x00000002; +} +static inline u32 fb_mmu_fault_buffer_hi_addr_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 fb_mmu_fault_buffer_hi_addr_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 fb_mmu_fault_buffer_get_r(u32 i) +{ + return 0x00100e2c + i*20; +} +static inline u32 fb_mmu_fault_buffer_get__size_1_v(void) +{ + return 0x00000002; +} +static inline u32 fb_mmu_fault_buffer_get_ptr_f(u32 v) +{ + return (v & 0xfffff) << 0; +} +static inline u32 fb_mmu_fault_buffer_get_ptr_m(void) +{ + return 0xfffff << 0; +} +static inline u32 fb_mmu_fault_buffer_get_ptr_v(u32 r) +{ + return (r >> 0) & 0xfffff; +} +static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_m(void) +{ + return 0x1 << 30; +} +static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_clear_f(void) +{ + return 0x40000000; +} +static inline u32 fb_mmu_fault_buffer_get_overflow_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 fb_mmu_fault_buffer_get_overflow_m(void) +{ + return 0x1 << 31; +} +static inline u32 fb_mmu_fault_buffer_get_overflow_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_get_overflow_clear_f(void) +{ + return 0x80000000; +} +static inline u32 fb_mmu_fault_buffer_put_r(u32 i) +{ + return 0x00100e30 + i*20; +} +static inline u32 fb_mmu_fault_buffer_put__size_1_v(void) +{ + return 0x00000002; +} +static inline u32 fb_mmu_fault_buffer_put_ptr_f(u32 v) +{ + return (v & 0xfffff) << 0; +} +static inline u32 fb_mmu_fault_buffer_put_ptr_v(u32 r) +{ + return (r >> 0) & 0xfffff; +} +static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_yes_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_yes_f(void) +{ + return 0x40000000; +} +static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_no_v(void) +{ + return 0x00000000; +} +static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_no_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_fault_buffer_put_overflow_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 fb_mmu_fault_buffer_put_overflow_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 fb_mmu_fault_buffer_put_overflow_yes_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_put_overflow_yes_f(void) +{ + return 0x80000000; +} +static inline u32 fb_mmu_fault_buffer_size_r(u32 i) +{ + return 0x00100e34 + i*20; +} +static inline u32 fb_mmu_fault_buffer_size__size_1_v(void) +{ + return 0x00000002; +} +static inline u32 fb_mmu_fault_buffer_size_val_f(u32 v) +{ + return (v & 0xfffff) << 0; +} +static inline u32 fb_mmu_fault_buffer_size_val_v(u32 r) +{ + return (r >> 0) & 0xfffff; +} +static inline u32 fb_mmu_fault_buffer_size_overflow_intr_f(u32 v) +{ + return (v & 0x1) << 29; +} +static inline u32 fb_mmu_fault_buffer_size_overflow_intr_v(u32 r) +{ + return (r >> 29) & 0x1; +} +static inline u32 fb_mmu_fault_buffer_size_overflow_intr_enable_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_size_overflow_intr_enable_f(void) +{ + return 0x20000000; +} +static inline u32 fb_mmu_fault_buffer_size_set_default_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 fb_mmu_fault_buffer_size_set_default_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 fb_mmu_fault_buffer_size_set_default_yes_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_size_set_default_yes_f(void) +{ + return 0x40000000; +} +static inline u32 fb_mmu_fault_buffer_size_enable_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 fb_mmu_fault_buffer_size_enable_m(void) +{ + return 0x1 << 31; +} +static inline u32 fb_mmu_fault_buffer_size_enable_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 fb_mmu_fault_buffer_size_enable_true_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_size_enable_true_f(void) +{ + return 0x80000000; +} +static inline u32 fb_mmu_fault_addr_lo_r(void) +{ + return 0x00100e4c; +} +static inline u32 fb_mmu_fault_addr_lo_phys_aperture_f(u32 v) +{ + return (v & 0x3) << 0; +} +static inline u32 fb_mmu_fault_addr_lo_phys_aperture_v(u32 r) +{ + return (r >> 0) & 0x3; +} +static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_coh_v(void) +{ + return 0x00000002; +} +static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_coh_f(void) +{ + return 0x2; +} +static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_nocoh_v(void) +{ + return 0x00000003; +} +static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_nocoh_f(void) +{ + return 0x3; +} +static inline u32 fb_mmu_fault_addr_lo_addr_f(u32 v) +{ + return (v & 0xfffff) << 12; +} +static inline u32 fb_mmu_fault_addr_lo_addr_v(u32 r) +{ + return (r >> 12) & 0xfffff; +} +static inline u32 fb_mmu_fault_addr_hi_r(void) +{ + return 0x00100e50; +} +static inline u32 fb_mmu_fault_addr_hi_addr_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 fb_mmu_fault_addr_hi_addr_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 fb_mmu_fault_inst_lo_r(void) +{ + return 0x00100e54; +} +static inline u32 fb_mmu_fault_inst_lo_engine_id_v(u32 r) +{ + return (r >> 0) & 0x1ff; +} +static inline u32 fb_mmu_fault_inst_lo_aperture_v(u32 r) +{ + return (r >> 10) & 0x3; +} +static inline u32 fb_mmu_fault_inst_lo_aperture_sys_coh_v(void) +{ + return 0x00000002; +} +static inline u32 fb_mmu_fault_inst_lo_aperture_sys_nocoh_v(void) +{ + return 0x00000003; +} +static inline u32 fb_mmu_fault_inst_lo_addr_f(u32 v) +{ + return (v & 0xfffff) << 12; +} +static inline u32 fb_mmu_fault_inst_lo_addr_v(u32 r) +{ + return (r >> 12) & 0xfffff; +} +static inline u32 fb_mmu_fault_inst_hi_r(void) +{ + return 0x00100e58; +} +static inline u32 fb_mmu_fault_inst_hi_addr_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 fb_mmu_fault_info_r(void) +{ + return 0x00100e5c; +} +static inline u32 fb_mmu_fault_info_fault_type_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 fb_mmu_fault_info_replayable_fault_v(u32 r) +{ + return (r >> 7) & 0x1; +} +static inline u32 fb_mmu_fault_info_client_v(u32 r) +{ + return (r >> 8) & 0x7f; +} +static inline u32 fb_mmu_fault_info_access_type_v(u32 r) +{ + return (r >> 16) & 0xf; +} +static inline u32 fb_mmu_fault_info_client_type_v(u32 r) +{ + return (r >> 20) & 0x1; +} +static inline u32 fb_mmu_fault_info_gpc_id_v(u32 r) +{ + return (r >> 24) & 0x1f; +} +static inline u32 fb_mmu_fault_info_protected_mode_v(u32 r) +{ + return (r >> 29) & 0x1; +} +static inline u32 fb_mmu_fault_info_replayable_fault_en_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 fb_mmu_fault_info_valid_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 fb_mmu_fault_status_r(void) +{ + return 0x00100e60; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_phys_m(void) +{ + return 0x1 << 0; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_phys_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_phys_set_f(void) +{ + return 0x1; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_phys_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_phys_clear_f(void) +{ + return 0x1; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_virt_m(void) +{ + return 0x1 << 1; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_virt_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_virt_set_f(void) +{ + return 0x2; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_virt_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_virt_clear_f(void) +{ + return 0x2; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_phys_m(void) +{ + return 0x1 << 2; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_phys_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_phys_set_f(void) +{ + return 0x4; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_phys_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_phys_clear_f(void) +{ + return 0x4; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_virt_m(void) +{ + return 0x1 << 3; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_virt_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_virt_set_f(void) +{ + return 0x8; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_virt_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_virt_clear_f(void) +{ + return 0x8; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_phys_m(void) +{ + return 0x1 << 4; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_phys_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_phys_set_f(void) +{ + return 0x10; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_phys_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_phys_clear_f(void) +{ + return 0x10; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_virt_m(void) +{ + return 0x1 << 5; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_virt_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_virt_set_f(void) +{ + return 0x20; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_virt_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_virt_clear_f(void) +{ + return 0x20; +} +static inline u32 fb_mmu_fault_status_dropped_other_phys_m(void) +{ + return 0x1 << 6; +} +static inline u32 fb_mmu_fault_status_dropped_other_phys_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_other_phys_set_f(void) +{ + return 0x40; +} +static inline u32 fb_mmu_fault_status_dropped_other_phys_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_other_phys_clear_f(void) +{ + return 0x40; +} +static inline u32 fb_mmu_fault_status_dropped_other_virt_m(void) +{ + return 0x1 << 7; +} +static inline u32 fb_mmu_fault_status_dropped_other_virt_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_other_virt_set_f(void) +{ + return 0x80; +} +static inline u32 fb_mmu_fault_status_dropped_other_virt_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_other_virt_clear_f(void) +{ + return 0x80; +} +static inline u32 fb_mmu_fault_status_replayable_m(void) +{ + return 0x1 << 8; +} +static inline u32 fb_mmu_fault_status_replayable_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_replayable_set_f(void) +{ + return 0x100; +} +static inline u32 fb_mmu_fault_status_replayable_reset_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_fault_status_non_replayable_m(void) +{ + return 0x1 << 9; +} +static inline u32 fb_mmu_fault_status_non_replayable_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_non_replayable_set_f(void) +{ + return 0x200; +} +static inline u32 fb_mmu_fault_status_non_replayable_reset_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_fault_status_replayable_error_m(void) +{ + return 0x1 << 10; +} +static inline u32 fb_mmu_fault_status_replayable_error_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_replayable_error_set_f(void) +{ + return 0x400; +} +static inline u32 fb_mmu_fault_status_replayable_error_reset_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_fault_status_non_replayable_error_m(void) +{ + return 0x1 << 11; +} +static inline u32 fb_mmu_fault_status_non_replayable_error_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_non_replayable_error_set_f(void) +{ + return 0x800; +} +static inline u32 fb_mmu_fault_status_non_replayable_error_reset_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_fault_status_replayable_overflow_m(void) +{ + return 0x1 << 12; +} +static inline u32 fb_mmu_fault_status_replayable_overflow_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_replayable_overflow_set_f(void) +{ + return 0x1000; +} +static inline u32 fb_mmu_fault_status_replayable_overflow_reset_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_fault_status_non_replayable_overflow_m(void) +{ + return 0x1 << 13; +} +static inline u32 fb_mmu_fault_status_non_replayable_overflow_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_non_replayable_overflow_set_f(void) +{ + return 0x2000; +} +static inline u32 fb_mmu_fault_status_non_replayable_overflow_reset_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_m(void) +{ + return 0x1 << 14; +} +static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_set_f(void) +{ + return 0x4000; +} +static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_m(void) +{ + return 0x1 << 15; +} +static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_set_f(void) +{ + return 0x8000; +} +static inline u32 fb_mmu_fault_status_busy_m(void) +{ + return 0x1 << 30; +} +static inline u32 fb_mmu_fault_status_busy_true_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_busy_true_f(void) +{ + return 0x40000000; +} +static inline u32 fb_mmu_fault_status_valid_m(void) +{ + return 0x1 << 31; +} +static inline u32 fb_mmu_fault_status_valid_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_valid_set_f(void) +{ + return 0x80000000; +} +static inline u32 fb_mmu_fault_status_valid_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_valid_clear_f(void) +{ + return 0x80000000; +} +static inline u32 fb_mmu_local_memory_range_r(void) +{ + return 0x00100ce0; +} +static inline u32 fb_mmu_local_memory_range_lower_scale_v(u32 r) +{ + return (r >> 0) & 0xf; +} +static inline u32 fb_mmu_local_memory_range_lower_mag_v(u32 r) +{ + return (r >> 4) & 0x3f; +} +static inline u32 fb_mmu_local_memory_range_ecc_mode_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 fb_niso_scrub_status_r(void) +{ + return 0x00100b20; +} +static inline u32 fb_niso_scrub_status_flag_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 fb_mmu_priv_level_mask_r(void) +{ + return 0x00100cdc; +} +static inline u32 fb_mmu_priv_level_mask_write_violation_m(void) +{ + return 0x1 << 7; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fifo_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fifo_gv100.h new file mode 100644 index 00000000..9466a695 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fifo_gv100.h @@ -0,0 +1,545 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_fifo_gv100_h_ +#define _hw_fifo_gv100_h_ + +static inline u32 fifo_bar1_base_r(void) +{ + return 0x00002254; +} +static inline u32 fifo_bar1_base_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 fifo_bar1_base_ptr_align_shift_v(void) +{ + return 0x0000000c; +} +static inline u32 fifo_bar1_base_valid_false_f(void) +{ + return 0x0; +} +static inline u32 fifo_bar1_base_valid_true_f(void) +{ + return 0x10000000; +} +static inline u32 fifo_userd_writeback_r(void) +{ + return 0x0000225c; +} +static inline u32 fifo_userd_writeback_timer_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 fifo_userd_writeback_timer_disabled_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_userd_writeback_timer_shorter_v(void) +{ + return 0x00000003; +} +static inline u32 fifo_userd_writeback_timer_100us_v(void) +{ + return 0x00000064; +} +static inline u32 fifo_userd_writeback_timescale_f(u32 v) +{ + return (v & 0xf) << 12; +} +static inline u32 fifo_userd_writeback_timescale_0_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_runlist_base_r(void) +{ + return 0x00002270; +} +static inline u32 fifo_runlist_base_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 fifo_runlist_base_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 fifo_runlist_base_target_sys_mem_coh_f(void) +{ + return 0x20000000; +} +static inline u32 fifo_runlist_base_target_sys_mem_ncoh_f(void) +{ + return 0x30000000; +} +static inline u32 fifo_runlist_r(void) +{ + return 0x00002274; +} +static inline u32 fifo_runlist_engine_f(u32 v) +{ + return (v & 0xf) << 20; +} +static inline u32 fifo_eng_runlist_base_r(u32 i) +{ + return 0x00002280 + i*8; +} +static inline u32 fifo_eng_runlist_base__size_1_v(void) +{ + return 0x0000000d; +} +static inline u32 fifo_eng_runlist_r(u32 i) +{ + return 0x00002284 + i*8; +} +static inline u32 fifo_eng_runlist__size_1_v(void) +{ + return 0x0000000d; +} +static inline u32 fifo_eng_runlist_length_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 fifo_eng_runlist_length_max_v(void) +{ + return 0x0000ffff; +} +static inline u32 fifo_eng_runlist_pending_true_f(void) +{ + return 0x100000; +} +static inline u32 fifo_pb_timeslice_r(u32 i) +{ + return 0x00002350 + i*4; +} +static inline u32 fifo_pb_timeslice_timeout_16_f(void) +{ + return 0x10; +} +static inline u32 fifo_pb_timeslice_timescale_0_f(void) +{ + return 0x0; +} +static inline u32 fifo_pb_timeslice_enable_true_f(void) +{ + return 0x10000000; +} +static inline u32 fifo_pbdma_map_r(u32 i) +{ + return 0x00002390 + i*4; +} +static inline u32 fifo_intr_0_r(void) +{ + return 0x00002100; +} +static inline u32 fifo_intr_0_bind_error_pending_f(void) +{ + return 0x1; +} +static inline u32 fifo_intr_0_bind_error_reset_f(void) +{ + return 0x1; +} +static inline u32 fifo_intr_0_sched_error_pending_f(void) +{ + return 0x100; +} +static inline u32 fifo_intr_0_sched_error_reset_f(void) +{ + return 0x100; +} +static inline u32 fifo_intr_0_chsw_error_pending_f(void) +{ + return 0x10000; +} +static inline u32 fifo_intr_0_chsw_error_reset_f(void) +{ + return 0x10000; +} +static inline u32 fifo_intr_0_fb_flush_timeout_pending_f(void) +{ + return 0x800000; +} +static inline u32 fifo_intr_0_fb_flush_timeout_reset_f(void) +{ + return 0x800000; +} +static inline u32 fifo_intr_0_lb_error_pending_f(void) +{ + return 0x1000000; +} +static inline u32 fifo_intr_0_lb_error_reset_f(void) +{ + return 0x1000000; +} +static inline u32 fifo_intr_0_pbdma_intr_pending_f(void) +{ + return 0x20000000; +} +static inline u32 fifo_intr_0_runlist_event_pending_f(void) +{ + return 0x40000000; +} +static inline u32 fifo_intr_0_channel_intr_pending_f(void) +{ + return 0x80000000; +} +static inline u32 fifo_intr_en_0_r(void) +{ + return 0x00002140; +} +static inline u32 fifo_intr_en_0_sched_error_f(u32 v) +{ + return (v & 0x1) << 8; +} +static inline u32 fifo_intr_en_0_sched_error_m(void) +{ + return 0x1 << 8; +} +static inline u32 fifo_intr_en_1_r(void) +{ + return 0x00002528; +} +static inline u32 fifo_intr_bind_error_r(void) +{ + return 0x0000252c; +} +static inline u32 fifo_intr_sched_error_r(void) +{ + return 0x0000254c; +} +static inline u32 fifo_intr_sched_error_code_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 fifo_intr_chsw_error_r(void) +{ + return 0x0000256c; +} +static inline u32 fifo_intr_pbdma_id_r(void) +{ + return 0x000025a0; +} +static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i) +{ + return (v & 0x1) << (0 + i*1); +} +static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i) +{ + return (r >> (0 + i*1)) & 0x1; +} +static inline u32 fifo_intr_pbdma_id_status__size_1_v(void) +{ + return 0x0000000e; +} +static inline u32 fifo_intr_runlist_r(void) +{ + return 0x00002a00; +} +static inline u32 fifo_fb_timeout_r(void) +{ + return 0x00002a04; +} +static inline u32 fifo_fb_timeout_period_m(void) +{ + return 0x3fffffff << 0; +} +static inline u32 fifo_fb_timeout_period_max_f(void) +{ + return 0x3fffffff; +} +static inline u32 fifo_fb_timeout_period_init_f(void) +{ + return 0x3c00; +} +static inline u32 fifo_sched_disable_r(void) +{ + return 0x00002630; +} +static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i) +{ + return (v & 0x1) << (0 + i*1); +} +static inline u32 fifo_sched_disable_runlist_m(u32 i) +{ + return 0x1 << (0 + i*1); +} +static inline u32 fifo_sched_disable_true_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_runlist_preempt_r(void) +{ + return 0x00002638; +} +static inline u32 fifo_runlist_preempt_runlist_f(u32 v, u32 i) +{ + return (v & 0x1) << (0 + i*1); +} +static inline u32 fifo_runlist_preempt_runlist_m(u32 i) +{ + return 0x1 << (0 + i*1); +} +static inline u32 fifo_runlist_preempt_runlist_pending_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_preempt_r(void) +{ + return 0x00002634; +} +static inline u32 fifo_preempt_pending_true_f(void) +{ + return 0x100000; +} +static inline u32 fifo_preempt_type_channel_f(void) +{ + return 0x0; +} +static inline u32 fifo_preempt_type_tsg_f(void) +{ + return 0x1000000; +} +static inline u32 fifo_preempt_chid_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 fifo_preempt_id_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 fifo_engine_status_r(u32 i) +{ + return 0x00002640 + i*8; +} +static inline u32 fifo_engine_status__size_1_v(void) +{ + return 0x0000000f; +} +static inline u32 fifo_engine_status_id_v(u32 r) +{ + return (r >> 0) & 0xfff; +} +static inline u32 fifo_engine_status_id_type_v(u32 r) +{ + return (r >> 12) & 0x1; +} +static inline u32 fifo_engine_status_id_type_chid_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_engine_status_id_type_tsgid_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_engine_status_ctx_status_v(u32 r) +{ + return (r >> 13) & 0x7; +} +static inline u32 fifo_engine_status_ctx_status_valid_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_engine_status_ctx_status_ctxsw_load_v(void) +{ + return 0x00000005; +} +static inline u32 fifo_engine_status_ctx_status_ctxsw_save_v(void) +{ + return 0x00000006; +} +static inline u32 fifo_engine_status_ctx_status_ctxsw_switch_v(void) +{ + return 0x00000007; +} +static inline u32 fifo_engine_status_next_id_v(u32 r) +{ + return (r >> 16) & 0xfff; +} +static inline u32 fifo_engine_status_next_id_type_v(u32 r) +{ + return (r >> 28) & 0x1; +} +static inline u32 fifo_engine_status_next_id_type_chid_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_engine_status_eng_reload_v(u32 r) +{ + return (r >> 29) & 0x1; +} +static inline u32 fifo_engine_status_faulted_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 fifo_engine_status_faulted_true_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_engine_status_engine_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 fifo_engine_status_engine_idle_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_engine_status_engine_busy_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_engine_status_ctxsw_v(u32 r) +{ + return (r >> 15) & 0x1; +} +static inline u32 fifo_engine_status_ctxsw_in_progress_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_engine_status_ctxsw_in_progress_f(void) +{ + return 0x8000; +} +static inline u32 fifo_pbdma_status_r(u32 i) +{ + return 0x00003080 + i*4; +} +static inline u32 fifo_pbdma_status__size_1_v(void) +{ + return 0x0000000e; +} +static inline u32 fifo_pbdma_status_id_v(u32 r) +{ + return (r >> 0) & 0xfff; +} +static inline u32 fifo_pbdma_status_id_type_v(u32 r) +{ + return (r >> 12) & 0x1; +} +static inline u32 fifo_pbdma_status_id_type_chid_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_pbdma_status_id_type_tsgid_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_pbdma_status_chan_status_v(u32 r) +{ + return (r >> 13) & 0x7; +} +static inline u32 fifo_pbdma_status_chan_status_valid_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_pbdma_status_chan_status_chsw_load_v(void) +{ + return 0x00000005; +} +static inline u32 fifo_pbdma_status_chan_status_chsw_save_v(void) +{ + return 0x00000006; +} +static inline u32 fifo_pbdma_status_chan_status_chsw_switch_v(void) +{ + return 0x00000007; +} +static inline u32 fifo_pbdma_status_next_id_v(u32 r) +{ + return (r >> 16) & 0xfff; +} +static inline u32 fifo_pbdma_status_next_id_type_v(u32 r) +{ + return (r >> 28) & 0x1; +} +static inline u32 fifo_pbdma_status_next_id_type_chid_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_pbdma_status_chsw_v(u32 r) +{ + return (r >> 15) & 0x1; +} +static inline u32 fifo_pbdma_status_chsw_in_progress_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_cfg0_r(void) +{ + return 0x00002004; +} +static inline u32 fifo_cfg0_num_pbdma_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 fifo_cfg0_pbdma_fault_id_v(u32 r) +{ + return (r >> 16) & 0xff; +} +static inline u32 fifo_fb_iface_r(void) +{ + return 0x000026f0; +} +static inline u32 fifo_fb_iface_control_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 fifo_fb_iface_control_enable_f(void) +{ + return 0x1; +} +static inline u32 fifo_fb_iface_status_v(u32 r) +{ + return (r >> 4) & 0x1; +} +static inline u32 fifo_fb_iface_status_enabled_f(void) +{ + return 0x10; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_flush_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_flush_gv100.h new file mode 100644 index 00000000..c9b592bf --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_flush_gv100.h @@ -0,0 +1,181 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_flush_gv100_h_ +#define _hw_flush_gv100_h_ + +static inline u32 flush_l2_system_invalidate_r(void) +{ + return 0x00070004; +} +static inline u32 flush_l2_system_invalidate_pending_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 flush_l2_system_invalidate_pending_busy_v(void) +{ + return 0x00000001; +} +static inline u32 flush_l2_system_invalidate_pending_busy_f(void) +{ + return 0x1; +} +static inline u32 flush_l2_system_invalidate_outstanding_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 flush_l2_system_invalidate_outstanding_true_v(void) +{ + return 0x00000001; +} +static inline u32 flush_l2_flush_dirty_r(void) +{ + return 0x00070010; +} +static inline u32 flush_l2_flush_dirty_pending_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 flush_l2_flush_dirty_pending_empty_v(void) +{ + return 0x00000000; +} +static inline u32 flush_l2_flush_dirty_pending_empty_f(void) +{ + return 0x0; +} +static inline u32 flush_l2_flush_dirty_pending_busy_v(void) +{ + return 0x00000001; +} +static inline u32 flush_l2_flush_dirty_pending_busy_f(void) +{ + return 0x1; +} +static inline u32 flush_l2_flush_dirty_outstanding_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 flush_l2_flush_dirty_outstanding_false_v(void) +{ + return 0x00000000; +} +static inline u32 flush_l2_flush_dirty_outstanding_false_f(void) +{ + return 0x0; +} +static inline u32 flush_l2_flush_dirty_outstanding_true_v(void) +{ + return 0x00000001; +} +static inline u32 flush_l2_clean_comptags_r(void) +{ + return 0x0007000c; +} +static inline u32 flush_l2_clean_comptags_pending_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 flush_l2_clean_comptags_pending_empty_v(void) +{ + return 0x00000000; +} +static inline u32 flush_l2_clean_comptags_pending_empty_f(void) +{ + return 0x0; +} +static inline u32 flush_l2_clean_comptags_pending_busy_v(void) +{ + return 0x00000001; +} +static inline u32 flush_l2_clean_comptags_pending_busy_f(void) +{ + return 0x1; +} +static inline u32 flush_l2_clean_comptags_outstanding_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 flush_l2_clean_comptags_outstanding_false_v(void) +{ + return 0x00000000; +} +static inline u32 flush_l2_clean_comptags_outstanding_false_f(void) +{ + return 0x0; +} +static inline u32 flush_l2_clean_comptags_outstanding_true_v(void) +{ + return 0x00000001; +} +static inline u32 flush_fb_flush_r(void) +{ + return 0x00070000; +} +static inline u32 flush_fb_flush_pending_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 flush_fb_flush_pending_busy_v(void) +{ + return 0x00000001; +} +static inline u32 flush_fb_flush_pending_busy_f(void) +{ + return 0x1; +} +static inline u32 flush_fb_flush_outstanding_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 flush_fb_flush_outstanding_true_v(void) +{ + return 0x00000001; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h new file mode 100644 index 00000000..b2b52ff2 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_fuse_gv100_h_ +#define _hw_fuse_gv100_h_ + +static inline u32 fuse_status_opt_tpc_gpc_r(u32 i) +{ + return 0x00021c38 + i*4; +} +static inline u32 fuse_ctrl_opt_tpc_gpc_r(u32 i) +{ + return 0x00021838 + i*4; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_r(void) +{ + return 0x00021944; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_m(void) +{ + return 0xff << 0; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_r(void) +{ + return 0x00021948; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_m(void) +{ + return 0x1 << 0; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f(void) +{ + return 0x1; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_no_f(void) +{ + return 0x0; +} +static inline u32 fuse_status_opt_fbio_r(void) +{ + return 0x00021c14; +} +static inline u32 fuse_status_opt_fbio_data_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 fuse_status_opt_fbio_data_m(void) +{ + return 0xffff << 0; +} +static inline u32 fuse_status_opt_fbio_data_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 fuse_status_opt_rop_l2_fbp_r(u32 i) +{ + return 0x00021d70 + i*4; +} +static inline u32 fuse_status_opt_fbp_r(void) +{ + return 0x00021d38; +} +static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i) +{ + return (r >> (0 + i*1)) & 0x1; +} +static inline u32 fuse_opt_ecc_en_r(void) +{ + return 0x00021228; +} +static inline u32 fuse_opt_feature_fuses_override_disable_r(void) +{ + return 0x000213f0; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gmmu_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gmmu_gv100.h new file mode 100644 index 00000000..15bdde6c --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gmmu_gv100.h @@ -0,0 +1,1281 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_gmmu_gv100_h_ +#define _hw_gmmu_gv100_h_ + +static inline u32 gmmu_new_pde_is_pte_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pde_is_pte_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_pde_aperture_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pde_aperture_invalid_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_pde_aperture_video_memory_f(void) +{ + return 0x2; +} +static inline u32 gmmu_new_pde_aperture_sys_mem_coh_f(void) +{ + return 0x4; +} +static inline u32 gmmu_new_pde_aperture_sys_mem_ncoh_f(void) +{ + return 0x6; +} +static inline u32 gmmu_new_pde_address_sys_f(u32 v) +{ + return (v & 0xffffff) << 8; +} +static inline u32 gmmu_new_pde_address_sys_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pde_vol_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pde_vol_true_f(void) +{ + return 0x8; +} +static inline u32 gmmu_new_pde_vol_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_pde_address_shift_v(void) +{ + return 0x0000000c; +} +static inline u32 gmmu_new_pde__size_v(void) +{ + return 0x00000008; +} +static inline u32 gmmu_new_dual_pde_is_pte_w(void) +{ + return 0; +} +static inline u32 gmmu_new_dual_pde_is_pte_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_dual_pde_aperture_big_w(void) +{ + return 0; +} +static inline u32 gmmu_new_dual_pde_aperture_big_invalid_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_dual_pde_aperture_big_video_memory_f(void) +{ + return 0x2; +} +static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_coh_f(void) +{ + return 0x4; +} +static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f(void) +{ + return 0x6; +} +static inline u32 gmmu_new_dual_pde_address_big_sys_f(u32 v) +{ + return (v & 0xfffffff) << 4; +} +static inline u32 gmmu_new_dual_pde_address_big_sys_w(void) +{ + return 0; +} +static inline u32 gmmu_new_dual_pde_aperture_small_w(void) +{ + return 2; +} +static inline u32 gmmu_new_dual_pde_aperture_small_invalid_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_dual_pde_aperture_small_video_memory_f(void) +{ + return 0x2; +} +static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_coh_f(void) +{ + return 0x4; +} +static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f(void) +{ + return 0x6; +} +static inline u32 gmmu_new_dual_pde_vol_small_w(void) +{ + return 2; +} +static inline u32 gmmu_new_dual_pde_vol_small_true_f(void) +{ + return 0x8; +} +static inline u32 gmmu_new_dual_pde_vol_small_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_dual_pde_vol_big_w(void) +{ + return 0; +} +static inline u32 gmmu_new_dual_pde_vol_big_true_f(void) +{ + return 0x8; +} +static inline u32 gmmu_new_dual_pde_vol_big_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_dual_pde_address_small_sys_f(u32 v) +{ + return (v & 0xffffff) << 8; +} +static inline u32 gmmu_new_dual_pde_address_small_sys_w(void) +{ + return 2; +} +static inline u32 gmmu_new_dual_pde_address_shift_v(void) +{ + return 0x0000000c; +} +static inline u32 gmmu_new_dual_pde_address_big_shift_v(void) +{ + return 0x00000008; +} +static inline u32 gmmu_new_dual_pde__size_v(void) +{ + return 0x00000010; +} +static inline u32 gmmu_new_pte__size_v(void) +{ + return 0x00000008; +} +static inline u32 gmmu_new_pte_valid_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pte_valid_true_f(void) +{ + return 0x1; +} +static inline u32 gmmu_new_pte_valid_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_pte_privilege_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pte_privilege_true_f(void) +{ + return 0x20; +} +static inline u32 gmmu_new_pte_privilege_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_pte_address_sys_f(u32 v) +{ + return (v & 0xffffff) << 8; +} +static inline u32 gmmu_new_pte_address_sys_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pte_address_vid_f(u32 v) +{ + return (v & 0xffffff) << 8; +} +static inline u32 gmmu_new_pte_address_vid_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pte_vol_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pte_vol_true_f(void) +{ + return 0x8; +} +static inline u32 gmmu_new_pte_vol_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_pte_aperture_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pte_aperture_video_memory_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_pte_aperture_sys_mem_coh_f(void) +{ + return 0x4; +} +static inline u32 gmmu_new_pte_aperture_sys_mem_ncoh_f(void) +{ + return 0x6; +} +static inline u32 gmmu_new_pte_read_only_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pte_read_only_true_f(void) +{ + return 0x40; +} +static inline u32 gmmu_new_pte_comptagline_f(u32 v) +{ + return (v & 0x3ffff) << 4; +} +static inline u32 gmmu_new_pte_comptagline_w(void) +{ + return 1; +} +static inline u32 gmmu_new_pte_kind_f(u32 v) +{ + return (v & 0xff) << 24; +} +static inline u32 gmmu_new_pte_kind_w(void) +{ + return 1; +} +static inline u32 gmmu_new_pte_address_shift_v(void) +{ + return 0x0000000c; +} +static inline u32 gmmu_pte_kind_f(u32 v) +{ + return (v & 0xff) << 4; +} +static inline u32 gmmu_pte_kind_w(void) +{ + return 1; +} +static inline u32 gmmu_pte_kind_invalid_v(void) +{ + return 0x000000ff; +} +static inline u32 gmmu_pte_kind_pitch_v(void) +{ + return 0x00000000; +} +static inline u32 gmmu_pte_kind_z16_v(void) +{ + return 0x00000001; +} +static inline u32 gmmu_pte_kind_z16_2c_v(void) +{ + return 0x00000002; +} +static inline u32 gmmu_pte_kind_z16_ms2_2c_v(void) +{ + return 0x00000003; +} +static inline u32 gmmu_pte_kind_z16_ms4_2c_v(void) +{ + return 0x00000004; +} +static inline u32 gmmu_pte_kind_z16_ms8_2c_v(void) +{ + return 0x00000005; +} +static inline u32 gmmu_pte_kind_z16_ms16_2c_v(void) +{ + return 0x00000006; +} +static inline u32 gmmu_pte_kind_z16_2z_v(void) +{ + return 0x00000007; +} +static inline u32 gmmu_pte_kind_z16_ms2_2z_v(void) +{ + return 0x00000008; +} +static inline u32 gmmu_pte_kind_z16_ms4_2z_v(void) +{ + return 0x00000009; +} +static inline u32 gmmu_pte_kind_z16_ms8_2z_v(void) +{ + return 0x0000000a; +} +static inline u32 gmmu_pte_kind_z16_ms16_2z_v(void) +{ + return 0x0000000b; +} +static inline u32 gmmu_pte_kind_z16_2cz_v(void) +{ + return 0x00000036; +} +static inline u32 gmmu_pte_kind_z16_ms2_2cz_v(void) +{ + return 0x00000037; +} +static inline u32 gmmu_pte_kind_z16_ms4_2cz_v(void) +{ + return 0x00000038; +} +static inline u32 gmmu_pte_kind_z16_ms8_2cz_v(void) +{ + return 0x00000039; +} +static inline u32 gmmu_pte_kind_z16_ms16_2cz_v(void) +{ + return 0x0000005f; +} +static inline u32 gmmu_pte_kind_s8z24_v(void) +{ + return 0x00000011; +} +static inline u32 gmmu_pte_kind_s8z24_1z_v(void) +{ + return 0x00000012; +} +static inline u32 gmmu_pte_kind_s8z24_ms2_1z_v(void) +{ + return 0x00000013; +} +static inline u32 gmmu_pte_kind_s8z24_ms4_1z_v(void) +{ + return 0x00000014; +} +static inline u32 gmmu_pte_kind_s8z24_ms8_1z_v(void) +{ + return 0x00000015; +} +static inline u32 gmmu_pte_kind_s8z24_ms16_1z_v(void) +{ + return 0x00000016; +} +static inline u32 gmmu_pte_kind_s8z24_2cz_v(void) +{ + return 0x00000017; +} +static inline u32 gmmu_pte_kind_s8z24_ms2_2cz_v(void) +{ + return 0x00000018; +} +static inline u32 gmmu_pte_kind_s8z24_ms4_2cz_v(void) +{ + return 0x00000019; +} +static inline u32 gmmu_pte_kind_s8z24_ms8_2cz_v(void) +{ + return 0x0000001a; +} +static inline u32 gmmu_pte_kind_s8z24_ms16_2cz_v(void) +{ + return 0x0000001b; +} +static inline u32 gmmu_pte_kind_s8z24_2cs_v(void) +{ + return 0x0000001c; +} +static inline u32 gmmu_pte_kind_s8z24_ms2_2cs_v(void) +{ + return 0x0000001d; +} +static inline u32 gmmu_pte_kind_s8z24_ms4_2cs_v(void) +{ + return 0x0000001e; +} +static inline u32 gmmu_pte_kind_s8z24_ms8_2cs_v(void) +{ + return 0x0000001f; +} +static inline u32 gmmu_pte_kind_s8z24_ms16_2cs_v(void) +{ + return 0x00000020; +} +static inline u32 gmmu_pte_kind_s8z24_4cszv_v(void) +{ + return 0x00000021; +} +static inline u32 gmmu_pte_kind_s8z24_ms2_4cszv_v(void) +{ + return 0x00000022; +} +static inline u32 gmmu_pte_kind_s8z24_ms4_4cszv_v(void) +{ + return 0x00000023; +} +static inline u32 gmmu_pte_kind_s8z24_ms8_4cszv_v(void) +{ + return 0x00000024; +} +static inline u32 gmmu_pte_kind_s8z24_ms16_4cszv_v(void) +{ + return 0x00000025; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_v(void) +{ + return 0x00000026; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_v(void) +{ + return 0x00000027; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_v(void) +{ + return 0x00000028; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_v(void) +{ + return 0x00000029; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_1zv_v(void) +{ + return 0x0000002e; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_1zv_v(void) +{ + return 0x0000002f; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_1zv_v(void) +{ + return 0x00000030; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_1zv_v(void) +{ + return 0x00000031; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2cs_v(void) +{ + return 0x00000032; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2cs_v(void) +{ + return 0x00000033; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2cs_v(void) +{ + return 0x00000034; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2cs_v(void) +{ + return 0x00000035; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2czv_v(void) +{ + return 0x0000003a; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2czv_v(void) +{ + return 0x0000003b; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2czv_v(void) +{ + return 0x0000003c; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2czv_v(void) +{ + return 0x0000003d; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2zv_v(void) +{ + return 0x0000003e; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2zv_v(void) +{ + return 0x0000003f; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2zv_v(void) +{ + return 0x00000040; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2zv_v(void) +{ + return 0x00000041; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_4cszv_v(void) +{ + return 0x00000042; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_4cszv_v(void) +{ + return 0x00000043; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_4cszv_v(void) +{ + return 0x00000044; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_4cszv_v(void) +{ + return 0x00000045; +} +static inline u32 gmmu_pte_kind_z24s8_v(void) +{ + return 0x00000046; +} +static inline u32 gmmu_pte_kind_z24s8_1z_v(void) +{ + return 0x00000047; +} +static inline u32 gmmu_pte_kind_z24s8_ms2_1z_v(void) +{ + return 0x00000048; +} +static inline u32 gmmu_pte_kind_z24s8_ms4_1z_v(void) +{ + return 0x00000049; +} +static inline u32 gmmu_pte_kind_z24s8_ms8_1z_v(void) +{ + return 0x0000004a; +} +static inline u32 gmmu_pte_kind_z24s8_ms16_1z_v(void) +{ + return 0x0000004b; +} +static inline u32 gmmu_pte_kind_z24s8_2cs_v(void) +{ + return 0x0000004c; +} +static inline u32 gmmu_pte_kind_z24s8_ms2_2cs_v(void) +{ + return 0x0000004d; +} +static inline u32 gmmu_pte_kind_z24s8_ms4_2cs_v(void) +{ + return 0x0000004e; +} +static inline u32 gmmu_pte_kind_z24s8_ms8_2cs_v(void) +{ + return 0x0000004f; +} +static inline u32 gmmu_pte_kind_z24s8_ms16_2cs_v(void) +{ + return 0x00000050; +} +static inline u32 gmmu_pte_kind_z24s8_2cz_v(void) +{ + return 0x00000051; +} +static inline u32 gmmu_pte_kind_z24s8_ms2_2cz_v(void) +{ + return 0x00000052; +} +static inline u32 gmmu_pte_kind_z24s8_ms4_2cz_v(void) +{ + return 0x00000053; +} +static inline u32 gmmu_pte_kind_z24s8_ms8_2cz_v(void) +{ + return 0x00000054; +} +static inline u32 gmmu_pte_kind_z24s8_ms16_2cz_v(void) +{ + return 0x00000055; +} +static inline u32 gmmu_pte_kind_z24s8_4cszv_v(void) +{ + return 0x00000056; +} +static inline u32 gmmu_pte_kind_z24s8_ms2_4cszv_v(void) +{ + return 0x00000057; +} +static inline u32 gmmu_pte_kind_z24s8_ms4_4cszv_v(void) +{ + return 0x00000058; +} +static inline u32 gmmu_pte_kind_z24s8_ms8_4cszv_v(void) +{ + return 0x00000059; +} +static inline u32 gmmu_pte_kind_z24s8_ms16_4cszv_v(void) +{ + return 0x0000005a; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_v(void) +{ + return 0x0000005b; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_v(void) +{ + return 0x0000005c; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_v(void) +{ + return 0x0000005d; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_v(void) +{ + return 0x0000005e; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_1zv_v(void) +{ + return 0x00000063; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_1zv_v(void) +{ + return 0x00000064; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_1zv_v(void) +{ + return 0x00000065; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_1zv_v(void) +{ + return 0x00000066; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2cs_v(void) +{ + return 0x00000067; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2cs_v(void) +{ + return 0x00000068; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2cs_v(void) +{ + return 0x00000069; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2cs_v(void) +{ + return 0x0000006a; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2czv_v(void) +{ + return 0x0000006f; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2czv_v(void) +{ + return 0x00000070; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2czv_v(void) +{ + return 0x00000071; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2czv_v(void) +{ + return 0x00000072; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2zv_v(void) +{ + return 0x00000073; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2zv_v(void) +{ + return 0x00000074; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2zv_v(void) +{ + return 0x00000075; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2zv_v(void) +{ + return 0x00000076; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_4cszv_v(void) +{ + return 0x00000077; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_4cszv_v(void) +{ + return 0x00000078; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_4cszv_v(void) +{ + return 0x00000079; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_4cszv_v(void) +{ + return 0x0000007a; +} +static inline u32 gmmu_pte_kind_zf32_v(void) +{ + return 0x0000007b; +} +static inline u32 gmmu_pte_kind_zf32_1z_v(void) +{ + return 0x0000007c; +} +static inline u32 gmmu_pte_kind_zf32_ms2_1z_v(void) +{ + return 0x0000007d; +} +static inline u32 gmmu_pte_kind_zf32_ms4_1z_v(void) +{ + return 0x0000007e; +} +static inline u32 gmmu_pte_kind_zf32_ms8_1z_v(void) +{ + return 0x0000007f; +} +static inline u32 gmmu_pte_kind_zf32_ms16_1z_v(void) +{ + return 0x00000080; +} +static inline u32 gmmu_pte_kind_zf32_2cs_v(void) +{ + return 0x00000081; +} +static inline u32 gmmu_pte_kind_zf32_ms2_2cs_v(void) +{ + return 0x00000082; +} +static inline u32 gmmu_pte_kind_zf32_ms4_2cs_v(void) +{ + return 0x00000083; +} +static inline u32 gmmu_pte_kind_zf32_ms8_2cs_v(void) +{ + return 0x00000084; +} +static inline u32 gmmu_pte_kind_zf32_ms16_2cs_v(void) +{ + return 0x00000085; +} +static inline u32 gmmu_pte_kind_zf32_2cz_v(void) +{ + return 0x00000086; +} +static inline u32 gmmu_pte_kind_zf32_ms2_2cz_v(void) +{ + return 0x00000087; +} +static inline u32 gmmu_pte_kind_zf32_ms4_2cz_v(void) +{ + return 0x00000088; +} +static inline u32 gmmu_pte_kind_zf32_ms8_2cz_v(void) +{ + return 0x00000089; +} +static inline u32 gmmu_pte_kind_zf32_ms16_2cz_v(void) +{ + return 0x0000008a; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_v(void) +{ + return 0x0000008b; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_v(void) +{ + return 0x0000008c; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_v(void) +{ + return 0x0000008d; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_v(void) +{ + return 0x0000008e; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1cs_v(void) +{ + return 0x0000008f; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1cs_v(void) +{ + return 0x00000090; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1cs_v(void) +{ + return 0x00000091; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1cs_v(void) +{ + return 0x00000092; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1zv_v(void) +{ + return 0x00000097; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1zv_v(void) +{ + return 0x00000098; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1zv_v(void) +{ + return 0x00000099; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1zv_v(void) +{ + return 0x0000009a; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1czv_v(void) +{ + return 0x0000009b; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1czv_v(void) +{ + return 0x0000009c; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1czv_v(void) +{ + return 0x0000009d; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1czv_v(void) +{ + return 0x0000009e; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cs_v(void) +{ + return 0x0000009f; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cs_v(void) +{ + return 0x000000a0; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cs_v(void) +{ + return 0x000000a1; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cs_v(void) +{ + return 0x000000a2; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cszv_v(void) +{ + return 0x000000a3; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cszv_v(void) +{ + return 0x000000a4; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cszv_v(void) +{ + return 0x000000a5; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cszv_v(void) +{ + return 0x000000a6; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_v(void) +{ + return 0x000000a7; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_v(void) +{ + return 0x000000a8; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_v(void) +{ + return 0x000000a9; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_v(void) +{ + return 0x000000aa; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1cs_v(void) +{ + return 0x000000ab; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1cs_v(void) +{ + return 0x000000ac; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1cs_v(void) +{ + return 0x000000ad; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1cs_v(void) +{ + return 0x000000ae; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1zv_v(void) +{ + return 0x000000b3; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1zv_v(void) +{ + return 0x000000b4; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1zv_v(void) +{ + return 0x000000b5; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1zv_v(void) +{ + return 0x000000b6; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1czv_v(void) +{ + return 0x000000b7; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1czv_v(void) +{ + return 0x000000b8; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1czv_v(void) +{ + return 0x000000b9; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1czv_v(void) +{ + return 0x000000ba; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cs_v(void) +{ + return 0x000000bb; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cs_v(void) +{ + return 0x000000bc; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cs_v(void) +{ + return 0x000000bd; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cs_v(void) +{ + return 0x000000be; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cszv_v(void) +{ + return 0x000000bf; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cszv_v(void) +{ + return 0x000000c0; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cszv_v(void) +{ + return 0x000000c1; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cszv_v(void) +{ + return 0x000000c2; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_v(void) +{ + return 0x000000c3; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_1cs_v(void) +{ + return 0x000000c4; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_1cs_v(void) +{ + return 0x000000c5; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_1cs_v(void) +{ + return 0x000000c6; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_1cs_v(void) +{ + return 0x000000c7; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_1cs_v(void) +{ + return 0x000000c8; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_2cszv_v(void) +{ + return 0x000000ce; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cszv_v(void) +{ + return 0x000000cf; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cszv_v(void) +{ + return 0x000000d0; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cszv_v(void) +{ + return 0x000000d1; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cszv_v(void) +{ + return 0x000000d2; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_2cs_v(void) +{ + return 0x000000d3; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cs_v(void) +{ + return 0x000000d4; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cs_v(void) +{ + return 0x000000d5; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cs_v(void) +{ + return 0x000000d6; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cs_v(void) +{ + return 0x000000d7; +} +static inline u32 gmmu_pte_kind_generic_16bx2_v(void) +{ + return 0x000000fe; +} +static inline u32 gmmu_pte_kind_c32_2c_v(void) +{ + return 0x000000d8; +} +static inline u32 gmmu_pte_kind_c32_2cbr_v(void) +{ + return 0x000000d9; +} +static inline u32 gmmu_pte_kind_c32_2cba_v(void) +{ + return 0x000000da; +} +static inline u32 gmmu_pte_kind_c32_2cra_v(void) +{ + return 0x000000db; +} +static inline u32 gmmu_pte_kind_c32_2bra_v(void) +{ + return 0x000000dc; +} +static inline u32 gmmu_pte_kind_c32_ms2_2c_v(void) +{ + return 0x000000dd; +} +static inline u32 gmmu_pte_kind_c32_ms2_2cbr_v(void) +{ + return 0x000000de; +} +static inline u32 gmmu_pte_kind_c32_ms2_4cbra_v(void) +{ + return 0x000000cc; +} +static inline u32 gmmu_pte_kind_c32_ms4_2c_v(void) +{ + return 0x000000df; +} +static inline u32 gmmu_pte_kind_c32_ms4_2cbr_v(void) +{ + return 0x000000e0; +} +static inline u32 gmmu_pte_kind_c32_ms4_2cba_v(void) +{ + return 0x000000e1; +} +static inline u32 gmmu_pte_kind_c32_ms4_2cra_v(void) +{ + return 0x000000e2; +} +static inline u32 gmmu_pte_kind_c32_ms4_2bra_v(void) +{ + return 0x000000e3; +} +static inline u32 gmmu_pte_kind_c32_ms4_4cbra_v(void) +{ + return 0x0000002c; +} +static inline u32 gmmu_pte_kind_c32_ms8_ms16_2c_v(void) +{ + return 0x000000e4; +} +static inline u32 gmmu_pte_kind_c32_ms8_ms16_2cra_v(void) +{ + return 0x000000e5; +} +static inline u32 gmmu_pte_kind_c64_2c_v(void) +{ + return 0x000000e6; +} +static inline u32 gmmu_pte_kind_c64_2cbr_v(void) +{ + return 0x000000e7; +} +static inline u32 gmmu_pte_kind_c64_2cba_v(void) +{ + return 0x000000e8; +} +static inline u32 gmmu_pte_kind_c64_2cra_v(void) +{ + return 0x000000e9; +} +static inline u32 gmmu_pte_kind_c64_2bra_v(void) +{ + return 0x000000ea; +} +static inline u32 gmmu_pte_kind_c64_ms2_2c_v(void) +{ + return 0x000000eb; +} +static inline u32 gmmu_pte_kind_c64_ms2_2cbr_v(void) +{ + return 0x000000ec; +} +static inline u32 gmmu_pte_kind_c64_ms2_4cbra_v(void) +{ + return 0x000000cd; +} +static inline u32 gmmu_pte_kind_c64_ms4_2c_v(void) +{ + return 0x000000ed; +} +static inline u32 gmmu_pte_kind_c64_ms4_2cbr_v(void) +{ + return 0x000000ee; +} +static inline u32 gmmu_pte_kind_c64_ms4_2cba_v(void) +{ + return 0x000000ef; +} +static inline u32 gmmu_pte_kind_c64_ms4_2cra_v(void) +{ + return 0x000000f0; +} +static inline u32 gmmu_pte_kind_c64_ms4_2bra_v(void) +{ + return 0x000000f1; +} +static inline u32 gmmu_pte_kind_c64_ms4_4cbra_v(void) +{ + return 0x0000002d; +} +static inline u32 gmmu_pte_kind_c64_ms8_ms16_2c_v(void) +{ + return 0x000000f2; +} +static inline u32 gmmu_pte_kind_c64_ms8_ms16_2cra_v(void) +{ + return 0x000000f3; +} +static inline u32 gmmu_pte_kind_c128_2c_v(void) +{ + return 0x000000f4; +} +static inline u32 gmmu_pte_kind_c128_2cr_v(void) +{ + return 0x000000f5; +} +static inline u32 gmmu_pte_kind_c128_ms2_2c_v(void) +{ + return 0x000000f6; +} +static inline u32 gmmu_pte_kind_c128_ms2_2cr_v(void) +{ + return 0x000000f7; +} +static inline u32 gmmu_pte_kind_c128_ms4_2c_v(void) +{ + return 0x000000f8; +} +static inline u32 gmmu_pte_kind_c128_ms4_2cr_v(void) +{ + return 0x000000f9; +} +static inline u32 gmmu_pte_kind_c128_ms8_ms16_2c_v(void) +{ + return 0x000000fa; +} +static inline u32 gmmu_pte_kind_c128_ms8_ms16_2cr_v(void) +{ + return 0x000000fb; +} +static inline u32 gmmu_pte_kind_x8c24_v(void) +{ + return 0x000000fc; +} +static inline u32 gmmu_pte_kind_pitch_no_swizzle_v(void) +{ + return 0x000000fd; +} +static inline u32 gmmu_pte_kind_smsked_message_v(void) +{ + return 0x000000ca; +} +static inline u32 gmmu_pte_kind_smhost_message_v(void) +{ + return 0x000000cb; +} +static inline u32 gmmu_pte_kind_s8_v(void) +{ + return 0x0000002a; +} +static inline u32 gmmu_pte_kind_s8_2s_v(void) +{ + return 0x0000002b; +} +static inline u32 gmmu_fault_client_type_gpc_v(void) +{ + return 0x00000000; +} +static inline u32 gmmu_fault_client_type_hub_v(void) +{ + return 0x00000001; +} +static inline u32 gmmu_fault_type_unbound_inst_block_v(void) +{ + return 0x00000004; +} +static inline u32 gmmu_fault_mmu_eng_id_bar2_v(void) +{ + return 0x00000005; +} +static inline u32 gmmu_fault_mmu_eng_id_physical_v(void) +{ + return 0x0000001f; +} +static inline u32 gmmu_fault_mmu_eng_id_ce0_v(void) +{ + return 0x0000000f; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h new file mode 100644 index 00000000..af1915b2 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h @@ -0,0 +1,3905 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_gr_gv100_h_ +#define _hw_gr_gv100_h_ + +static inline u32 gr_intr_r(void) +{ + return 0x00400100; +} +static inline u32 gr_intr_notify_pending_f(void) +{ + return 0x1; +} +static inline u32 gr_intr_notify_reset_f(void) +{ + return 0x1; +} +static inline u32 gr_intr_semaphore_pending_f(void) +{ + return 0x2; +} +static inline u32 gr_intr_semaphore_reset_f(void) +{ + return 0x2; +} +static inline u32 gr_intr_illegal_method_pending_f(void) +{ + return 0x10; +} +static inline u32 gr_intr_illegal_method_reset_f(void) +{ + return 0x10; +} +static inline u32 gr_intr_illegal_notify_pending_f(void) +{ + return 0x40; +} +static inline u32 gr_intr_illegal_notify_reset_f(void) +{ + return 0x40; +} +static inline u32 gr_intr_firmware_method_f(u32 v) +{ + return (v & 0x1) << 8; +} +static inline u32 gr_intr_firmware_method_pending_f(void) +{ + return 0x100; +} +static inline u32 gr_intr_firmware_method_reset_f(void) +{ + return 0x100; +} +static inline u32 gr_intr_illegal_class_pending_f(void) +{ + return 0x20; +} +static inline u32 gr_intr_illegal_class_reset_f(void) +{ + return 0x20; +} +static inline u32 gr_intr_fecs_error_pending_f(void) +{ + return 0x80000; +} +static inline u32 gr_intr_fecs_error_reset_f(void) +{ + return 0x80000; +} +static inline u32 gr_intr_class_error_pending_f(void) +{ + return 0x100000; +} +static inline u32 gr_intr_class_error_reset_f(void) +{ + return 0x100000; +} +static inline u32 gr_intr_exception_pending_f(void) +{ + return 0x200000; +} +static inline u32 gr_intr_exception_reset_f(void) +{ + return 0x200000; +} +static inline u32 gr_fecs_intr_r(void) +{ + return 0x00400144; +} +static inline u32 gr_class_error_r(void) +{ + return 0x00400110; +} +static inline u32 gr_class_error_code_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_intr_nonstall_r(void) +{ + return 0x00400120; +} +static inline u32 gr_intr_nonstall_trap_pending_f(void) +{ + return 0x2; +} +static inline u32 gr_intr_en_r(void) +{ + return 0x0040013c; +} +static inline u32 gr_exception_r(void) +{ + return 0x00400108; +} +static inline u32 gr_exception_fe_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_exception_gpc_m(void) +{ + return 0x1 << 24; +} +static inline u32 gr_exception_memfmt_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_exception_ds_m(void) +{ + return 0x1 << 4; +} +static inline u32 gr_exception_sked_m(void) +{ + return 0x1 << 8; +} +static inline u32 gr_exception1_r(void) +{ + return 0x00400118; +} +static inline u32 gr_exception1_gpc_0_pending_f(void) +{ + return 0x1; +} +static inline u32 gr_exception2_r(void) +{ + return 0x0040011c; +} +static inline u32 gr_exception_en_r(void) +{ + return 0x00400138; +} +static inline u32 gr_exception_en_fe_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_exception_en_fe_enabled_f(void) +{ + return 0x1; +} +static inline u32 gr_exception_en_gpc_m(void) +{ + return 0x1 << 24; +} +static inline u32 gr_exception_en_gpc_enabled_f(void) +{ + return 0x1000000; +} +static inline u32 gr_exception_en_memfmt_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_exception_en_memfmt_enabled_f(void) +{ + return 0x2; +} +static inline u32 gr_exception_en_ds_m(void) +{ + return 0x1 << 4; +} +static inline u32 gr_exception_en_ds_enabled_f(void) +{ + return 0x10; +} +static inline u32 gr_exception1_en_r(void) +{ + return 0x00400130; +} +static inline u32 gr_exception2_en_r(void) +{ + return 0x00400134; +} +static inline u32 gr_gpfifo_ctl_r(void) +{ + return 0x00400500; +} +static inline u32 gr_gpfifo_ctl_access_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 gr_gpfifo_ctl_access_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_gpfifo_ctl_access_enabled_f(void) +{ + return 0x1; +} +static inline u32 gr_gpfifo_ctl_semaphore_access_f(u32 v) +{ + return (v & 0x1) << 16; +} +static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_f(void) +{ + return 0x10000; +} +static inline u32 gr_gpfifo_status_r(void) +{ + return 0x00400504; +} +static inline u32 gr_trapped_addr_r(void) +{ + return 0x00400704; +} +static inline u32 gr_trapped_addr_mthd_v(u32 r) +{ + return (r >> 2) & 0xfff; +} +static inline u32 gr_trapped_addr_subch_v(u32 r) +{ + return (r >> 16) & 0x7; +} +static inline u32 gr_trapped_data_lo_r(void) +{ + return 0x00400708; +} +static inline u32 gr_trapped_data_hi_r(void) +{ + return 0x0040070c; +} +static inline u32 gr_status_r(void) +{ + return 0x00400700; +} +static inline u32 gr_status_fe_method_upper_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 gr_status_fe_method_lower_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 gr_status_fe_method_lower_idle_v(void) +{ + return 0x00000000; +} +static inline u32 gr_status_fe_gi_v(u32 r) +{ + return (r >> 21) & 0x1; +} +static inline u32 gr_status_mask_r(void) +{ + return 0x00400610; +} +static inline u32 gr_status_1_r(void) +{ + return 0x00400604; +} +static inline u32 gr_status_2_r(void) +{ + return 0x00400608; +} +static inline u32 gr_engine_status_r(void) +{ + return 0x0040060c; +} +static inline u32 gr_engine_status_value_busy_f(void) +{ + return 0x1; +} +static inline u32 gr_pri_be0_becs_be_exception_r(void) +{ + return 0x00410204; +} +static inline u32 gr_pri_be0_becs_be_exception_en_r(void) +{ + return 0x00410208; +} +static inline u32 gr_pri_gpc0_gpccs_gpc_exception_r(void) +{ + return 0x00502c90; +} +static inline u32 gr_pri_gpc0_gpccs_gpc_exception_en_r(void) +{ + return 0x00502c94; +} +static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_r(void) +{ + return 0x00504508; +} +static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r(void) +{ + return 0x0050450c; +} +static inline u32 gr_activity_0_r(void) +{ + return 0x00400380; +} +static inline u32 gr_activity_1_r(void) +{ + return 0x00400384; +} +static inline u32 gr_activity_2_r(void) +{ + return 0x00400388; +} +static inline u32 gr_activity_4_r(void) +{ + return 0x00400390; +} +static inline u32 gr_activity_4_gpc0_s(void) +{ + return 3; +} +static inline u32 gr_activity_4_gpc0_f(u32 v) +{ + return (v & 0x7) << 0; +} +static inline u32 gr_activity_4_gpc0_m(void) +{ + return 0x7 << 0; +} +static inline u32 gr_activity_4_gpc0_v(u32 r) +{ + return (r >> 0) & 0x7; +} +static inline u32 gr_activity_4_gpc0_empty_v(void) +{ + return 0x00000000; +} +static inline u32 gr_activity_4_gpc0_preempted_v(void) +{ + return 0x00000004; +} +static inline u32 gr_pri_gpc0_gcc_dbg_r(void) +{ + return 0x00501000; +} +static inline u32 gr_pri_gpcs_gcc_dbg_r(void) +{ + return 0x00419000; +} +static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void) +{ + return 0x0050433c; +} +static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void) +{ + return 0x00419b3c; +} +static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_pri_sked_activity_r(void) +{ + return 0x00407054; +} +static inline u32 gr_pri_gpc0_gpccs_gpc_activity0_r(void) +{ + return 0x00502c80; +} +static inline u32 gr_pri_gpc0_gpccs_gpc_activity1_r(void) +{ + return 0x00502c84; +} +static inline u32 gr_pri_gpc0_gpccs_gpc_activity2_r(void) +{ + return 0x00502c88; +} +static inline u32 gr_pri_gpc0_gpccs_gpc_activity3_r(void) +{ + return 0x00502c8c; +} +static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r(void) +{ + return 0x00504500; +} +static inline u32 gr_pri_gpc0_tpc1_tpccs_tpc_activity_0_r(void) +{ + return 0x00504d00; +} +static inline u32 gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r(void) +{ + return 0x00501d00; +} +static inline u32 gr_pri_gpcs_gpccs_gpc_activity_0_r(void) +{ + return 0x0041ac80; +} +static inline u32 gr_pri_gpcs_gpccs_gpc_activity_1_r(void) +{ + return 0x0041ac84; +} +static inline u32 gr_pri_gpcs_gpccs_gpc_activity_2_r(void) +{ + return 0x0041ac88; +} +static inline u32 gr_pri_gpcs_gpccs_gpc_activity_3_r(void) +{ + return 0x0041ac8c; +} +static inline u32 gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r(void) +{ + return 0x0041c500; +} +static inline u32 gr_pri_gpcs_tpc1_tpccs_tpc_activity_0_r(void) +{ + return 0x0041cd00; +} +static inline u32 gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r(void) +{ + return 0x00419d00; +} +static inline u32 gr_pri_be0_becs_be_activity0_r(void) +{ + return 0x00410200; +} +static inline u32 gr_pri_be1_becs_be_activity0_r(void) +{ + return 0x00410600; +} +static inline u32 gr_pri_bes_becs_be_activity0_r(void) +{ + return 0x00408a00; +} +static inline u32 gr_pri_ds_mpipe_status_r(void) +{ + return 0x00405858; +} +static inline u32 gr_pri_fe_go_idle_info_r(void) +{ + return 0x00404194; +} +static inline u32 gr_pri_fe_chip_def_info_r(void) +{ + return 0x00404030; +} +static inline u32 gr_pri_fe_chip_def_info_max_veid_count_v(u32 r) +{ + return (r >> 0) & 0xfff; +} +static inline u32 gr_pri_fe_chip_def_info_max_veid_count_init_v(void) +{ + return 0x00000040; +} +static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void) +{ + return 0x00504238; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r(void) +{ + return 0x00504358; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp0_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp1_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp2_m(void) +{ + return 0x1 << 2; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp3_m(void) +{ + return 0x1 << 3; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp4_m(void) +{ + return 0x1 << 4; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp5_m(void) +{ + return 0x1 << 5; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp6_m(void) +{ + return 0x1 << 6; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp7_m(void) +{ + return 0x1 << 7; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp0_m(void) +{ + return 0x1 << 8; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp1_m(void) +{ + return 0x1 << 9; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp2_m(void) +{ + return 0x1 << 10; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp3_m(void) +{ + return 0x1 << 11; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp4_m(void) +{ + return 0x1 << 12; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp5_m(void) +{ + return 0x1 << 13; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp6_m(void) +{ + return 0x1 << 14; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp7_m(void) +{ + return 0x1 << 15; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_total_counter_overflow_v(u32 r) +{ + return (r >> 24) & 0x1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) +{ + return (r >> 26) & 0x1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_reset_task_f(void) +{ + return 0x40000000; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_r(void) +{ + return 0x0050435c; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_r(void) +{ + return 0x00504360; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_r(void) +{ + return 0x0050436c; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_0_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_1_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_0_m(void) +{ + return 0x1 << 2; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_1_m(void) +{ + return 0x1 << 3; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_total_counter_overflow_v(u32 r) +{ + return (r >> 8) & 0x1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) +{ + return (r >> 10) & 0x1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_reset_task_f(void) +{ + return 0x40000000; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_r(void) +{ + return 0x00504370; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_r(void) +{ + return 0x00504374; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_r(void) +{ + return 0x00504638; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm0_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm1_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm0_m(void) +{ + return 0x1 << 2; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm1_m(void) +{ + return 0x1 << 3; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm0_m(void) +{ + return 0x1 << 4; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm1_m(void) +{ + return 0x1 << 5; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm0_m(void) +{ + return 0x1 << 6; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm1_m(void) +{ + return 0x1 << 7; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_total_counter_overflow_v(u32 r) +{ + return (r >> 16) & 0x1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) +{ + return (r >> 18) & 0x1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_reset_task_f(void) +{ + return 0x40000000; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_r(void) +{ + return 0x0050463c; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_r(void) +{ + return 0x00504640; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_r(void) +{ + return 0x005042c4; +} +static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f(void) +{ + return 0x0; +} +static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f(void) +{ + return 0x1; +} +static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f(void) +{ + return 0x2; +} +static inline u32 gr_gpc0_tpc0_mpc_hww_esr_r(void) +{ + return 0x00504430; +} +static inline u32 gr_gpc0_tpc0_mpc_hww_esr_reset_trigger_f(void) +{ + return 0x40000000; +} +static inline u32 gr_gpc0_tpc0_mpc_hww_esr_info_r(void) +{ + return 0x00504434; +} +static inline u32 gr_gpc0_tpc0_mpc_hww_esr_info_veid_v(u32 r) +{ + return (r >> 0) & 0x3f; +} +static inline u32 gr_pri_be0_crop_status1_r(void) +{ + return 0x00410134; +} +static inline u32 gr_pri_bes_crop_status1_r(void) +{ + return 0x00408934; +} +static inline u32 gr_pri_be0_zrop_status_r(void) +{ + return 0x00410048; +} +static inline u32 gr_pri_be0_zrop_status2_r(void) +{ + return 0x0041004c; +} +static inline u32 gr_pri_bes_zrop_status_r(void) +{ + return 0x00408848; +} +static inline u32 gr_pri_bes_zrop_status2_r(void) +{ + return 0x0040884c; +} +static inline u32 gr_pipe_bundle_address_r(void) +{ + return 0x00400200; +} +static inline u32 gr_pipe_bundle_address_value_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_pipe_bundle_address_veid_f(u32 v) +{ + return (v & 0x3f) << 20; +} +static inline u32 gr_pipe_bundle_address_veid_w(void) +{ + return 0; +} +static inline u32 gr_pipe_bundle_data_r(void) +{ + return 0x00400204; +} +static inline u32 gr_pipe_bundle_config_r(void) +{ + return 0x00400208; +} +static inline u32 gr_pipe_bundle_config_override_pipe_mode_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_pipe_bundle_config_override_pipe_mode_enabled_f(void) +{ + return 0x80000000; +} +static inline u32 gr_fe_hww_esr_r(void) +{ + return 0x00404000; +} +static inline u32 gr_fe_hww_esr_reset_active_f(void) +{ + return 0x40000000; +} +static inline u32 gr_fe_hww_esr_en_enable_f(void) +{ + return 0x80000000; +} +static inline u32 gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r(void) +{ + return 0x00419eac; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_r(void) +{ + return 0x0050472c; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_multiple_warp_errors_report_f(void) +{ + return 0x4; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_bpt_int_report_f(void) +{ + return 0x10; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_bpt_pause_report_f(void) +{ + return 0x20; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_single_step_complete_report_f(void) +{ + return 0x40; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_error_in_trap_report_f(void) +{ + return 0x100; +} +static inline u32 gr_gpcs_tpcs_sms_hww_global_esr_r(void) +{ + return 0x00419eb4; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_r(void) +{ + return 0x00504734; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_m(void) +{ + return 0x1 << 4; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f(void) +{ + return 0x10; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_m(void) +{ + return 0x1 << 5; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_pending_f(void) +{ + return 0x20; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_m(void) +{ + return 0x1 << 6; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_pending_f(void) +{ + return 0x40; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_m(void) +{ + return 0x1 << 2; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_pending_f(void) +{ + return 0x4; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_m(void) +{ + return 0x1 << 8; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_pending_f(void) +{ + return 0x100; +} +static inline u32 gr_fe_go_idle_timeout_r(void) +{ + return 0x00404154; +} +static inline u32 gr_fe_go_idle_timeout_count_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_fe_go_idle_timeout_count_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_fe_go_idle_timeout_count_prod_f(void) +{ + return 0x1800; +} +static inline u32 gr_fe_object_table_r(u32 i) +{ + return 0x00404200 + i*4; +} +static inline u32 gr_fe_object_table_nvclass_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_fe_tpc_fs_r(u32 i) +{ + return 0x0040a200 + i*4; +} +static inline u32 gr_pri_mme_shadow_raw_index_r(void) +{ + return 0x00404488; +} +static inline u32 gr_pri_mme_shadow_raw_index_write_trigger_f(void) +{ + return 0x80000000; +} +static inline u32 gr_pri_mme_shadow_raw_data_r(void) +{ + return 0x0040448c; +} +static inline u32 gr_mme_hww_esr_r(void) +{ + return 0x00404490; +} +static inline u32 gr_mme_hww_esr_reset_active_f(void) +{ + return 0x40000000; +} +static inline u32 gr_mme_hww_esr_en_enable_f(void) +{ + return 0x80000000; +} +static inline u32 gr_memfmt_hww_esr_r(void) +{ + return 0x00404600; +} +static inline u32 gr_memfmt_hww_esr_reset_active_f(void) +{ + return 0x40000000; +} +static inline u32 gr_memfmt_hww_esr_en_enable_f(void) +{ + return 0x80000000; +} +static inline u32 gr_fecs_cpuctl_r(void) +{ + return 0x00409100; +} +static inline u32 gr_fecs_cpuctl_startcpu_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 gr_fecs_cpuctl_alias_r(void) +{ + return 0x00409130; +} +static inline u32 gr_fecs_cpuctl_alias_startcpu_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 gr_fecs_dmactl_r(void) +{ + return 0x0040910c; +} +static inline u32 gr_fecs_dmactl_require_ctx_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 gr_fecs_dmactl_dmem_scrubbing_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_fecs_dmactl_imem_scrubbing_m(void) +{ + return 0x1 << 2; +} +static inline u32 gr_fecs_os_r(void) +{ + return 0x00409080; +} +static inline u32 gr_fecs_idlestate_r(void) +{ + return 0x0040904c; +} +static inline u32 gr_fecs_mailbox0_r(void) +{ + return 0x00409040; +} +static inline u32 gr_fecs_mailbox1_r(void) +{ + return 0x00409044; +} +static inline u32 gr_fecs_irqstat_r(void) +{ + return 0x00409008; +} +static inline u32 gr_fecs_irqmode_r(void) +{ + return 0x0040900c; +} +static inline u32 gr_fecs_irqmask_r(void) +{ + return 0x00409018; +} +static inline u32 gr_fecs_irqdest_r(void) +{ + return 0x0040901c; +} +static inline u32 gr_fecs_curctx_r(void) +{ + return 0x00409050; +} +static inline u32 gr_fecs_nxtctx_r(void) +{ + return 0x00409054; +} +static inline u32 gr_fecs_engctl_r(void) +{ + return 0x004090a4; +} +static inline u32 gr_fecs_debug1_r(void) +{ + return 0x00409090; +} +static inline u32 gr_fecs_debuginfo_r(void) +{ + return 0x00409094; +} +static inline u32 gr_fecs_icd_cmd_r(void) +{ + return 0x00409200; +} +static inline u32 gr_fecs_icd_cmd_opc_s(void) +{ + return 4; +} +static inline u32 gr_fecs_icd_cmd_opc_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 gr_fecs_icd_cmd_opc_m(void) +{ + return 0xf << 0; +} +static inline u32 gr_fecs_icd_cmd_opc_v(u32 r) +{ + return (r >> 0) & 0xf; +} +static inline u32 gr_fecs_icd_cmd_opc_rreg_f(void) +{ + return 0x8; +} +static inline u32 gr_fecs_icd_cmd_opc_rstat_f(void) +{ + return 0xe; +} +static inline u32 gr_fecs_icd_cmd_idx_f(u32 v) +{ + return (v & 0x1f) << 8; +} +static inline u32 gr_fecs_icd_rdata_r(void) +{ + return 0x0040920c; +} +static inline u32 gr_fecs_imemc_r(u32 i) +{ + return 0x00409180 + i*16; +} +static inline u32 gr_fecs_imemc_offs_f(u32 v) +{ + return (v & 0x3f) << 2; +} +static inline u32 gr_fecs_imemc_blk_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_fecs_imemc_aincw_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 gr_fecs_imemd_r(u32 i) +{ + return 0x00409184 + i*16; +} +static inline u32 gr_fecs_imemt_r(u32 i) +{ + return 0x00409188 + i*16; +} +static inline u32 gr_fecs_imemt_tag_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_fecs_dmemc_r(u32 i) +{ + return 0x004091c0 + i*8; +} +static inline u32 gr_fecs_dmemc_offs_s(void) +{ + return 6; +} +static inline u32 gr_fecs_dmemc_offs_f(u32 v) +{ + return (v & 0x3f) << 2; +} +static inline u32 gr_fecs_dmemc_offs_m(void) +{ + return 0x3f << 2; +} +static inline u32 gr_fecs_dmemc_offs_v(u32 r) +{ + return (r >> 2) & 0x3f; +} +static inline u32 gr_fecs_dmemc_blk_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_fecs_dmemc_aincw_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 gr_fecs_dmemd_r(u32 i) +{ + return 0x004091c4 + i*8; +} +static inline u32 gr_fecs_dmatrfbase_r(void) +{ + return 0x00409110; +} +static inline u32 gr_fecs_dmatrfmoffs_r(void) +{ + return 0x00409114; +} +static inline u32 gr_fecs_dmatrffboffs_r(void) +{ + return 0x0040911c; +} +static inline u32 gr_fecs_dmatrfcmd_r(void) +{ + return 0x00409118; +} +static inline u32 gr_fecs_dmatrfcmd_imem_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 gr_fecs_dmatrfcmd_write_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 gr_fecs_dmatrfcmd_size_f(u32 v) +{ + return (v & 0x7) << 8; +} +static inline u32 gr_fecs_dmatrfcmd_ctxdma_f(u32 v) +{ + return (v & 0x7) << 12; +} +static inline u32 gr_fecs_bootvec_r(void) +{ + return 0x00409104; +} +static inline u32 gr_fecs_bootvec_vec_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_fecs_falcon_hwcfg_r(void) +{ + return 0x00409108; +} +static inline u32 gr_gpcs_gpccs_falcon_hwcfg_r(void) +{ + return 0x0041a108; +} +static inline u32 gr_fecs_falcon_rm_r(void) +{ + return 0x00409084; +} +static inline u32 gr_fecs_current_ctx_r(void) +{ + return 0x00409b00; +} +static inline u32 gr_fecs_current_ctx_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 gr_fecs_current_ctx_ptr_v(u32 r) +{ + return (r >> 0) & 0xfffffff; +} +static inline u32 gr_fecs_current_ctx_target_s(void) +{ + return 2; +} +static inline u32 gr_fecs_current_ctx_target_f(u32 v) +{ + return (v & 0x3) << 28; +} +static inline u32 gr_fecs_current_ctx_target_m(void) +{ + return 0x3 << 28; +} +static inline u32 gr_fecs_current_ctx_target_v(u32 r) +{ + return (r >> 28) & 0x3; +} +static inline u32 gr_fecs_current_ctx_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 gr_fecs_current_ctx_target_sys_mem_coh_f(void) +{ + return 0x20000000; +} +static inline u32 gr_fecs_current_ctx_target_sys_mem_ncoh_f(void) +{ + return 0x30000000; +} +static inline u32 gr_fecs_current_ctx_valid_s(void) +{ + return 1; +} +static inline u32 gr_fecs_current_ctx_valid_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 gr_fecs_current_ctx_valid_m(void) +{ + return 0x1 << 31; +} +static inline u32 gr_fecs_current_ctx_valid_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 gr_fecs_current_ctx_valid_false_f(void) +{ + return 0x0; +} +static inline u32 gr_fecs_method_data_r(void) +{ + return 0x00409500; +} +static inline u32 gr_fecs_method_push_r(void) +{ + return 0x00409504; +} +static inline u32 gr_fecs_method_push_adr_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 gr_fecs_method_push_adr_bind_pointer_v(void) +{ + return 0x00000003; +} +static inline u32 gr_fecs_method_push_adr_bind_pointer_f(void) +{ + return 0x3; +} +static inline u32 gr_fecs_method_push_adr_discover_image_size_v(void) +{ + return 0x00000010; +} +static inline u32 gr_fecs_method_push_adr_wfi_golden_save_v(void) +{ + return 0x00000009; +} +static inline u32 gr_fecs_method_push_adr_restore_golden_v(void) +{ + return 0x00000015; +} +static inline u32 gr_fecs_method_push_adr_discover_zcull_image_size_v(void) +{ + return 0x00000016; +} +static inline u32 gr_fecs_method_push_adr_discover_pm_image_size_v(void) +{ + return 0x00000025; +} +static inline u32 gr_fecs_method_push_adr_discover_reglist_image_size_v(void) +{ + return 0x00000030; +} +static inline u32 gr_fecs_method_push_adr_set_reglist_bind_instance_v(void) +{ + return 0x00000031; +} +static inline u32 gr_fecs_method_push_adr_set_reglist_virtual_address_v(void) +{ + return 0x00000032; +} +static inline u32 gr_fecs_method_push_adr_stop_ctxsw_v(void) +{ + return 0x00000038; +} +static inline u32 gr_fecs_method_push_adr_start_ctxsw_v(void) +{ + return 0x00000039; +} +static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void) +{ + return 0x21; +} +static inline u32 gr_fecs_method_push_adr_discover_preemption_image_size_v(void) +{ + return 0x0000001a; +} +static inline u32 gr_fecs_method_push_adr_halt_pipeline_v(void) +{ + return 0x00000004; +} +static inline u32 gr_fecs_method_push_adr_configure_interrupt_completion_option_v(void) +{ + return 0x0000003a; +} +static inline u32 gr_fecs_host_int_status_r(void) +{ + return 0x00409c18; +} +static inline u32 gr_fecs_host_int_status_fault_during_ctxsw_f(u32 v) +{ + return (v & 0x1) << 16; +} +static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v) +{ + return (v & 0x1) << 17; +} +static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v) +{ + return (v & 0x1) << 18; +} +static inline u32 gr_fecs_host_int_status_ctxsw_intr_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_fecs_host_int_clear_r(void) +{ + return 0x00409c20; +} +static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_clear_f(void) +{ + return 0x2; +} +static inline u32 gr_fecs_host_int_enable_r(void) +{ + return 0x00409c24; +} +static inline u32 gr_fecs_host_int_enable_ctxsw_intr1_enable_f(void) +{ + return 0x2; +} +static inline u32 gr_fecs_host_int_enable_fault_during_ctxsw_enable_f(void) +{ + return 0x10000; +} +static inline u32 gr_fecs_host_int_enable_umimp_firmware_method_enable_f(void) +{ + return 0x20000; +} +static inline u32 gr_fecs_host_int_enable_umimp_illegal_method_enable_f(void) +{ + return 0x40000; +} +static inline u32 gr_fecs_host_int_enable_watchdog_enable_f(void) +{ + return 0x80000; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_r(void) +{ + return 0x00409614; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f(void) +{ + return 0x10; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f(void) +{ + return 0x20; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f(void) +{ + return 0x40; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f(void) +{ + return 0x0; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f(void) +{ + return 0x100; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f(void) +{ + return 0x0; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f(void) +{ + return 0x200; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_s(void) +{ + return 1; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_f(u32 v) +{ + return (v & 0x1) << 10; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_m(void) +{ + return 0x1 << 10; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_v(u32 r) +{ + return (r >> 10) & 0x1; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f(void) +{ + return 0x0; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f(void) +{ + return 0x400; +} +static inline u32 gr_fecs_ctx_state_store_major_rev_id_r(void) +{ + return 0x0040960c; +} +static inline u32 gr_fecs_ctxsw_mailbox_r(u32 i) +{ + return 0x00409800 + i*4; +} +static inline u32 gr_fecs_ctxsw_mailbox__size_1_v(void) +{ + return 0x00000010; +} +static inline u32 gr_fecs_ctxsw_mailbox_value_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_fecs_ctxsw_mailbox_value_pass_v(void) +{ + return 0x00000001; +} +static inline u32 gr_fecs_ctxsw_mailbox_value_fail_v(void) +{ + return 0x00000002; +} +static inline u32 gr_fecs_ctxsw_mailbox_set_r(u32 i) +{ + return 0x004098c0 + i*4; +} +static inline u32 gr_fecs_ctxsw_mailbox_set_value_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_fecs_ctxsw_mailbox_clear_r(u32 i) +{ + return 0x00409840 + i*4; +} +static inline u32 gr_fecs_ctxsw_mailbox_clear_value_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_fecs_fs_r(void) +{ + return 0x00409604; +} +static inline u32 gr_fecs_fs_num_available_gpcs_s(void) +{ + return 5; +} +static inline u32 gr_fecs_fs_num_available_gpcs_f(u32 v) +{ + return (v & 0x1f) << 0; +} +static inline u32 gr_fecs_fs_num_available_gpcs_m(void) +{ + return 0x1f << 0; +} +static inline u32 gr_fecs_fs_num_available_gpcs_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 gr_fecs_fs_num_available_fbps_s(void) +{ + return 5; +} +static inline u32 gr_fecs_fs_num_available_fbps_f(u32 v) +{ + return (v & 0x1f) << 16; +} +static inline u32 gr_fecs_fs_num_available_fbps_m(void) +{ + return 0x1f << 16; +} +static inline u32 gr_fecs_fs_num_available_fbps_v(u32 r) +{ + return (r >> 16) & 0x1f; +} +static inline u32 gr_fecs_cfg_r(void) +{ + return 0x00409620; +} +static inline u32 gr_fecs_cfg_imem_sz_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 gr_fecs_rc_lanes_r(void) +{ + return 0x00409880; +} +static inline u32 gr_fecs_rc_lanes_num_chains_s(void) +{ + return 6; +} +static inline u32 gr_fecs_rc_lanes_num_chains_f(u32 v) +{ + return (v & 0x3f) << 0; +} +static inline u32 gr_fecs_rc_lanes_num_chains_m(void) +{ + return 0x3f << 0; +} +static inline u32 gr_fecs_rc_lanes_num_chains_v(u32 r) +{ + return (r >> 0) & 0x3f; +} +static inline u32 gr_fecs_ctxsw_status_1_r(void) +{ + return 0x00409400; +} +static inline u32 gr_fecs_ctxsw_status_1_arb_busy_s(void) +{ + return 1; +} +static inline u32 gr_fecs_ctxsw_status_1_arb_busy_f(u32 v) +{ + return (v & 0x1) << 12; +} +static inline u32 gr_fecs_ctxsw_status_1_arb_busy_m(void) +{ + return 0x1 << 12; +} +static inline u32 gr_fecs_ctxsw_status_1_arb_busy_v(u32 r) +{ + return (r >> 12) & 0x1; +} +static inline u32 gr_fecs_arb_ctx_adr_r(void) +{ + return 0x00409a24; +} +static inline u32 gr_fecs_new_ctx_r(void) +{ + return 0x00409b04; +} +static inline u32 gr_fecs_new_ctx_ptr_s(void) +{ + return 28; +} +static inline u32 gr_fecs_new_ctx_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 gr_fecs_new_ctx_ptr_m(void) +{ + return 0xfffffff << 0; +} +static inline u32 gr_fecs_new_ctx_ptr_v(u32 r) +{ + return (r >> 0) & 0xfffffff; +} +static inline u32 gr_fecs_new_ctx_target_s(void) +{ + return 2; +} +static inline u32 gr_fecs_new_ctx_target_f(u32 v) +{ + return (v & 0x3) << 28; +} +static inline u32 gr_fecs_new_ctx_target_m(void) +{ + return 0x3 << 28; +} +static inline u32 gr_fecs_new_ctx_target_v(u32 r) +{ + return (r >> 28) & 0x3; +} +static inline u32 gr_fecs_new_ctx_valid_s(void) +{ + return 1; +} +static inline u32 gr_fecs_new_ctx_valid_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 gr_fecs_new_ctx_valid_m(void) +{ + return 0x1 << 31; +} +static inline u32 gr_fecs_new_ctx_valid_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 gr_fecs_arb_ctx_ptr_r(void) +{ + return 0x00409a0c; +} +static inline u32 gr_fecs_arb_ctx_ptr_ptr_s(void) +{ + return 28; +} +static inline u32 gr_fecs_arb_ctx_ptr_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 gr_fecs_arb_ctx_ptr_ptr_m(void) +{ + return 0xfffffff << 0; +} +static inline u32 gr_fecs_arb_ctx_ptr_ptr_v(u32 r) +{ + return (r >> 0) & 0xfffffff; +} +static inline u32 gr_fecs_arb_ctx_ptr_target_s(void) +{ + return 2; +} +static inline u32 gr_fecs_arb_ctx_ptr_target_f(u32 v) +{ + return (v & 0x3) << 28; +} +static inline u32 gr_fecs_arb_ctx_ptr_target_m(void) +{ + return 0x3 << 28; +} +static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r) +{ + return (r >> 28) & 0x3; +} +static inline u32 gr_fecs_arb_ctx_cmd_r(void) +{ + return 0x00409a10; +} +static inline u32 gr_fecs_arb_ctx_cmd_cmd_s(void) +{ + return 5; +} +static inline u32 gr_fecs_arb_ctx_cmd_cmd_f(u32 v) +{ + return (v & 0x1f) << 0; +} +static inline u32 gr_fecs_arb_ctx_cmd_cmd_m(void) +{ + return 0x1f << 0; +} +static inline u32 gr_fecs_arb_ctx_cmd_cmd_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 gr_fecs_ctxsw_status_fe_0_r(void) +{ + return 0x00409c00; +} +static inline u32 gr_gpc0_gpccs_ctxsw_status_gpc_0_r(void) +{ + return 0x00502c04; +} +static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void) +{ + return 0x00502400; +} +static inline u32 gr_fecs_ctxsw_idlestate_r(void) +{ + return 0x00409420; +} +static inline u32 gr_fecs_feature_override_ecc_r(void) +{ + return 0x00409658; +} +static inline u32 gr_fecs_feature_override_ecc_sm_lrf_override_v(u32 r) +{ + return (r >> 3) & 0x1; +} +static inline u32 gr_fecs_feature_override_ecc_ltc_override_v(u32 r) +{ + return (r >> 15) & 0x1; +} +static inline u32 gr_fecs_feature_override_ecc_sm_lrf_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 gr_fecs_feature_override_ecc_ltc_v(u32 r) +{ + return (r >> 12) & 0x1; +} +static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void) +{ + return 0x00502420; +} +static inline u32 gr_rstr2d_gpc_map_r(u32 i) +{ + return 0x0040780c + i*4; +} +static inline u32 gr_rstr2d_map_table_cfg_r(void) +{ + return 0x004078bc; +} +static inline u32 gr_rstr2d_map_table_cfg_row_offset_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_rstr2d_map_table_cfg_num_entries_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_pd_hww_esr_r(void) +{ + return 0x00406018; +} +static inline u32 gr_pd_hww_esr_reset_active_f(void) +{ + return 0x40000000; +} +static inline u32 gr_pd_hww_esr_en_enable_f(void) +{ + return 0x80000000; +} +static inline u32 gr_pd_num_tpc_per_gpc_r(u32 i) +{ + return 0x00406028 + i*4; +} +static inline u32 gr_pd_num_tpc_per_gpc__size_1_v(void) +{ + return 0x00000004; +} +static inline u32 gr_pd_num_tpc_per_gpc_count0_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 gr_pd_num_tpc_per_gpc_count1_f(u32 v) +{ + return (v & 0xf) << 4; +} +static inline u32 gr_pd_num_tpc_per_gpc_count2_f(u32 v) +{ + return (v & 0xf) << 8; +} +static inline u32 gr_pd_num_tpc_per_gpc_count3_f(u32 v) +{ + return (v & 0xf) << 12; +} +static inline u32 gr_pd_num_tpc_per_gpc_count4_f(u32 v) +{ + return (v & 0xf) << 16; +} +static inline u32 gr_pd_num_tpc_per_gpc_count5_f(u32 v) +{ + return (v & 0xf) << 20; +} +static inline u32 gr_pd_num_tpc_per_gpc_count6_f(u32 v) +{ + return (v & 0xf) << 24; +} +static inline u32 gr_pd_num_tpc_per_gpc_count7_f(u32 v) +{ + return (v & 0xf) << 28; +} +static inline u32 gr_pd_ab_dist_cfg0_r(void) +{ + return 0x004064c0; +} +static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_en_f(void) +{ + return 0x80000000; +} +static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_dis_f(void) +{ + return 0x0; +} +static inline u32 gr_pd_ab_dist_cfg1_r(void) +{ + return 0x004064c4; +} +static inline u32 gr_pd_ab_dist_cfg1_max_batches_init_f(void) +{ + return 0xffff; +} +static inline u32 gr_pd_ab_dist_cfg1_max_output_f(u32 v) +{ + return (v & 0xffff) << 16; +} +static inline u32 gr_pd_ab_dist_cfg1_max_output_granularity_v(void) +{ + return 0x00000080; +} +static inline u32 gr_pd_ab_dist_cfg2_r(void) +{ + return 0x004064c8; +} +static inline u32 gr_pd_ab_dist_cfg2_token_limit_f(u32 v) +{ + return (v & 0x1fff) << 0; +} +static inline u32 gr_pd_ab_dist_cfg2_token_limit_init_v(void) +{ + return 0x00001680; +} +static inline u32 gr_pd_ab_dist_cfg2_state_limit_f(u32 v) +{ + return (v & 0x1fff) << 16; +} +static inline u32 gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(void) +{ + return 0x00000020; +} +static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void) +{ + return 0x00001680; +} +static inline u32 gr_pd_dist_skip_table_r(u32 i) +{ + return 0x004064d0 + i*4; +} +static inline u32 gr_pd_dist_skip_table__size_1_v(void) +{ + return 0x00000008; +} +static inline u32 gr_pd_dist_skip_table_gpc_4n0_mask_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_pd_dist_skip_table_gpc_4n1_mask_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_pd_dist_skip_table_gpc_4n2_mask_f(u32 v) +{ + return (v & 0xff) << 16; +} +static inline u32 gr_pd_dist_skip_table_gpc_4n3_mask_f(u32 v) +{ + return (v & 0xff) << 24; +} +static inline u32 gr_ds_debug_r(void) +{ + return 0x00405800; +} +static inline u32 gr_ds_debug_timeslice_mode_disable_f(void) +{ + return 0x0; +} +static inline u32 gr_ds_debug_timeslice_mode_enable_f(void) +{ + return 0x8000000; +} +static inline u32 gr_ds_zbc_color_r_r(void) +{ + return 0x00405804; +} +static inline u32 gr_ds_zbc_color_r_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_ds_zbc_color_g_r(void) +{ + return 0x00405808; +} +static inline u32 gr_ds_zbc_color_g_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_ds_zbc_color_b_r(void) +{ + return 0x0040580c; +} +static inline u32 gr_ds_zbc_color_b_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_ds_zbc_color_a_r(void) +{ + return 0x00405810; +} +static inline u32 gr_ds_zbc_color_a_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_ds_zbc_color_fmt_r(void) +{ + return 0x00405814; +} +static inline u32 gr_ds_zbc_color_fmt_val_f(u32 v) +{ + return (v & 0x7f) << 0; +} +static inline u32 gr_ds_zbc_color_fmt_val_invalid_f(void) +{ + return 0x0; +} +static inline u32 gr_ds_zbc_color_fmt_val_zero_v(void) +{ + return 0x00000001; +} +static inline u32 gr_ds_zbc_color_fmt_val_unorm_one_v(void) +{ + return 0x00000002; +} +static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void) +{ + return 0x00000004; +} +static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void) +{ + return 0x00000028; +} +static inline u32 gr_ds_zbc_z_r(void) +{ + return 0x00405818; +} +static inline u32 gr_ds_zbc_z_val_s(void) +{ + return 32; +} +static inline u32 gr_ds_zbc_z_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_ds_zbc_z_val_m(void) +{ + return 0xffffffff << 0; +} +static inline u32 gr_ds_zbc_z_val_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 gr_ds_zbc_z_val__init_v(void) +{ + return 0x00000000; +} +static inline u32 gr_ds_zbc_z_val__init_f(void) +{ + return 0x0; +} +static inline u32 gr_ds_zbc_z_fmt_r(void) +{ + return 0x0040581c; +} +static inline u32 gr_ds_zbc_z_fmt_val_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 gr_ds_zbc_z_fmt_val_invalid_f(void) +{ + return 0x0; +} +static inline u32 gr_ds_zbc_z_fmt_val_fp32_v(void) +{ + return 0x00000001; +} +static inline u32 gr_ds_zbc_tbl_index_r(void) +{ + return 0x00405820; +} +static inline u32 gr_ds_zbc_tbl_index_val_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 gr_ds_zbc_tbl_ld_r(void) +{ + return 0x00405824; +} +static inline u32 gr_ds_zbc_tbl_ld_select_c_f(void) +{ + return 0x0; +} +static inline u32 gr_ds_zbc_tbl_ld_select_z_f(void) +{ + return 0x1; +} +static inline u32 gr_ds_zbc_tbl_ld_action_write_f(void) +{ + return 0x0; +} +static inline u32 gr_ds_zbc_tbl_ld_trigger_active_f(void) +{ + return 0x4; +} +static inline u32 gr_ds_tga_constraintlogic_beta_r(void) +{ + return 0x00405830; +} +static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v) +{ + return (v & 0x3fffff) << 0; +} +static inline u32 gr_ds_tga_constraintlogic_alpha_r(void) +{ + return 0x0040585c; +} +static inline u32 gr_ds_tga_constraintlogic_alpha_cbsize_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_ds_hww_esr_r(void) +{ + return 0x00405840; +} +static inline u32 gr_ds_hww_esr_reset_s(void) +{ + return 1; +} +static inline u32 gr_ds_hww_esr_reset_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 gr_ds_hww_esr_reset_m(void) +{ + return 0x1 << 30; +} +static inline u32 gr_ds_hww_esr_reset_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 gr_ds_hww_esr_reset_task_v(void) +{ + return 0x00000001; +} +static inline u32 gr_ds_hww_esr_reset_task_f(void) +{ + return 0x40000000; +} +static inline u32 gr_ds_hww_esr_en_enabled_f(void) +{ + return 0x80000000; +} +static inline u32 gr_ds_hww_esr_2_r(void) +{ + return 0x00405848; +} +static inline u32 gr_ds_hww_esr_2_reset_s(void) +{ + return 1; +} +static inline u32 gr_ds_hww_esr_2_reset_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 gr_ds_hww_esr_2_reset_m(void) +{ + return 0x1 << 30; +} +static inline u32 gr_ds_hww_esr_2_reset_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 gr_ds_hww_esr_2_reset_task_v(void) +{ + return 0x00000001; +} +static inline u32 gr_ds_hww_esr_2_reset_task_f(void) +{ + return 0x40000000; +} +static inline u32 gr_ds_hww_esr_2_en_enabled_f(void) +{ + return 0x80000000; +} +static inline u32 gr_ds_hww_report_mask_r(void) +{ + return 0x00405844; +} +static inline u32 gr_ds_hww_report_mask_sph0_err_report_f(void) +{ + return 0x1; +} +static inline u32 gr_ds_hww_report_mask_sph1_err_report_f(void) +{ + return 0x2; +} +static inline u32 gr_ds_hww_report_mask_sph2_err_report_f(void) +{ + return 0x4; +} +static inline u32 gr_ds_hww_report_mask_sph3_err_report_f(void) +{ + return 0x8; +} +static inline u32 gr_ds_hww_report_mask_sph4_err_report_f(void) +{ + return 0x10; +} +static inline u32 gr_ds_hww_report_mask_sph5_err_report_f(void) +{ + return 0x20; +} +static inline u32 gr_ds_hww_report_mask_sph6_err_report_f(void) +{ + return 0x40; +} +static inline u32 gr_ds_hww_report_mask_sph7_err_report_f(void) +{ + return 0x80; +} +static inline u32 gr_ds_hww_report_mask_sph8_err_report_f(void) +{ + return 0x100; +} +static inline u32 gr_ds_hww_report_mask_sph9_err_report_f(void) +{ + return 0x200; +} +static inline u32 gr_ds_hww_report_mask_sph10_err_report_f(void) +{ + return 0x400; +} +static inline u32 gr_ds_hww_report_mask_sph11_err_report_f(void) +{ + return 0x800; +} +static inline u32 gr_ds_hww_report_mask_sph12_err_report_f(void) +{ + return 0x1000; +} +static inline u32 gr_ds_hww_report_mask_sph13_err_report_f(void) +{ + return 0x2000; +} +static inline u32 gr_ds_hww_report_mask_sph14_err_report_f(void) +{ + return 0x4000; +} +static inline u32 gr_ds_hww_report_mask_sph15_err_report_f(void) +{ + return 0x8000; +} +static inline u32 gr_ds_hww_report_mask_sph16_err_report_f(void) +{ + return 0x10000; +} +static inline u32 gr_ds_hww_report_mask_sph17_err_report_f(void) +{ + return 0x20000; +} +static inline u32 gr_ds_hww_report_mask_sph18_err_report_f(void) +{ + return 0x40000; +} +static inline u32 gr_ds_hww_report_mask_sph19_err_report_f(void) +{ + return 0x80000; +} +static inline u32 gr_ds_hww_report_mask_sph20_err_report_f(void) +{ + return 0x100000; +} +static inline u32 gr_ds_hww_report_mask_sph21_err_report_f(void) +{ + return 0x200000; +} +static inline u32 gr_ds_hww_report_mask_sph22_err_report_f(void) +{ + return 0x400000; +} +static inline u32 gr_ds_hww_report_mask_sph23_err_report_f(void) +{ + return 0x800000; +} +static inline u32 gr_ds_hww_report_mask_2_r(void) +{ + return 0x0040584c; +} +static inline u32 gr_ds_hww_report_mask_2_sph24_err_report_f(void) +{ + return 0x1; +} +static inline u32 gr_ds_num_tpc_per_gpc_r(u32 i) +{ + return 0x00405870 + i*4; +} +static inline u32 gr_scc_bundle_cb_base_r(void) +{ + return 0x00408004; +} +static inline u32 gr_scc_bundle_cb_base_addr_39_8_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_scc_bundle_cb_base_addr_39_8_align_bits_v(void) +{ + return 0x00000008; +} +static inline u32 gr_scc_bundle_cb_size_r(void) +{ + return 0x00408008; +} +static inline u32 gr_scc_bundle_cb_size_div_256b_f(u32 v) +{ + return (v & 0x7ff) << 0; +} +static inline u32 gr_scc_bundle_cb_size_div_256b__prod_v(void) +{ + return 0x00000030; +} +static inline u32 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(void) +{ + return 0x00000100; +} +static inline u32 gr_scc_bundle_cb_size_valid_false_v(void) +{ + return 0x00000000; +} +static inline u32 gr_scc_bundle_cb_size_valid_false_f(void) +{ + return 0x0; +} +static inline u32 gr_scc_bundle_cb_size_valid_true_f(void) +{ + return 0x80000000; +} +static inline u32 gr_scc_pagepool_base_r(void) +{ + return 0x0040800c; +} +static inline u32 gr_scc_pagepool_base_addr_39_8_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_scc_pagepool_base_addr_39_8_align_bits_v(void) +{ + return 0x00000008; +} +static inline u32 gr_scc_pagepool_r(void) +{ + return 0x00408010; +} +static inline u32 gr_scc_pagepool_total_pages_f(u32 v) +{ + return (v & 0x3ff) << 0; +} +static inline u32 gr_scc_pagepool_total_pages_hwmax_v(void) +{ + return 0x00000000; +} +static inline u32 gr_scc_pagepool_total_pages_hwmax_value_v(void) +{ + return 0x00000200; +} +static inline u32 gr_scc_pagepool_total_pages_byte_granularity_v(void) +{ + return 0x00000100; +} +static inline u32 gr_scc_pagepool_max_valid_pages_s(void) +{ + return 10; +} +static inline u32 gr_scc_pagepool_max_valid_pages_f(u32 v) +{ + return (v & 0x3ff) << 10; +} +static inline u32 gr_scc_pagepool_max_valid_pages_m(void) +{ + return 0x3ff << 10; +} +static inline u32 gr_scc_pagepool_max_valid_pages_v(u32 r) +{ + return (r >> 10) & 0x3ff; +} +static inline u32 gr_scc_pagepool_valid_true_f(void) +{ + return 0x80000000; +} +static inline u32 gr_scc_init_r(void) +{ + return 0x0040802c; +} +static inline u32 gr_scc_init_ram_trigger_f(void) +{ + return 0x1; +} +static inline u32 gr_scc_hww_esr_r(void) +{ + return 0x00408030; +} +static inline u32 gr_scc_hww_esr_reset_active_f(void) +{ + return 0x40000000; +} +static inline u32 gr_scc_hww_esr_en_enable_f(void) +{ + return 0x80000000; +} +static inline u32 gr_sked_hww_esr_r(void) +{ + return 0x00407020; +} +static inline u32 gr_sked_hww_esr_reset_active_f(void) +{ + return 0x40000000; +} +static inline u32 gr_sked_hww_esr_en_r(void) +{ + return 0x00407024; +} +static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_m(void) +{ + return 0x1 << 25; +} +static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_enabled_f(void) +{ + return 0x2000000; +} +static inline u32 gr_cwd_fs_r(void) +{ + return 0x00405b00; +} +static inline u32 gr_cwd_fs_num_gpcs_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_cwd_fs_num_tpcs_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_cwd_gpc_tpc_id_r(u32 i) +{ + return 0x00405b60 + i*4; +} +static inline u32 gr_cwd_gpc_tpc_id_tpc0_s(void) +{ + return 4; +} +static inline u32 gr_cwd_gpc_tpc_id_tpc0_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 gr_cwd_gpc_tpc_id_gpc0_s(void) +{ + return 4; +} +static inline u32 gr_cwd_gpc_tpc_id_gpc0_f(u32 v) +{ + return (v & 0xf) << 4; +} +static inline u32 gr_cwd_gpc_tpc_id_tpc1_f(u32 v) +{ + return (v & 0xf) << 8; +} +static inline u32 gr_cwd_sm_id_r(u32 i) +{ + return 0x00405ba0 + i*4; +} +static inline u32 gr_cwd_sm_id__size_1_v(void) +{ + return 0x00000010; +} +static inline u32 gr_cwd_sm_id_tpc0_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_cwd_sm_id_tpc1_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_gpc0_fs_gpc_r(void) +{ + return 0x00502608; +} +static inline u32 gr_gpc0_fs_gpc_num_available_tpcs_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 gr_gpc0_fs_gpc_num_available_zculls_v(u32 r) +{ + return (r >> 16) & 0x1f; +} +static inline u32 gr_gpc0_cfg_r(void) +{ + return 0x00502620; +} +static inline u32 gr_gpc0_cfg_imem_sz_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 gr_gpccs_rc_lanes_r(void) +{ + return 0x00502880; +} +static inline u32 gr_gpccs_rc_lanes_num_chains_s(void) +{ + return 6; +} +static inline u32 gr_gpccs_rc_lanes_num_chains_f(u32 v) +{ + return (v & 0x3f) << 0; +} +static inline u32 gr_gpccs_rc_lanes_num_chains_m(void) +{ + return 0x3f << 0; +} +static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r) +{ + return (r >> 0) & 0x3f; +} +static inline u32 gr_gpccs_rc_lane_size_r(void) +{ + return 0x00502910; +} +static inline u32 gr_gpccs_rc_lane_size_v_s(void) +{ + return 24; +} +static inline u32 gr_gpccs_rc_lane_size_v_f(u32 v) +{ + return (v & 0xffffff) << 0; +} +static inline u32 gr_gpccs_rc_lane_size_v_m(void) +{ + return 0xffffff << 0; +} +static inline u32 gr_gpccs_rc_lane_size_v_v(u32 r) +{ + return (r >> 0) & 0xffffff; +} +static inline u32 gr_gpccs_rc_lane_size_v_0_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpccs_rc_lane_size_v_0_f(void) +{ + return 0x0; +} +static inline u32 gr_gpc0_zcull_fs_r(void) +{ + return 0x00500910; +} +static inline u32 gr_gpc0_zcull_fs_num_sms_f(u32 v) +{ + return (v & 0x1ff) << 0; +} +static inline u32 gr_gpc0_zcull_fs_num_active_banks_f(u32 v) +{ + return (v & 0xf) << 16; +} +static inline u32 gr_gpc0_zcull_ram_addr_r(void) +{ + return 0x00500914; +} +static inline u32 gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 gr_gpc0_zcull_ram_addr_row_offset_f(u32 v) +{ + return (v & 0xf) << 8; +} +static inline u32 gr_gpc0_zcull_sm_num_rcp_r(void) +{ + return 0x00500918; +} +static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative_f(u32 v) +{ + return (v & 0xffffff) << 0; +} +static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative__max_v(void) +{ + return 0x00800000; +} +static inline u32 gr_gpc0_zcull_total_ram_size_r(void) +{ + return 0x00500920; +} +static inline u32 gr_gpc0_zcull_total_ram_size_num_aliquots_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_gpc0_zcull_zcsize_r(u32 i) +{ + return 0x00500a04 + i*32; +} +static inline u32 gr_gpc0_zcull_zcsize_height_subregion__multiple_v(void) +{ + return 0x00000040; +} +static inline u32 gr_gpc0_zcull_zcsize_width_subregion__multiple_v(void) +{ + return 0x00000010; +} +static inline u32 gr_gpc0_gpm_pd_sm_id_r(u32 i) +{ + return 0x00500c10 + i*4; +} +static inline u32 gr_gpc0_gpm_pd_sm_id_id_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_r(u32 i) +{ + return 0x00500c30 + i*4; +} +static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 gr_gpc0_tpc0_pe_cfg_smid_r(void) +{ + return 0x00504088; +} +static inline u32 gr_gpc0_tpc0_pe_cfg_smid_value_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_gpc0_tpc0_sm_cfg_r(void) +{ + return 0x00504608; +} +static inline u32 gr_gpc0_tpc0_sm_cfg_tpc_id_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_gpc0_tpc0_sm_cfg_tpc_id_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_gpc0_tpc0_sm_arch_r(void) +{ + return 0x00504330; +} +static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 gr_gpc0_tpc0_sm_arch_spa_version_v(u32 r) +{ + return (r >> 8) & 0xfff; +} +static inline u32 gr_gpc0_tpc0_sm_arch_sm_version_v(u32 r) +{ + return (r >> 20) & 0xfff; +} +static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void) +{ + return 0x00503018; +} +static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f(void) +{ + return 0x1; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_r(void) +{ + return 0x005030c0; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_f(u32 v) +{ + return (v & 0x3fffff) << 0; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void) +{ + return 0x3fffff << 0; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void) +{ + return 0x00000480; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v(void) +{ + return 0x00000d10; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void) +{ + return 0x00000020; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_cb_offset_r(void) +{ + return 0x005030f4; +} +static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_r(void) +{ + return 0x005030e4; +} +static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(void) +{ + return 0xffff << 0; +} +static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(void) +{ + return 0x00000800; +} +static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v(void) +{ + return 0x00000020; +} +static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_offset_r(void) +{ + return 0x005030f8; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r(void) +{ + return 0x005030f0; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(u32 v) +{ + return (v & 0x3fffff) << 0; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(void) +{ + return 0x00000480; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_r(void) +{ + return 0x00419e00; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_r(void) +{ + return 0x00419e04; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_s(void) +{ + return 21; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(u32 v) +{ + return (v & 0x1fffff) << 0; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_m(void) +{ + return 0x1fffff << 0; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_v(u32 r) +{ + return (r >> 0) & 0x1fffff; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f(void) +{ + return 0x80; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_s(void) +{ + return 1; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_m(void) +{ + return 0x1 << 31; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f(void) +{ + return 0x80000000; +} +static inline u32 gr_gpccs_falcon_addr_r(void) +{ + return 0x0041a0ac; +} +static inline u32 gr_gpccs_falcon_addr_lsb_s(void) +{ + return 6; +} +static inline u32 gr_gpccs_falcon_addr_lsb_f(u32 v) +{ + return (v & 0x3f) << 0; +} +static inline u32 gr_gpccs_falcon_addr_lsb_m(void) +{ + return 0x3f << 0; +} +static inline u32 gr_gpccs_falcon_addr_lsb_v(u32 r) +{ + return (r >> 0) & 0x3f; +} +static inline u32 gr_gpccs_falcon_addr_lsb_init_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpccs_falcon_addr_lsb_init_f(void) +{ + return 0x0; +} +static inline u32 gr_gpccs_falcon_addr_msb_s(void) +{ + return 6; +} +static inline u32 gr_gpccs_falcon_addr_msb_f(u32 v) +{ + return (v & 0x3f) << 6; +} +static inline u32 gr_gpccs_falcon_addr_msb_m(void) +{ + return 0x3f << 6; +} +static inline u32 gr_gpccs_falcon_addr_msb_v(u32 r) +{ + return (r >> 6) & 0x3f; +} +static inline u32 gr_gpccs_falcon_addr_msb_init_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpccs_falcon_addr_msb_init_f(void) +{ + return 0x0; +} +static inline u32 gr_gpccs_falcon_addr_ext_s(void) +{ + return 12; +} +static inline u32 gr_gpccs_falcon_addr_ext_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 gr_gpccs_falcon_addr_ext_m(void) +{ + return 0xfff << 0; +} +static inline u32 gr_gpccs_falcon_addr_ext_v(u32 r) +{ + return (r >> 0) & 0xfff; +} +static inline u32 gr_gpccs_cpuctl_r(void) +{ + return 0x0041a100; +} +static inline u32 gr_gpccs_cpuctl_startcpu_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 gr_gpccs_dmactl_r(void) +{ + return 0x0041a10c; +} +static inline u32 gr_gpccs_dmactl_require_ctx_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 gr_gpccs_dmactl_dmem_scrubbing_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_gpccs_dmactl_imem_scrubbing_m(void) +{ + return 0x1 << 2; +} +static inline u32 gr_gpccs_imemc_r(u32 i) +{ + return 0x0041a180 + i*16; +} +static inline u32 gr_gpccs_imemc_offs_f(u32 v) +{ + return (v & 0x3f) << 2; +} +static inline u32 gr_gpccs_imemc_blk_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_gpccs_imemc_aincw_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 gr_gpccs_imemd_r(u32 i) +{ + return 0x0041a184 + i*16; +} +static inline u32 gr_gpccs_imemt_r(u32 i) +{ + return 0x0041a188 + i*16; +} +static inline u32 gr_gpccs_imemt__size_1_v(void) +{ + return 0x00000004; +} +static inline u32 gr_gpccs_imemt_tag_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_gpccs_dmemc_r(u32 i) +{ + return 0x0041a1c0 + i*8; +} +static inline u32 gr_gpccs_dmemc_offs_f(u32 v) +{ + return (v & 0x3f) << 2; +} +static inline u32 gr_gpccs_dmemc_blk_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_gpccs_dmemc_aincw_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 gr_gpccs_dmemd_r(u32 i) +{ + return 0x0041a1c4 + i*8; +} +static inline u32 gr_gpccs_ctxsw_mailbox_r(u32 i) +{ + return 0x0041a800 + i*4; +} +static inline u32 gr_gpccs_ctxsw_mailbox_value_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_swdx_bundle_cb_base_r(void) +{ + return 0x00418e24; +} +static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_s(void) +{ + return 32; +} +static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_m(void) +{ + return 0xffffffff << 0; +} +static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f(void) +{ + return 0x0; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_r(void) +{ + return 0x00418e28; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_s(void) +{ + return 11; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_f(u32 v) +{ + return (v & 0x7ff) << 0; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_m(void) +{ + return 0x7ff << 0; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_v(u32 r) +{ + return (r >> 0) & 0x7ff; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_v(void) +{ + return 0x00000030; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_f(void) +{ + return 0x30; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_s(void) +{ + return 1; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_m(void) +{ + return 0x1 << 31; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_f(void) +{ + return 0x0; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_f(void) +{ + return 0x80000000; +} +static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_r(void) +{ + return 0x005001dc; +} +static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v(void) +{ + return 0x000004b0; +} +static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(void) +{ + return 0x00000100; +} +static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_r(void) +{ + return 0x005001d8; +} +static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v(void) +{ + return 0x00000008; +} +static inline u32 gr_gpcs_swdx_beta_cb_ctrl_r(void) +{ + return 0x004181e4; +} +static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v(void) +{ + return 0x00000100; +} +static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_r(void) +{ + return 0x0041befc; +} +static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 gr_gpcs_swdx_tc_beta_cb_size_r(u32 i) +{ + return 0x00418ea0 + i*4; +} +static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_f(u32 v) +{ + return (v & 0x3fffff) << 0; +} +static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void) +{ + return 0x3fffff << 0; +} +static inline u32 gr_gpcs_swdx_dss_zbc_color_r_r(u32 i) +{ + return 0x00418010 + i*4; +} +static inline u32 gr_gpcs_swdx_dss_zbc_color_r_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_swdx_dss_zbc_color_g_r(u32 i) +{ + return 0x0041804c + i*4; +} +static inline u32 gr_gpcs_swdx_dss_zbc_color_g_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_swdx_dss_zbc_color_b_r(u32 i) +{ + return 0x00418088 + i*4; +} +static inline u32 gr_gpcs_swdx_dss_zbc_color_b_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_swdx_dss_zbc_color_a_r(u32 i) +{ + return 0x004180c4 + i*4; +} +static inline u32 gr_gpcs_swdx_dss_zbc_color_a_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r(void) +{ + return 0x00418100; +} +static inline u32 gr_gpcs_swdx_dss_zbc_z_r(u32 i) +{ + return 0x00418110 + i*4; +} +static inline u32 gr_gpcs_swdx_dss_zbc_z_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r(void) +{ + return 0x0041814c; +} +static inline u32 gr_gpcs_swdx_dss_zbc_s_r(u32 i) +{ + return 0x0041815c + i*4; +} +static inline u32 gr_gpcs_swdx_dss_zbc_s_val_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_gpcs_swdx_dss_zbc_s_01_to_04_format_r(void) +{ + return 0x00418198; +} +static inline u32 gr_gpcs_setup_attrib_cb_base_r(void) +{ + return 0x00418810; +} +static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v(void) +{ + return 0x0000000c; +} +static inline u32 gr_gpcs_setup_attrib_cb_base_valid_true_f(void) +{ + return 0x80000000; +} +static inline u32 gr_crstr_gpc_map_r(u32 i) +{ + return 0x00418b08 + i*4; +} +static inline u32 gr_crstr_gpc_map_tile0_f(u32 v) +{ + return (v & 0x1f) << 0; +} +static inline u32 gr_crstr_gpc_map_tile1_f(u32 v) +{ + return (v & 0x1f) << 5; +} +static inline u32 gr_crstr_gpc_map_tile2_f(u32 v) +{ + return (v & 0x1f) << 10; +} +static inline u32 gr_crstr_gpc_map_tile3_f(u32 v) +{ + return (v & 0x1f) << 15; +} +static inline u32 gr_crstr_gpc_map_tile4_f(u32 v) +{ + return (v & 0x1f) << 20; +} +static inline u32 gr_crstr_gpc_map_tile5_f(u32 v) +{ + return (v & 0x1f) << 25; +} +static inline u32 gr_crstr_map_table_cfg_r(void) +{ + return 0x00418bb8; +} +static inline u32 gr_crstr_map_table_cfg_row_offset_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_crstr_map_table_cfg_num_entries_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_r(u32 i) +{ + return 0x00418980 + i*4; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_0_f(u32 v) +{ + return (v & 0x7) << 0; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_1_f(u32 v) +{ + return (v & 0x7) << 4; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_2_f(u32 v) +{ + return (v & 0x7) << 8; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_3_f(u32 v) +{ + return (v & 0x7) << 12; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_4_f(u32 v) +{ + return (v & 0x7) << 16; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_5_f(u32 v) +{ + return (v & 0x7) << 20; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_6_f(u32 v) +{ + return (v & 0x7) << 24; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_7_f(u32 v) +{ + return (v & 0x7) << 28; +} +static inline u32 gr_gpcs_gpm_pd_cfg_r(void) +{ + return 0x00418c6c; +} +static inline u32 gr_gpcs_gcc_pagepool_base_r(void) +{ + return 0x00419004; +} +static inline u32 gr_gpcs_gcc_pagepool_base_addr_39_8_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_gcc_pagepool_r(void) +{ + return 0x00419008; +} +static inline u32 gr_gpcs_gcc_pagepool_total_pages_f(u32 v) +{ + return (v & 0x3ff) << 0; +} +static inline u32 gr_gpcs_tpcs_pe_vaf_r(void) +{ + return 0x0041980c; +} +static inline u32 gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f(void) +{ + return 0x10; +} +static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r(void) +{ + return 0x00419848; +} +static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(u32 v) +{ + return (v & 0x1) << 28; +} +static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f(void) +{ + return 0x10000000; +} +static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_r(void) +{ + return 0x00419c00; +} +static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f(void) +{ + return 0x8; +} +static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r(void) +{ + return 0x00419c2c; +} +static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(u32 v) +{ + return (v & 0x1) << 28; +} +static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void) +{ + return 0x10000000; +} +static inline u32 gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r(void) +{ + return 0x00419ea8; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_r(void) +{ + return 0x00504728; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_stack_error_report_f(void) +{ + return 0x2; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_api_stack_error_report_f(void) +{ + return 0x4; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_pc_wrap_report_f(void) +{ + return 0x10; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_pc_report_f(void) +{ + return 0x20; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_pc_overflow_report_f(void) +{ + return 0x40; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_reg_report_f(void) +{ + return 0x100; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void) +{ + return 0x200; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_param_report_f(void) +{ + return 0x800; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_reg_report_f(void) +{ + return 0x2000; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_addr_report_f(void) +{ + return 0x4000; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_addr_report_f(void) +{ + return 0x8000; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_addr_space_report_f(void) +{ + return 0x10000; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void) +{ + return 0x40000; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_mmu_fault_report_f(void) +{ + return 0x800000; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_stack_overflow_report_f(void) +{ + return 0x400000; +} +static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void) +{ + return 0x00419d0c; +} +static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f(void) +{ + return 0x2; +} +static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f(void) +{ + return 0x1; +} +static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_mpc_enabled_f(void) +{ + return 0x10; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void) +{ + return 0x0050450c; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void) +{ + return 0x2; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_mpc_enabled_f(void) +{ + return 0x10; +} +static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void) +{ + return 0x0041ac94; +} +static inline u32 gr_gpcs_gpccs_gpc_exception_en_gcc_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v) +{ + return (v & 0xff) << 16; +} +static inline u32 gr_gpc0_gpccs_gpc_exception_r(void) +{ + return 0x00502c90; +} +static inline u32 gr_gpc0_gpccs_gpc_exception_gcc_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r) +{ + return (r >> 16) & 0xff; +} +static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void) +{ + return 0x00504508; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_pending_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_mpc_m(void) +{ + return 0x1 << 4; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_mpc_pending_f(void) +{ + return 0x10; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_r(void) +{ + return 0x00504704; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_f(void) +{ + return 0x1; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_f(void) +{ + return 0x0; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_m(void) +{ + return 0x1 << 31; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_enable_f(void) +{ + return 0x80000000; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_disable_f(void) +{ + return 0x0; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_m(void) +{ + return 0x1 << 3; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_enable_f(void) +{ + return 0x8; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_disable_f(void) +{ + return 0x0; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_run_trigger_task_f(void) +{ + return 0x40000000; +} +static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_0_r(void) +{ + return 0x00504708; +} +static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_1_r(void) +{ + return 0x0050470c; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_0_r(void) +{ + return 0x00504710; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_1_r(void) +{ + return 0x00504714; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_0_r(void) +{ + return 0x00504718; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_1_r(void) +{ + return 0x0050471c; +} +static inline u32 gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_0_r(void) +{ + return 0x00419e90; +} +static inline u32 gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_1_r(void) +{ + return 0x00419e94; +} +static inline u32 gr_gpcs_tpcs_sms_dbgr_status0_r(void) +{ + return 0x00419e80; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_r(void) +{ + return 0x00504700; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_sm_in_trap_mode_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_v(u32 r) +{ + return (r >> 4) & 0x1; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_true_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_r(void) +{ + return 0x00504730; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_f(void) +{ + return 0x0; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_wrap_id_m(void) +{ + return 0xff << 16; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_m(void) +{ + return 0xf << 24; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_none_f(void) +{ + return 0x0; +} +static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_r(void) +{ + return 0x0050460c; +} +static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm0_error_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm1_error_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_pc_r(void) +{ + return 0x00504738; +} +static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void) +{ + return 0x005043a0; +} +static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void) +{ + return 0x00419ba0; +} +static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void) +{ + return 0x1 << 4; +} +static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 gr_gpc0_tpc0_sm_debug_sfe_control_r(void) +{ + return 0x005043b0; +} +static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void) +{ + return 0x00419bb0; +} +static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void) +{ + return 0x0041be08; +} +static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f(void) +{ + return 0x4; +} +static inline u32 gr_ppcs_wwdx_map_gpc_map_r(u32 i) +{ + return 0x0041bf00 + i*4; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void) +{ + return 0x0041bfd0; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_row_offset_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_num_entries_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(u32 v) +{ + return (v & 0x1f) << 16; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(u32 v) +{ + return (v & 0x7) << 21; +} +static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_r(void) +{ + return 0x0041bfd4; +} +static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(u32 v) +{ + return (v & 0xffffff) << 0; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_r(u32 i) +{ + return 0x0041bfb0 + i*4; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff__size_1_v(void) +{ + return 0x00000005; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_0_mod_value_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_1_mod_value_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_2_mod_value_f(u32 v) +{ + return (v & 0xff) << 16; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_3_mod_value_f(u32 v) +{ + return (v & 0xff) << 24; +} +static inline u32 gr_bes_zrop_settings_r(void) +{ + return 0x00408850; +} +static inline u32 gr_bes_zrop_settings_num_active_ltcs_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 gr_be0_crop_debug3_r(void) +{ + return 0x00410108; +} +static inline u32 gr_bes_crop_debug3_r(void) +{ + return 0x00408908; +} +static inline u32 gr_bes_crop_debug3_comp_vdc_4to2_disable_m(void) +{ + return 0x1 << 31; +} +static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_enabled_f(void) +{ + return 0x2; +} +static inline u32 gr_bes_crop_debug3_blendopt_fill_override_m(void) +{ + return 0x1 << 2; +} +static inline u32 gr_bes_crop_debug3_blendopt_fill_override_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_bes_crop_debug3_blendopt_fill_override_enabled_f(void) +{ + return 0x4; +} +static inline u32 gr_bes_crop_settings_r(void) +{ + return 0x00408958; +} +static inline u32 gr_bes_crop_settings_num_active_ltcs_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 gr_zcull_bytes_per_aliquot_per_gpu_v(void) +{ + return 0x00000020; +} +static inline u32 gr_zcull_save_restore_header_bytes_per_gpc_v(void) +{ + return 0x00000020; +} +static inline u32 gr_zcull_save_restore_subregion_header_bytes_per_gpc_v(void) +{ + return 0x000000c0; +} +static inline u32 gr_zcull_subregion_qty_v(void) +{ + return 0x00000010; +} +static inline u32 gr_gpcs_tpcs_tex_in_dbg_r(void) +{ + return 0x00419a00; +} +static inline u32 gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_f(u32 v) +{ + return (v & 0x1) << 19; +} +static inline u32 gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_m(void) +{ + return 0x1 << 19; +} +static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_r(void) +{ + return 0x00419bf0; +} +static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_m(void) +{ + return 0x1 << 5; +} +static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_f(u32 v) +{ + return (v & 0x1) << 10; +} +static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_m(void) +{ + return 0x1 << 10; +} +static inline u32 gr_fe_pwr_mode_r(void) +{ + return 0x00404170; +} +static inline u32 gr_fe_pwr_mode_mode_auto_f(void) +{ + return 0x0; +} +static inline u32 gr_fe_pwr_mode_mode_force_on_f(void) +{ + return 0x2; +} +static inline u32 gr_fe_pwr_mode_req_v(u32 r) +{ + return (r >> 4) & 0x1; +} +static inline u32 gr_fe_pwr_mode_req_send_f(void) +{ + return 0x10; +} +static inline u32 gr_fe_pwr_mode_req_done_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_r(void) +{ + return 0x00418880; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_vm_pg_size_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m(void) +{ + return 0x1 << 11; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_vol_fault_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_comp_fault_m(void) +{ + return 0x1 << 2; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_miss_gran_m(void) +{ + return 0x3 << 3; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_cache_mode_m(void) +{ + return 0x3 << 5; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_aperture_m(void) +{ + return 0x3 << 28; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_vol_m(void) +{ + return 0x1 << 30; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void) +{ + return 0x1 << 31; +} +static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void) +{ + return 0x00418890; +} +static inline u32 gr_gpcs_pri_mmu_pm_req_mask_r(void) +{ + return 0x00418894; +} +static inline u32 gr_gpcs_pri_mmu_debug_ctrl_r(void) +{ + return 0x004188b0; +} +static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_v(u32 r) +{ + return (r >> 16) & 0x1; +} +static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpcs_pri_mmu_debug_wr_r(void) +{ + return 0x004188b4; +} +static inline u32 gr_gpcs_pri_mmu_debug_rd_r(void) +{ + return 0x004188b8; +} +static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void) +{ + return 0x004188ac; +} +static inline u32 gr_gpcs_tpcs_sms_dbgr_control0_r(void) +{ + return 0x00419e84; +} +static inline u32 gr_fe_gfxp_wfi_timeout_r(void) +{ + return 0x004041c0; +} +static inline u32 gr_fe_gfxp_wfi_timeout_count_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_fe_gfxp_wfi_timeout_count_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_gpcs_tpcs_sm_texio_control_r(void) +{ + return 0x00419bd8; +} +static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(u32 v) +{ + return (v & 0x7) << 8; +} +static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m(void) +{ + return 0x7 << 8; +} +static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f(void) +{ + return 0x100; +} +static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_r(void) +{ + return 0x00419ba4; +} +static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(void) +{ + return 0x3 << 11; +} +static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f(void) +{ + return 0x1000; +} +static inline u32 gr_gpcs_tc_debug0_r(void) +{ + return 0x00418708; +} +static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(u32 v) +{ + return (v & 0x1ff) << 0; +} +static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(void) +{ + return 0x1ff << 0; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ltc_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ltc_gv100.h new file mode 100644 index 00000000..f1d977d4 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ltc_gv100.h @@ -0,0 +1,613 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_ltc_gv100_h_ +#define _hw_ltc_gv100_h_ + +static inline u32 ltc_pltcg_base_v(void) +{ + return 0x00140000; +} +static inline u32 ltc_pltcg_extent_v(void) +{ + return 0x0017ffff; +} +static inline u32 ltc_ltc0_ltss_v(void) +{ + return 0x00140200; +} +static inline u32 ltc_ltc0_lts0_v(void) +{ + return 0x00140400; +} +static inline u32 ltc_ltcs_ltss_v(void) +{ + return 0x0017e200; +} +static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void) +{ + return 0x0014046c; +} +static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void) +{ + return 0x00140518; +} +static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void) +{ + return 0x0017e318; +} +static inline u32 ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m(void) +{ + return 0x1 << 15; +} +static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void) +{ + return 0x00140494; +} +static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r) +{ + return (r >> 16) & 0x3; +} +static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void) +{ + return 0x00000000; +} +static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void) +{ + return 0x00000002; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void) +{ + return 0x0017e26c; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void) +{ + return 0x2; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void) +{ + return 0x4; +} +static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void) +{ + return 0x0014046c; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void) +{ + return 0x0017e270; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v) +{ + return (v & 0x3ffff) << 0; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void) +{ + return 0x0017e274; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v) +{ + return (v & 0x3ffff) << 0; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void) +{ + return 0x0003ffff; +} +static inline u32 ltc_ltcs_ltss_cbc_base_r(void) +{ + return 0x0017e278; +} +static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void) +{ + return 0x0000000b; +} +static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r) +{ + return (r >> 0) & 0x3ffffff; +} +static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_r(void) +{ + return 0x0017e27c; +} +static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs__v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_v(u32 r) +{ + return (r >> 24) & 0x1; +} +static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_f(u32 v) +{ + return (v & 0x1) << 25; +} +static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_v(u32 r) +{ + return (r >> 25) & 0x1; +} +static inline u32 ltc_ltcs_misc_ltc_num_active_ltcs_r(void) +{ + return 0x0017e000; +} +static inline u32 ltc_ltcs_ltss_cbc_param_r(void) +{ + return 0x0017e280; +} +static inline u32 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 ltc_ltcs_ltss_cbc_param_cache_line_size_v(u32 r) +{ + return (r >> 24) & 0xf; +} +static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(u32 r) +{ + return (r >> 28) & 0xf; +} +static inline u32 ltc_ltcs_ltss_cbc_param2_r(void) +{ + return 0x0017e3f4; +} +static inline u32 ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void) +{ + return 0x0017e2ac; +} +static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v) +{ + return (v & 0x1f) << 16; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void) +{ + return 0x0017e338; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i) +{ + return 0x0017e33c + i*4; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void) +{ + return 0x00000004; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void) +{ + return 0x0017e34c; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void) +{ + return 32; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void) +{ + return 0xffffffff << 0; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_r(void) +{ + return 0x0017e204; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_s(void) +{ + return 8; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_m(void) +{ + return 0xff << 0; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void) +{ + return 0x0017e2b0; +} +static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void) +{ + return 0x10000000; +} +static inline u32 ltc_ltcs_ltss_g_elpg_r(void) +{ + return 0x0017e214; +} +static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltc0_ltss_g_elpg_r(void) +{ + return 0x00140214; +} +static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltc1_ltss_g_elpg_r(void) +{ + return 0x00142214; +} +static inline u32 ltc_ltc1_ltss_g_elpg_flush_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltcs_ltss_intr_r(void) +{ + return 0x0017e20c; +} +static inline u32 ltc_ltcs_ltss_intr_ecc_sec_error_pending_f(void) +{ + return 0x100; +} +static inline u32 ltc_ltcs_ltss_intr_ecc_ded_error_pending_f(void) +{ + return 0x200; +} +static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void) +{ + return 0x1 << 20; +} +static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(void) +{ + return 0x1 << 30; +} +static inline u32 ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f(void) +{ + return 0x1000000; +} +static inline u32 ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f(void) +{ + return 0x2000000; +} +static inline u32 ltc_ltc0_lts0_intr_r(void) +{ + return 0x0014040c; +} +static inline u32 ltc_ltc0_lts0_dstg_ecc_report_r(void) +{ + return 0x0014051c; +} +static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_m(void) +{ + return 0xff << 0; +} +static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_m(void) +{ + return 0xff << 16; +} +static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(u32 r) +{ + return (r >> 16) & 0xff; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void) +{ + return 0x0017e2a0; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r) +{ + return (r >> 8) & 0xf; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void) +{ + return 0x00000003; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void) +{ + return 0x300; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r) +{ + return (r >> 28) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void) +{ + return 0x10000000; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r) +{ + return (r >> 29) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void) +{ + return 0x20000000; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void) +{ + return 0x40000000; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void) +{ + return 0x0017e2a4; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r) +{ + return (r >> 8) & 0xf; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void) +{ + return 0x00000003; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void) +{ + return 0x300; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r) +{ + return (r >> 16) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void) +{ + return 0x10000; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r) +{ + return (r >> 28) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void) +{ + return 0x10000000; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r) +{ + return (r >> 29) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void) +{ + return 0x20000000; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void) +{ + return 0x40000000; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void) +{ + return 0x001402a0; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void) +{ + return 0x001402a4; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_r(void) +{ + return 0x001422a0; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_r(void) +{ + return 0x001422a4; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltc0_lts0_tstg_info_1_r(void) +{ + return 0x0014058c; +} +static inline u32 ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(u32 r) +{ + return (r >> 16) & 0x1f; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h new file mode 100644 index 00000000..0cd59c3b --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h @@ -0,0 +1,245 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_mc_gv100_h_ +#define _hw_mc_gv100_h_ + +static inline u32 mc_boot_0_r(void) +{ + return 0x00000000; +} +static inline u32 mc_boot_0_architecture_v(u32 r) +{ + return (r >> 24) & 0x1f; +} +static inline u32 mc_boot_0_implementation_v(u32 r) +{ + return (r >> 20) & 0xf; +} +static inline u32 mc_boot_0_major_revision_v(u32 r) +{ + return (r >> 4) & 0xf; +} +static inline u32 mc_boot_0_minor_revision_v(u32 r) +{ + return (r >> 0) & 0xf; +} +static inline u32 mc_intr_r(u32 i) +{ + return 0x00000100 + i*4; +} +static inline u32 mc_intr_pfifo_pending_f(void) +{ + return 0x100; +} +static inline u32 mc_intr_hub_pending_f(void) +{ + return 0x200; +} +static inline u32 mc_intr_pgraph_pending_f(void) +{ + return 0x1000; +} +static inline u32 mc_intr_pmu_pending_f(void) +{ + return 0x1000000; +} +static inline u32 mc_intr_ltc_pending_f(void) +{ + return 0x2000000; +} +static inline u32 mc_intr_priv_ring_pending_f(void) +{ + return 0x40000000; +} +static inline u32 mc_intr_pbus_pending_f(void) +{ + return 0x10000000; +} +static inline u32 mc_intr_en_r(u32 i) +{ + return 0x00000140 + i*4; +} +static inline u32 mc_intr_en_set_r(u32 i) +{ + return 0x00000160 + i*4; +} +static inline u32 mc_intr_en_clear_r(u32 i) +{ + return 0x00000180 + i*4; +} +static inline u32 mc_enable_r(void) +{ + return 0x00000200; +} +static inline u32 mc_enable_xbar_enabled_f(void) +{ + return 0x4; +} +static inline u32 mc_enable_l2_enabled_f(void) +{ + return 0x8; +} +static inline u32 mc_enable_pmedia_s(void) +{ + return 1; +} +static inline u32 mc_enable_pmedia_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 mc_enable_pmedia_m(void) +{ + return 0x1 << 4; +} +static inline u32 mc_enable_pmedia_v(u32 r) +{ + return (r >> 4) & 0x1; +} +static inline u32 mc_enable_ce0_m(void) +{ + return 0x1 << 6; +} +static inline u32 mc_enable_pfifo_enabled_f(void) +{ + return 0x100; +} +static inline u32 mc_enable_pgraph_enabled_f(void) +{ + return 0x1000; +} +static inline u32 mc_enable_pwr_v(u32 r) +{ + return (r >> 13) & 0x1; +} +static inline u32 mc_enable_pwr_disabled_v(void) +{ + return 0x00000000; +} +static inline u32 mc_enable_pwr_enabled_f(void) +{ + return 0x2000; +} +static inline u32 mc_enable_pfb_enabled_f(void) +{ + return 0x100000; +} +static inline u32 mc_enable_ce2_m(void) +{ + return 0x1 << 21; +} +static inline u32 mc_enable_ce2_enabled_f(void) +{ + return 0x200000; +} +static inline u32 mc_enable_blg_enabled_f(void) +{ + return 0x8000000; +} +static inline u32 mc_enable_perfmon_enabled_f(void) +{ + return 0x10000000; +} +static inline u32 mc_enable_hub_enabled_f(void) +{ + return 0x20000000; +} +static inline u32 mc_intr_ltc_r(void) +{ + return 0x000001c0; +} +static inline u32 mc_enable_pb_r(void) +{ + return 0x00000204; +} +static inline u32 mc_enable_pb_0_s(void) +{ + return 1; +} +static inline u32 mc_enable_pb_0_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 mc_enable_pb_0_m(void) +{ + return 0x1 << 0; +} +static inline u32 mc_enable_pb_0_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 mc_enable_pb_0_enabled_v(void) +{ + return 0x00000001; +} +static inline u32 mc_enable_pb_sel_f(u32 v, u32 i) +{ + return (v & 0x1) << (0 + i*1); +} +static inline u32 mc_elpg_enable_r(void) +{ + return 0x0000020c; +} +static inline u32 mc_elpg_enable_xbar_enabled_f(void) +{ + return 0x4; +} +static inline u32 mc_elpg_enable_pfb_enabled_f(void) +{ + return 0x100000; +} +static inline u32 mc_elpg_enable_hub_enabled_f(void) +{ + return 0x20000000; +} +static inline u32 mc_elpg_enable_l2_enabled_f(void) +{ + return 0x8; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h new file mode 100644 index 00000000..ab363e94 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h @@ -0,0 +1,645 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_pbdma_gv100_h_ +#define _hw_pbdma_gv100_h_ + +static inline u32 pbdma_gp_entry1_r(void) +{ + return 0x10000004; +} +static inline u32 pbdma_gp_entry1_get_hi_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 pbdma_gp_entry1_length_f(u32 v) +{ + return (v & 0x1fffff) << 10; +} +static inline u32 pbdma_gp_entry1_length_v(u32 r) +{ + return (r >> 10) & 0x1fffff; +} +static inline u32 pbdma_gp_base_r(u32 i) +{ + return 0x00040048 + i*8192; +} +static inline u32 pbdma_gp_base__size_1_v(void) +{ + return 0x0000000e; +} +static inline u32 pbdma_gp_base_offset_f(u32 v) +{ + return (v & 0x1fffffff) << 3; +} +static inline u32 pbdma_gp_base_rsvd_s(void) +{ + return 3; +} +static inline u32 pbdma_gp_base_hi_r(u32 i) +{ + return 0x0004004c + i*8192; +} +static inline u32 pbdma_gp_base_hi_offset_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 pbdma_gp_base_hi_limit2_f(u32 v) +{ + return (v & 0x1f) << 16; +} +static inline u32 pbdma_gp_fetch_r(u32 i) +{ + return 0x00040050 + i*8192; +} +static inline u32 pbdma_gp_get_r(u32 i) +{ + return 0x00040014 + i*8192; +} +static inline u32 pbdma_gp_put_r(u32 i) +{ + return 0x00040000 + i*8192; +} +static inline u32 pbdma_pb_fetch_r(u32 i) +{ + return 0x00040054 + i*8192; +} +static inline u32 pbdma_pb_fetch_hi_r(u32 i) +{ + return 0x00040058 + i*8192; +} +static inline u32 pbdma_get_r(u32 i) +{ + return 0x00040018 + i*8192; +} +static inline u32 pbdma_get_hi_r(u32 i) +{ + return 0x0004001c + i*8192; +} +static inline u32 pbdma_put_r(u32 i) +{ + return 0x0004005c + i*8192; +} +static inline u32 pbdma_put_hi_r(u32 i) +{ + return 0x00040060 + i*8192; +} +static inline u32 pbdma_pb_header_r(u32 i) +{ + return 0x00040084 + i*8192; +} +static inline u32 pbdma_pb_header_priv_user_f(void) +{ + return 0x0; +} +static inline u32 pbdma_pb_header_method_zero_f(void) +{ + return 0x0; +} +static inline u32 pbdma_pb_header_subchannel_zero_f(void) +{ + return 0x0; +} +static inline u32 pbdma_pb_header_level_main_f(void) +{ + return 0x0; +} +static inline u32 pbdma_pb_header_first_true_f(void) +{ + return 0x400000; +} +static inline u32 pbdma_pb_header_type_inc_f(void) +{ + return 0x20000000; +} +static inline u32 pbdma_pb_header_type_non_inc_f(void) +{ + return 0x60000000; +} +static inline u32 pbdma_hdr_shadow_r(u32 i) +{ + return 0x00040118 + i*8192; +} +static inline u32 pbdma_subdevice_r(u32 i) +{ + return 0x00040094 + i*8192; +} +static inline u32 pbdma_subdevice_id_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 pbdma_subdevice_status_active_f(void) +{ + return 0x10000000; +} +static inline u32 pbdma_subdevice_channel_dma_enable_f(void) +{ + return 0x20000000; +} +static inline u32 pbdma_method0_r(u32 i) +{ + return 0x000400c0 + i*8192; +} +static inline u32 pbdma_method0_fifo_size_v(void) +{ + return 0x00000004; +} +static inline u32 pbdma_method0_addr_f(u32 v) +{ + return (v & 0xfff) << 2; +} +static inline u32 pbdma_method0_addr_v(u32 r) +{ + return (r >> 2) & 0xfff; +} +static inline u32 pbdma_method0_subch_v(u32 r) +{ + return (r >> 16) & 0x7; +} +static inline u32 pbdma_method0_first_true_f(void) +{ + return 0x400000; +} +static inline u32 pbdma_method0_valid_true_f(void) +{ + return 0x80000000; +} +static inline u32 pbdma_method1_r(u32 i) +{ + return 0x000400c8 + i*8192; +} +static inline u32 pbdma_method2_r(u32 i) +{ + return 0x000400d0 + i*8192; +} +static inline u32 pbdma_method3_r(u32 i) +{ + return 0x000400d8 + i*8192; +} +static inline u32 pbdma_data0_r(u32 i) +{ + return 0x000400c4 + i*8192; +} +static inline u32 pbdma_acquire_r(u32 i) +{ + return 0x00040030 + i*8192; +} +static inline u32 pbdma_acquire_retry_man_2_f(void) +{ + return 0x2; +} +static inline u32 pbdma_acquire_retry_exp_2_f(void) +{ + return 0x100; +} +static inline u32 pbdma_acquire_timeout_exp_f(u32 v) +{ + return (v & 0xf) << 11; +} +static inline u32 pbdma_acquire_timeout_exp_max_v(void) +{ + return 0x0000000f; +} +static inline u32 pbdma_acquire_timeout_exp_max_f(void) +{ + return 0x7800; +} +static inline u32 pbdma_acquire_timeout_man_f(u32 v) +{ + return (v & 0xffff) << 15; +} +static inline u32 pbdma_acquire_timeout_man_max_v(void) +{ + return 0x0000ffff; +} +static inline u32 pbdma_acquire_timeout_man_max_f(void) +{ + return 0x7fff8000; +} +static inline u32 pbdma_acquire_timeout_en_enable_f(void) +{ + return 0x80000000; +} +static inline u32 pbdma_acquire_timeout_en_disable_f(void) +{ + return 0x0; +} +static inline u32 pbdma_status_r(u32 i) +{ + return 0x00040100 + i*8192; +} +static inline u32 pbdma_channel_r(u32 i) +{ + return 0x00040120 + i*8192; +} +static inline u32 pbdma_signature_r(u32 i) +{ + return 0x00040010 + i*8192; +} +static inline u32 pbdma_signature_hw_valid_f(void) +{ + return 0xface; +} +static inline u32 pbdma_signature_sw_zero_f(void) +{ + return 0x0; +} +static inline u32 pbdma_userd_r(u32 i) +{ + return 0x00040008 + i*8192; +} +static inline u32 pbdma_userd_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 pbdma_userd_target_sys_mem_coh_f(void) +{ + return 0x2; +} +static inline u32 pbdma_userd_target_sys_mem_ncoh_f(void) +{ + return 0x3; +} +static inline u32 pbdma_userd_addr_f(u32 v) +{ + return (v & 0x7fffff) << 9; +} +static inline u32 pbdma_config_r(u32 i) +{ + return 0x000400f4 + i*8192; +} +static inline u32 pbdma_config_l2_evict_first_f(void) +{ + return 0x0; +} +static inline u32 pbdma_config_l2_evict_normal_f(void) +{ + return 0x1; +} +static inline u32 pbdma_config_l2_evict_last_f(void) +{ + return 0x2; +} +static inline u32 pbdma_config_ce_split_enable_f(void) +{ + return 0x0; +} +static inline u32 pbdma_config_ce_split_disable_f(void) +{ + return 0x10; +} +static inline u32 pbdma_config_auth_level_non_privileged_f(void) +{ + return 0x0; +} +static inline u32 pbdma_config_auth_level_privileged_f(void) +{ + return 0x100; +} +static inline u32 pbdma_config_userd_writeback_disable_f(void) +{ + return 0x0; +} +static inline u32 pbdma_config_userd_writeback_enable_f(void) +{ + return 0x1000; +} +static inline u32 pbdma_userd_hi_r(u32 i) +{ + return 0x0004000c + i*8192; +} +static inline u32 pbdma_userd_hi_addr_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 pbdma_hce_ctrl_r(u32 i) +{ + return 0x000400e4 + i*8192; +} +static inline u32 pbdma_hce_ctrl_hce_priv_mode_yes_f(void) +{ + return 0x20; +} +static inline u32 pbdma_intr_0_r(u32 i) +{ + return 0x00040108 + i*8192; +} +static inline u32 pbdma_intr_0_memreq_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 pbdma_intr_0_memreq_pending_f(void) +{ + return 0x1; +} +static inline u32 pbdma_intr_0_memack_timeout_pending_f(void) +{ + return 0x2; +} +static inline u32 pbdma_intr_0_memack_extra_pending_f(void) +{ + return 0x4; +} +static inline u32 pbdma_intr_0_memdat_timeout_pending_f(void) +{ + return 0x8; +} +static inline u32 pbdma_intr_0_memdat_extra_pending_f(void) +{ + return 0x10; +} +static inline u32 pbdma_intr_0_memflush_pending_f(void) +{ + return 0x20; +} +static inline u32 pbdma_intr_0_memop_pending_f(void) +{ + return 0x40; +} +static inline u32 pbdma_intr_0_lbconnect_pending_f(void) +{ + return 0x80; +} +static inline u32 pbdma_intr_0_lbreq_pending_f(void) +{ + return 0x100; +} +static inline u32 pbdma_intr_0_lback_timeout_pending_f(void) +{ + return 0x200; +} +static inline u32 pbdma_intr_0_lback_extra_pending_f(void) +{ + return 0x400; +} +static inline u32 pbdma_intr_0_lbdat_timeout_pending_f(void) +{ + return 0x800; +} +static inline u32 pbdma_intr_0_lbdat_extra_pending_f(void) +{ + return 0x1000; +} +static inline u32 pbdma_intr_0_gpfifo_pending_f(void) +{ + return 0x2000; +} +static inline u32 pbdma_intr_0_gpptr_pending_f(void) +{ + return 0x4000; +} +static inline u32 pbdma_intr_0_gpentry_pending_f(void) +{ + return 0x8000; +} +static inline u32 pbdma_intr_0_gpcrc_pending_f(void) +{ + return 0x10000; +} +static inline u32 pbdma_intr_0_pbptr_pending_f(void) +{ + return 0x20000; +} +static inline u32 pbdma_intr_0_pbentry_pending_f(void) +{ + return 0x40000; +} +static inline u32 pbdma_intr_0_pbcrc_pending_f(void) +{ + return 0x80000; +} +static inline u32 pbdma_intr_0_clear_faulted_error_pending_f(void) +{ + return 0x100000; +} +static inline u32 pbdma_intr_0_method_pending_f(void) +{ + return 0x200000; +} +static inline u32 pbdma_intr_0_methodcrc_pending_f(void) +{ + return 0x400000; +} +static inline u32 pbdma_intr_0_device_pending_f(void) +{ + return 0x800000; +} +static inline u32 pbdma_intr_0_eng_reset_pending_f(void) +{ + return 0x1000000; +} +static inline u32 pbdma_intr_0_semaphore_pending_f(void) +{ + return 0x2000000; +} +static inline u32 pbdma_intr_0_acquire_pending_f(void) +{ + return 0x4000000; +} +static inline u32 pbdma_intr_0_pri_pending_f(void) +{ + return 0x8000000; +} +static inline u32 pbdma_intr_0_no_ctxsw_seg_pending_f(void) +{ + return 0x20000000; +} +static inline u32 pbdma_intr_0_pbseg_pending_f(void) +{ + return 0x40000000; +} +static inline u32 pbdma_intr_0_signature_pending_f(void) +{ + return 0x80000000; +} +static inline u32 pbdma_intr_1_r(u32 i) +{ + return 0x00040148 + i*8192; +} +static inline u32 pbdma_intr_1_ctxnotvalid_m(void) +{ + return 0x1 << 31; +} +static inline u32 pbdma_intr_1_ctxnotvalid_pending_f(void) +{ + return 0x80000000; +} +static inline u32 pbdma_intr_en_0_r(u32 i) +{ + return 0x0004010c + i*8192; +} +static inline u32 pbdma_intr_en_0_lbreq_enabled_f(void) +{ + return 0x100; +} +static inline u32 pbdma_intr_en_1_r(u32 i) +{ + return 0x0004014c + i*8192; +} +static inline u32 pbdma_intr_stall_r(u32 i) +{ + return 0x0004013c + i*8192; +} +static inline u32 pbdma_intr_stall_lbreq_enabled_f(void) +{ + return 0x100; +} +static inline u32 pbdma_intr_stall_1_r(u32 i) +{ + return 0x00040140 + i*8192; +} +static inline u32 pbdma_udma_nop_r(void) +{ + return 0x00000008; +} +static inline u32 pbdma_runlist_timeslice_r(u32 i) +{ + return 0x000400f8 + i*8192; +} +static inline u32 pbdma_runlist_timeslice_timeout_128_f(void) +{ + return 0x80; +} +static inline u32 pbdma_runlist_timeslice_timescale_3_f(void) +{ + return 0x3000; +} +static inline u32 pbdma_runlist_timeslice_enable_true_f(void) +{ + return 0x10000000; +} +static inline u32 pbdma_target_r(u32 i) +{ + return 0x000400ac + i*8192; +} +static inline u32 pbdma_target_engine_sw_f(void) +{ + return 0x1f; +} +static inline u32 pbdma_target_eng_ctx_valid_true_f(void) +{ + return 0x10000; +} +static inline u32 pbdma_target_eng_ctx_valid_false_f(void) +{ + return 0x0; +} +static inline u32 pbdma_target_ce_ctx_valid_true_f(void) +{ + return 0x20000; +} +static inline u32 pbdma_target_ce_ctx_valid_false_f(void) +{ + return 0x0; +} +static inline u32 pbdma_target_host_tsg_event_reason_pbdma_idle_f(void) +{ + return 0x0; +} +static inline u32 pbdma_target_host_tsg_event_reason_semaphore_acquire_failure_f(void) +{ + return 0x1000000; +} +static inline u32 pbdma_target_host_tsg_event_reason_tsg_yield_f(void) +{ + return 0x2000000; +} +static inline u32 pbdma_target_host_tsg_event_reason_host_subchannel_switch_f(void) +{ + return 0x3000000; +} +static inline u32 pbdma_target_should_send_tsg_event_true_f(void) +{ + return 0x20000000; +} +static inline u32 pbdma_target_should_send_tsg_event_false_f(void) +{ + return 0x0; +} +static inline u32 pbdma_target_needs_host_tsg_event_true_f(void) +{ + return 0x80000000; +} +static inline u32 pbdma_target_needs_host_tsg_event_false_f(void) +{ + return 0x0; +} +static inline u32 pbdma_set_channel_info_r(u32 i) +{ + return 0x000400fc + i*8192; +} +static inline u32 pbdma_set_channel_info_scg_type_graphics_compute0_f(void) +{ + return 0x0; +} +static inline u32 pbdma_set_channel_info_scg_type_compute1_f(void) +{ + return 0x1; +} +static inline u32 pbdma_set_channel_info_veid_f(u32 v) +{ + return (v & 0x3f) << 8; +} +static inline u32 pbdma_timeout_r(u32 i) +{ + return 0x0004012c + i*8192; +} +static inline u32 pbdma_timeout_period_m(void) +{ + return 0xffffffff << 0; +} +static inline u32 pbdma_timeout_period_max_f(void) +{ + return 0xffffffff; +} +static inline u32 pbdma_timeout_period_init_f(void) +{ + return 0x10000; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h new file mode 100644 index 00000000..f8e7c2a4 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h @@ -0,0 +1,205 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_perf_gv100_h_ +#define _hw_perf_gv100_h_ + +static inline u32 perf_pmasys_control_r(void) +{ + return 0x0024a000; +} +static inline u32 perf_pmasys_control_membuf_status_v(u32 r) +{ + return (r >> 4) & 0x1; +} +static inline u32 perf_pmasys_control_membuf_status_overflowed_v(void) +{ + return 0x00000001; +} +static inline u32 perf_pmasys_control_membuf_status_overflowed_f(void) +{ + return 0x10; +} +static inline u32 perf_pmasys_control_membuf_clear_status_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 perf_pmasys_control_membuf_clear_status_v(u32 r) +{ + return (r >> 5) & 0x1; +} +static inline u32 perf_pmasys_control_membuf_clear_status_doit_v(void) +{ + return 0x00000001; +} +static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void) +{ + return 0x20; +} +static inline u32 perf_pmasys_mem_block_r(void) +{ + return 0x0024a070; +} +static inline u32 perf_pmasys_mem_block_base_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 perf_pmasys_mem_block_target_f(u32 v) +{ + return (v & 0x3) << 28; +} +static inline u32 perf_pmasys_mem_block_target_v(u32 r) +{ + return (r >> 28) & 0x3; +} +static inline u32 perf_pmasys_mem_block_target_lfb_v(void) +{ + return 0x00000000; +} +static inline u32 perf_pmasys_mem_block_target_lfb_f(void) +{ + return 0x0; +} +static inline u32 perf_pmasys_mem_block_target_sys_coh_v(void) +{ + return 0x00000002; +} +static inline u32 perf_pmasys_mem_block_target_sys_coh_f(void) +{ + return 0x20000000; +} +static inline u32 perf_pmasys_mem_block_target_sys_ncoh_v(void) +{ + return 0x00000003; +} +static inline u32 perf_pmasys_mem_block_target_sys_ncoh_f(void) +{ + return 0x30000000; +} +static inline u32 perf_pmasys_mem_block_valid_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 perf_pmasys_mem_block_valid_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 perf_pmasys_mem_block_valid_true_v(void) +{ + return 0x00000001; +} +static inline u32 perf_pmasys_mem_block_valid_true_f(void) +{ + return 0x80000000; +} +static inline u32 perf_pmasys_mem_block_valid_false_v(void) +{ + return 0x00000000; +} +static inline u32 perf_pmasys_mem_block_valid_false_f(void) +{ + return 0x0; +} +static inline u32 perf_pmasys_outbase_r(void) +{ + return 0x0024a074; +} +static inline u32 perf_pmasys_outbase_ptr_f(u32 v) +{ + return (v & 0x7ffffff) << 5; +} +static inline u32 perf_pmasys_outbaseupper_r(void) +{ + return 0x0024a078; +} +static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 perf_pmasys_outsize_r(void) +{ + return 0x0024a07c; +} +static inline u32 perf_pmasys_outsize_numbytes_f(u32 v) +{ + return (v & 0x7ffffff) << 5; +} +static inline u32 perf_pmasys_mem_bytes_r(void) +{ + return 0x0024a084; +} +static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v) +{ + return (v & 0xfffffff) << 4; +} +static inline u32 perf_pmasys_mem_bump_r(void) +{ + return 0x0024a088; +} +static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v) +{ + return (v & 0xfffffff) << 4; +} +static inline u32 perf_pmasys_enginestatus_r(void) +{ + return 0x0024a0a4; +} +static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 perf_pmasys_enginestatus_rbufempty_empty_v(void) +{ + return 0x00000001; +} +static inline u32 perf_pmasys_enginestatus_rbufempty_empty_f(void) +{ + return 0x10; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pram_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pram_gv100.h new file mode 100644 index 00000000..88c70f53 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pram_gv100.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_pram_gv100_h_ +#define _hw_pram_gv100_h_ + +static inline u32 pram_data032_r(u32 i) +{ + return 0x00700000 + i*4; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h new file mode 100644 index 00000000..197fe550 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h @@ -0,0 +1,161 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_pri_ringmaster_gv100_h_ +#define _hw_pri_ringmaster_gv100_h_ + +static inline u32 pri_ringmaster_command_r(void) +{ + return 0x0012004c; +} +static inline u32 pri_ringmaster_command_cmd_m(void) +{ + return 0x3f << 0; +} +static inline u32 pri_ringmaster_command_cmd_v(u32 r) +{ + return (r >> 0) & 0x3f; +} +static inline u32 pri_ringmaster_command_cmd_no_cmd_v(void) +{ + return 0x00000000; +} +static inline u32 pri_ringmaster_command_cmd_start_ring_f(void) +{ + return 0x1; +} +static inline u32 pri_ringmaster_command_cmd_ack_interrupt_f(void) +{ + return 0x2; +} +static inline u32 pri_ringmaster_command_cmd_enumerate_stations_f(void) +{ + return 0x3; +} +static inline u32 pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f(void) +{ + return 0x0; +} +static inline u32 pri_ringmaster_command_data_r(void) +{ + return 0x00120048; +} +static inline u32 pri_ringmaster_start_results_r(void) +{ + return 0x00120050; +} +static inline u32 pri_ringmaster_start_results_connectivity_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 pri_ringmaster_start_results_connectivity_pass_v(void) +{ + return 0x00000001; +} +static inline u32 pri_ringmaster_intr_status0_r(void) +{ + return 0x00120058; +} +static inline u32 pri_ringmaster_intr_status0_ring_start_conn_fault_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 pri_ringmaster_intr_status0_disconnect_fault_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 pri_ringmaster_intr_status0_overflow_fault_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 pri_ringmaster_intr_status0_gbl_write_error_sys_v(u32 r) +{ + return (r >> 8) & 0x1; +} +static inline u32 pri_ringmaster_intr_status1_r(void) +{ + return 0x0012005c; +} +static inline u32 pri_ringmaster_global_ctl_r(void) +{ + return 0x00120060; +} +static inline u32 pri_ringmaster_global_ctl_ring_reset_asserted_f(void) +{ + return 0x1; +} +static inline u32 pri_ringmaster_global_ctl_ring_reset_deasserted_f(void) +{ + return 0x0; +} +static inline u32 pri_ringmaster_enum_fbp_r(void) +{ + return 0x00120074; +} +static inline u32 pri_ringmaster_enum_fbp_count_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 pri_ringmaster_enum_gpc_r(void) +{ + return 0x00120078; +} +static inline u32 pri_ringmaster_enum_gpc_count_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 pri_ringmaster_enum_ltc_r(void) +{ + return 0x0012006c; +} +static inline u32 pri_ringmaster_enum_ltc_count_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h new file mode 100644 index 00000000..eb77b4c0 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_pri_ringstation_gpc_gv100_h_ +#define _hw_pri_ringstation_gpc_gv100_h_ + +static inline u32 pri_ringstation_gpc_master_config_r(u32 i) +{ + return 0x00128300 + i*4; +} +static inline u32 pri_ringstation_gpc_gpc0_priv_error_adr_r(void) +{ + return 0x00128120; +} +static inline u32 pri_ringstation_gpc_gpc0_priv_error_wrdat_r(void) +{ + return 0x00128124; +} +static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_r(void) +{ + return 0x00128128; +} +static inline u32 pri_ringstation_gpc_gpc0_priv_error_code_r(void) +{ + return 0x0012812c; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h new file mode 100644 index 00000000..27feb5e9 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_pri_ringstation_sys_gv100_h_ +#define _hw_pri_ringstation_sys_gv100_h_ + +static inline u32 pri_ringstation_sys_master_config_r(u32 i) +{ + return 0x00122300 + i*4; +} +static inline u32 pri_ringstation_sys_decode_config_r(void) +{ + return 0x00122204; +} +static inline u32 pri_ringstation_sys_decode_config_ring_m(void) +{ + return 0x7 << 0; +} +static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void) +{ + return 0x1; +} +static inline u32 pri_ringstation_sys_priv_error_adr_r(void) +{ + return 0x00122120; +} +static inline u32 pri_ringstation_sys_priv_error_wrdat_r(void) +{ + return 0x00122124; +} +static inline u32 pri_ringstation_sys_priv_error_info_r(void) +{ + return 0x00122128; +} +static inline u32 pri_ringstation_sys_priv_error_code_r(void) +{ + return 0x0012212c; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h new file mode 100644 index 00000000..44e804e7 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h @@ -0,0 +1,161 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_proj_gv100_h_ +#define _hw_proj_gv100_h_ + +static inline u32 proj_gpc_base_v(void) +{ + return 0x00500000; +} +static inline u32 proj_gpc_shared_base_v(void) +{ + return 0x00418000; +} +static inline u32 proj_gpc_stride_v(void) +{ + return 0x00008000; +} +static inline u32 proj_ltc_stride_v(void) +{ + return 0x00002000; +} +static inline u32 proj_lts_stride_v(void) +{ + return 0x00000200; +} +static inline u32 proj_fbpa_stride_v(void) +{ + return 0x00004000; +} +static inline u32 proj_ppc_in_gpc_base_v(void) +{ + return 0x00003000; +} +static inline u32 proj_ppc_in_gpc_stride_v(void) +{ + return 0x00000200; +} +static inline u32 proj_rop_base_v(void) +{ + return 0x00410000; +} +static inline u32 proj_rop_shared_base_v(void) +{ + return 0x00408800; +} +static inline u32 proj_rop_stride_v(void) +{ + return 0x00000400; +} +static inline u32 proj_tpc_in_gpc_base_v(void) +{ + return 0x00004000; +} +static inline u32 proj_tpc_in_gpc_stride_v(void) +{ + return 0x00000800; +} +static inline u32 proj_tpc_in_gpc_shared_base_v(void) +{ + return 0x00001800; +} +static inline u32 proj_host_num_engines_v(void) +{ + return 0x0000000f; +} +static inline u32 proj_host_num_pbdma_v(void) +{ + return 0x0000000e; +} +static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void) +{ + return 0x00000007; +} +static inline u32 proj_scal_litter_num_fbps_v(void) +{ + return 0x00000008; +} +static inline u32 proj_scal_litter_num_fbpas_v(void) +{ + return 0x00000010; +} +static inline u32 proj_scal_litter_num_gpcs_v(void) +{ + return 0x00000006; +} +static inline u32 proj_scal_litter_num_pes_per_gpc_v(void) +{ + return 0x00000003; +} +static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void) +{ + return 0x00000003; +} +static inline u32 proj_scal_litter_num_zcull_banks_v(void) +{ + return 0x00000004; +} +static inline u32 proj_scal_litter_num_sm_per_tpc_v(void) +{ + return 0x00000002; +} +static inline u32 proj_scal_max_gpcs_v(void) +{ + return 0x00000020; +} +static inline u32 proj_scal_max_tpc_per_gpc_v(void) +{ + return 0x00000008; +} +static inline u32 proj_sm_stride_v(void) +{ + return 0x00000080; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h new file mode 100644 index 00000000..7d83b4ae --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h @@ -0,0 +1,929 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_pwr_gv100_h_ +#define _hw_pwr_gv100_h_ + +static inline u32 pwr_falcon_irqsset_r(void) +{ + return 0x0010a000; +} +static inline u32 pwr_falcon_irqsset_swgen0_set_f(void) +{ + return 0x40; +} +static inline u32 pwr_falcon_irqsclr_r(void) +{ + return 0x0010a004; +} +static inline u32 pwr_falcon_irqstat_r(void) +{ + return 0x0010a008; +} +static inline u32 pwr_falcon_irqstat_halt_true_f(void) +{ + return 0x10; +} +static inline u32 pwr_falcon_irqstat_exterr_true_f(void) +{ + return 0x20; +} +static inline u32 pwr_falcon_irqstat_swgen0_true_f(void) +{ + return 0x40; +} +static inline u32 pwr_falcon_irqstat_ext_second_true_f(void) +{ + return 0x800; +} +static inline u32 pwr_falcon_irqmode_r(void) +{ + return 0x0010a00c; +} +static inline u32 pwr_falcon_irqmset_r(void) +{ + return 0x0010a010; +} +static inline u32 pwr_falcon_irqmset_gptmr_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 pwr_falcon_irqmset_wdtmr_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 pwr_falcon_irqmset_mthd_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 pwr_falcon_irqmset_ctxsw_f(u32 v) +{ + return (v & 0x1) << 3; +} +static inline u32 pwr_falcon_irqmset_halt_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 pwr_falcon_irqmset_exterr_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 pwr_falcon_irqmset_swgen0_f(u32 v) +{ + return (v & 0x1) << 6; +} +static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v) +{ + return (v & 0x1) << 7; +} +static inline u32 pwr_falcon_irqmset_ext_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 pwr_falcon_irqmset_ext_ctxe_f(u32 v) +{ + return (v & 0x1) << 8; +} +static inline u32 pwr_falcon_irqmset_ext_limitv_f(u32 v) +{ + return (v & 0x1) << 9; +} +static inline u32 pwr_falcon_irqmset_ext_second_f(u32 v) +{ + return (v & 0x1) << 11; +} +static inline u32 pwr_falcon_irqmset_ext_therm_f(u32 v) +{ + return (v & 0x1) << 12; +} +static inline u32 pwr_falcon_irqmset_ext_miscio_f(u32 v) +{ + return (v & 0x1) << 13; +} +static inline u32 pwr_falcon_irqmset_ext_rttimer_f(u32 v) +{ + return (v & 0x1) << 14; +} +static inline u32 pwr_falcon_irqmclr_r(void) +{ + return 0x0010a014; +} +static inline u32 pwr_falcon_irqmclr_gptmr_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 pwr_falcon_irqmclr_wdtmr_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 pwr_falcon_irqmclr_mthd_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 pwr_falcon_irqmclr_ctxsw_f(u32 v) +{ + return (v & 0x1) << 3; +} +static inline u32 pwr_falcon_irqmclr_halt_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 pwr_falcon_irqmclr_exterr_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 pwr_falcon_irqmclr_swgen0_f(u32 v) +{ + return (v & 0x1) << 6; +} +static inline u32 pwr_falcon_irqmclr_swgen1_f(u32 v) +{ + return (v & 0x1) << 7; +} +static inline u32 pwr_falcon_irqmclr_ext_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 pwr_falcon_irqmclr_ext_ctxe_f(u32 v) +{ + return (v & 0x1) << 8; +} +static inline u32 pwr_falcon_irqmclr_ext_limitv_f(u32 v) +{ + return (v & 0x1) << 9; +} +static inline u32 pwr_falcon_irqmclr_ext_second_f(u32 v) +{ + return (v & 0x1) << 11; +} +static inline u32 pwr_falcon_irqmclr_ext_therm_f(u32 v) +{ + return (v & 0x1) << 12; +} +static inline u32 pwr_falcon_irqmclr_ext_miscio_f(u32 v) +{ + return (v & 0x1) << 13; +} +static inline u32 pwr_falcon_irqmclr_ext_rttimer_f(u32 v) +{ + return (v & 0x1) << 14; +} +static inline u32 pwr_falcon_irqmask_r(void) +{ + return 0x0010a018; +} +static inline u32 pwr_falcon_irqdest_r(void) +{ + return 0x0010a01c; +} +static inline u32 pwr_falcon_irqdest_host_gptmr_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 pwr_falcon_irqdest_host_wdtmr_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 pwr_falcon_irqdest_host_mthd_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 pwr_falcon_irqdest_host_ctxsw_f(u32 v) +{ + return (v & 0x1) << 3; +} +static inline u32 pwr_falcon_irqdest_host_halt_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 pwr_falcon_irqdest_host_exterr_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 pwr_falcon_irqdest_host_swgen0_f(u32 v) +{ + return (v & 0x1) << 6; +} +static inline u32 pwr_falcon_irqdest_host_swgen1_f(u32 v) +{ + return (v & 0x1) << 7; +} +static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 pwr_falcon_irqdest_host_ext_ctxe_f(u32 v) +{ + return (v & 0x1) << 8; +} +static inline u32 pwr_falcon_irqdest_host_ext_limitv_f(u32 v) +{ + return (v & 0x1) << 9; +} +static inline u32 pwr_falcon_irqdest_host_ext_second_f(u32 v) +{ + return (v & 0x1) << 11; +} +static inline u32 pwr_falcon_irqdest_host_ext_therm_f(u32 v) +{ + return (v & 0x1) << 12; +} +static inline u32 pwr_falcon_irqdest_host_ext_miscio_f(u32 v) +{ + return (v & 0x1) << 13; +} +static inline u32 pwr_falcon_irqdest_host_ext_rttimer_f(u32 v) +{ + return (v & 0x1) << 14; +} +static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v) +{ + return (v & 0x1) << 16; +} +static inline u32 pwr_falcon_irqdest_target_wdtmr_f(u32 v) +{ + return (v & 0x1) << 17; +} +static inline u32 pwr_falcon_irqdest_target_mthd_f(u32 v) +{ + return (v & 0x1) << 18; +} +static inline u32 pwr_falcon_irqdest_target_ctxsw_f(u32 v) +{ + return (v & 0x1) << 19; +} +static inline u32 pwr_falcon_irqdest_target_halt_f(u32 v) +{ + return (v & 0x1) << 20; +} +static inline u32 pwr_falcon_irqdest_target_exterr_f(u32 v) +{ + return (v & 0x1) << 21; +} +static inline u32 pwr_falcon_irqdest_target_swgen0_f(u32 v) +{ + return (v & 0x1) << 22; +} +static inline u32 pwr_falcon_irqdest_target_swgen1_f(u32 v) +{ + return (v & 0x1) << 23; +} +static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v) +{ + return (v & 0xff) << 24; +} +static inline u32 pwr_falcon_irqdest_target_ext_ctxe_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 pwr_falcon_irqdest_target_ext_limitv_f(u32 v) +{ + return (v & 0x1) << 25; +} +static inline u32 pwr_falcon_irqdest_target_ext_second_f(u32 v) +{ + return (v & 0x1) << 27; +} +static inline u32 pwr_falcon_irqdest_target_ext_therm_f(u32 v) +{ + return (v & 0x1) << 28; +} +static inline u32 pwr_falcon_irqdest_target_ext_miscio_f(u32 v) +{ + return (v & 0x1) << 29; +} +static inline u32 pwr_falcon_irqdest_target_ext_rttimer_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 pwr_falcon_curctx_r(void) +{ + return 0x0010a050; +} +static inline u32 pwr_falcon_nxtctx_r(void) +{ + return 0x0010a054; +} +static inline u32 pwr_falcon_mailbox0_r(void) +{ + return 0x0010a040; +} +static inline u32 pwr_falcon_mailbox1_r(void) +{ + return 0x0010a044; +} +static inline u32 pwr_falcon_itfen_r(void) +{ + return 0x0010a048; +} +static inline u32 pwr_falcon_itfen_ctxen_enable_f(void) +{ + return 0x1; +} +static inline u32 pwr_falcon_idlestate_r(void) +{ + return 0x0010a04c; +} +static inline u32 pwr_falcon_idlestate_falcon_busy_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 pwr_falcon_idlestate_ext_busy_v(u32 r) +{ + return (r >> 1) & 0x7fff; +} +static inline u32 pwr_falcon_os_r(void) +{ + return 0x0010a080; +} +static inline u32 pwr_falcon_engctl_r(void) +{ + return 0x0010a0a4; +} +static inline u32 pwr_falcon_cpuctl_r(void) +{ + return 0x0010a100; +} +static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 pwr_falcon_cpuctl_halt_intr_m(void) +{ + return 0x1 << 4; +} +static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r) +{ + return (r >> 4) & 0x1; +} +static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_f(u32 v) +{ + return (v & 0x1) << 6; +} +static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_m(void) +{ + return 0x1 << 6; +} +static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_v(u32 r) +{ + return (r >> 6) & 0x1; +} +static inline u32 pwr_falcon_cpuctl_alias_r(void) +{ + return 0x0010a130; +} +static inline u32 pwr_falcon_cpuctl_alias_startcpu_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 pwr_pmu_scpctl_stat_r(void) +{ + return 0x0010ac08; +} +static inline u32 pwr_pmu_scpctl_stat_debug_mode_f(u32 v) +{ + return (v & 0x1) << 20; +} +static inline u32 pwr_pmu_scpctl_stat_debug_mode_m(void) +{ + return 0x1 << 20; +} +static inline u32 pwr_pmu_scpctl_stat_debug_mode_v(u32 r) +{ + return (r >> 20) & 0x1; +} +static inline u32 pwr_falcon_imemc_r(u32 i) +{ + return 0x0010a180 + i*16; +} +static inline u32 pwr_falcon_imemc_offs_f(u32 v) +{ + return (v & 0x3f) << 2; +} +static inline u32 pwr_falcon_imemc_blk_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 pwr_falcon_imemc_aincw_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 pwr_falcon_imemd_r(u32 i) +{ + return 0x0010a184 + i*16; +} +static inline u32 pwr_falcon_imemt_r(u32 i) +{ + return 0x0010a188 + i*16; +} +static inline u32 pwr_falcon_sctl_r(void) +{ + return 0x0010a240; +} +static inline u32 pwr_falcon_mmu_phys_sec_r(void) +{ + return 0x00100ce4; +} +static inline u32 pwr_falcon_bootvec_r(void) +{ + return 0x0010a104; +} +static inline u32 pwr_falcon_bootvec_vec_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 pwr_falcon_dmactl_r(void) +{ + return 0x0010a10c; +} +static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void) +{ + return 0x1 << 1; +} +static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void) +{ + return 0x1 << 2; +} +static inline u32 pwr_falcon_hwcfg_r(void) +{ + return 0x0010a108; +} +static inline u32 pwr_falcon_hwcfg_imem_size_v(u32 r) +{ + return (r >> 0) & 0x1ff; +} +static inline u32 pwr_falcon_hwcfg_dmem_size_v(u32 r) +{ + return (r >> 9) & 0x1ff; +} +static inline u32 pwr_falcon_dmatrfbase_r(void) +{ + return 0x0010a110; +} +static inline u32 pwr_falcon_dmatrfbase1_r(void) +{ + return 0x0010a128; +} +static inline u32 pwr_falcon_dmatrfmoffs_r(void) +{ + return 0x0010a114; +} +static inline u32 pwr_falcon_dmatrfcmd_r(void) +{ + return 0x0010a118; +} +static inline u32 pwr_falcon_dmatrfcmd_imem_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 pwr_falcon_dmatrfcmd_write_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 pwr_falcon_dmatrfcmd_size_f(u32 v) +{ + return (v & 0x7) << 8; +} +static inline u32 pwr_falcon_dmatrfcmd_ctxdma_f(u32 v) +{ + return (v & 0x7) << 12; +} +static inline u32 pwr_falcon_dmatrffboffs_r(void) +{ + return 0x0010a11c; +} +static inline u32 pwr_falcon_exterraddr_r(void) +{ + return 0x0010a168; +} +static inline u32 pwr_falcon_exterrstat_r(void) +{ + return 0x0010a16c; +} +static inline u32 pwr_falcon_exterrstat_valid_m(void) +{ + return 0x1 << 31; +} +static inline u32 pwr_falcon_exterrstat_valid_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 pwr_falcon_exterrstat_valid_true_v(void) +{ + return 0x00000001; +} +static inline u32 pwr_pmu_falcon_icd_cmd_r(void) +{ + return 0x0010a200; +} +static inline u32 pwr_pmu_falcon_icd_cmd_opc_s(void) +{ + return 4; +} +static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void) +{ + return 0xf << 0; +} +static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r) +{ + return (r >> 0) & 0xf; +} +static inline u32 pwr_pmu_falcon_icd_cmd_opc_rreg_f(void) +{ + return 0x8; +} +static inline u32 pwr_pmu_falcon_icd_cmd_opc_rstat_f(void) +{ + return 0xe; +} +static inline u32 pwr_pmu_falcon_icd_cmd_idx_f(u32 v) +{ + return (v & 0x1f) << 8; +} +static inline u32 pwr_pmu_falcon_icd_rdata_r(void) +{ + return 0x0010a20c; +} +static inline u32 pwr_falcon_dmemc_r(u32 i) +{ + return 0x0010a1c0 + i*8; +} +static inline u32 pwr_falcon_dmemc_offs_f(u32 v) +{ + return (v & 0x3f) << 2; +} +static inline u32 pwr_falcon_dmemc_offs_m(void) +{ + return 0x3f << 2; +} +static inline u32 pwr_falcon_dmemc_blk_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 pwr_falcon_dmemc_blk_m(void) +{ + return 0xff << 8; +} +static inline u32 pwr_falcon_dmemc_aincw_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 pwr_falcon_dmemc_aincr_f(u32 v) +{ + return (v & 0x1) << 25; +} +static inline u32 pwr_falcon_dmemd_r(u32 i) +{ + return 0x0010a1c4 + i*8; +} +static inline u32 pwr_pmu_new_instblk_r(void) +{ + return 0x0010a480; +} +static inline u32 pwr_pmu_new_instblk_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 pwr_pmu_new_instblk_target_fb_f(void) +{ + return 0x0; +} +static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void) +{ + return 0x20000000; +} +static inline u32 pwr_pmu_new_instblk_target_sys_ncoh_f(void) +{ + return 0x30000000; +} +static inline u32 pwr_pmu_new_instblk_valid_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 pwr_pmu_mutex_id_r(void) +{ + return 0x0010a488; +} +static inline u32 pwr_pmu_mutex_id_value_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 pwr_pmu_mutex_id_value_init_v(void) +{ + return 0x00000000; +} +static inline u32 pwr_pmu_mutex_id_value_not_avail_v(void) +{ + return 0x000000ff; +} +static inline u32 pwr_pmu_mutex_id_release_r(void) +{ + return 0x0010a48c; +} +static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 pwr_pmu_mutex_id_release_value_m(void) +{ + return 0xff << 0; +} +static inline u32 pwr_pmu_mutex_id_release_value_init_v(void) +{ + return 0x00000000; +} +static inline u32 pwr_pmu_mutex_id_release_value_init_f(void) +{ + return 0x0; +} +static inline u32 pwr_pmu_mutex_r(u32 i) +{ + return 0x0010a580 + i*4; +} +static inline u32 pwr_pmu_mutex__size_1_v(void) +{ + return 0x00000010; +} +static inline u32 pwr_pmu_mutex_value_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 pwr_pmu_mutex_value_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 pwr_pmu_mutex_value_initial_lock_f(void) +{ + return 0x0; +} +static inline u32 pwr_pmu_queue_head_r(u32 i) +{ + return 0x0010a800 + i*4; +} +static inline u32 pwr_pmu_queue_head__size_1_v(void) +{ + return 0x00000008; +} +static inline u32 pwr_pmu_queue_head_address_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 pwr_pmu_queue_head_address_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 pwr_pmu_queue_tail_r(u32 i) +{ + return 0x0010a820 + i*4; +} +static inline u32 pwr_pmu_queue_tail__size_1_v(void) +{ + return 0x00000008; +} +static inline u32 pwr_pmu_queue_tail_address_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 pwr_pmu_queue_tail_address_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 pwr_pmu_msgq_head_r(void) +{ + return 0x0010a4c8; +} +static inline u32 pwr_pmu_msgq_head_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 pwr_pmu_msgq_head_val_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 pwr_pmu_msgq_tail_r(void) +{ + return 0x0010a4cc; +} +static inline u32 pwr_pmu_msgq_tail_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 pwr_pmu_msgq_tail_val_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 pwr_pmu_idle_mask_r(u32 i) +{ + return 0x0010a504 + i*16; +} +static inline u32 pwr_pmu_idle_mask_gr_enabled_f(void) +{ + return 0x1; +} +static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void) +{ + return 0x200000; +} +static inline u32 pwr_pmu_idle_count_r(u32 i) +{ + return 0x0010a508 + i*16; +} +static inline u32 pwr_pmu_idle_count_value_f(u32 v) +{ + return (v & 0x7fffffff) << 0; +} +static inline u32 pwr_pmu_idle_count_value_v(u32 r) +{ + return (r >> 0) & 0x7fffffff; +} +static inline u32 pwr_pmu_idle_count_reset_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 pwr_pmu_idle_ctrl_r(u32 i) +{ + return 0x0010a50c + i*16; +} +static inline u32 pwr_pmu_idle_ctrl_value_m(void) +{ + return 0x3 << 0; +} +static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void) +{ + return 0x2; +} +static inline u32 pwr_pmu_idle_ctrl_value_always_f(void) +{ + return 0x3; +} +static inline u32 pwr_pmu_idle_ctrl_filter_m(void) +{ + return 0x1 << 2; +} +static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void) +{ + return 0x0; +} +static inline u32 pwr_pmu_idle_mask_supp_r(u32 i) +{ + return 0x0010a9f0 + i*8; +} +static inline u32 pwr_pmu_idle_mask_1_supp_r(u32 i) +{ + return 0x0010a9f4 + i*8; +} +static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i) +{ + return 0x0010aa30 + i*8; +} +static inline u32 pwr_pmu_debug_r(u32 i) +{ + return 0x0010a5c0 + i*4; +} +static inline u32 pwr_pmu_debug__size_1_v(void) +{ + return 0x00000004; +} +static inline u32 pwr_pmu_mailbox_r(u32 i) +{ + return 0x0010a450 + i*4; +} +static inline u32 pwr_pmu_mailbox__size_1_v(void) +{ + return 0x0000000c; +} +static inline u32 pwr_pmu_bar0_addr_r(void) +{ + return 0x0010a7a0; +} +static inline u32 pwr_pmu_bar0_data_r(void) +{ + return 0x0010a7a4; +} +static inline u32 pwr_pmu_bar0_ctl_r(void) +{ + return 0x0010a7ac; +} +static inline u32 pwr_pmu_bar0_timeout_r(void) +{ + return 0x0010a7a8; +} +static inline u32 pwr_pmu_bar0_fecs_error_r(void) +{ + return 0x0010a988; +} +static inline u32 pwr_pmu_bar0_error_status_r(void) +{ + return 0x0010a7b0; +} +static inline u32 pwr_pmu_pg_idlefilth_r(u32 i) +{ + return 0x0010a6c0 + i*4; +} +static inline u32 pwr_pmu_pg_ppuidlefilth_r(u32 i) +{ + return 0x0010a6e8 + i*4; +} +static inline u32 pwr_pmu_pg_idle_cnt_r(u32 i) +{ + return 0x0010a710 + i*4; +} +static inline u32 pwr_pmu_pg_intren_r(u32 i) +{ + return 0x0010a760 + i*4; +} +static inline u32 pwr_fbif_transcfg_r(u32 i) +{ + return 0x0010ae00 + i*4; +} +static inline u32 pwr_fbif_transcfg_target_local_fb_f(void) +{ + return 0x0; +} +static inline u32 pwr_fbif_transcfg_target_coherent_sysmem_f(void) +{ + return 0x1; +} +static inline u32 pwr_fbif_transcfg_target_noncoherent_sysmem_f(void) +{ + return 0x2; +} +static inline u32 pwr_fbif_transcfg_mem_type_s(void) +{ + return 1; +} +static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 pwr_fbif_transcfg_mem_type_m(void) +{ + return 0x1 << 2; +} +static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 pwr_fbif_transcfg_mem_type_virtual_f(void) +{ + return 0x0; +} +static inline u32 pwr_fbif_transcfg_mem_type_physical_f(void) +{ + return 0x4; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h new file mode 100644 index 00000000..7fff981b --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h @@ -0,0 +1,761 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_ram_gv100_h_ +#define _hw_ram_gv100_h_ + +static inline u32 ram_in_ramfc_s(void) +{ + return 4096; +} +static inline u32 ram_in_ramfc_w(void) +{ + return 0; +} +static inline u32 ram_in_page_dir_base_target_f(u32 v) +{ + return (v & 0x3) << 0; +} +static inline u32 ram_in_page_dir_base_target_w(void) +{ + return 128; +} +static inline u32 ram_in_page_dir_base_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 ram_in_page_dir_base_target_sys_mem_coh_f(void) +{ + return 0x2; +} +static inline u32 ram_in_page_dir_base_target_sys_mem_ncoh_f(void) +{ + return 0x3; +} +static inline u32 ram_in_page_dir_base_vol_w(void) +{ + return 128; +} +static inline u32 ram_in_page_dir_base_vol_true_f(void) +{ + return 0x4; +} +static inline u32 ram_in_page_dir_base_vol_false_f(void) +{ + return 0x0; +} +static inline u32 ram_in_page_dir_base_fault_replay_tex_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 ram_in_page_dir_base_fault_replay_tex_m(void) +{ + return 0x1 << 4; +} +static inline u32 ram_in_page_dir_base_fault_replay_tex_w(void) +{ + return 128; +} +static inline u32 ram_in_page_dir_base_fault_replay_tex_true_f(void) +{ + return 0x10; +} +static inline u32 ram_in_page_dir_base_fault_replay_gcc_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 ram_in_page_dir_base_fault_replay_gcc_m(void) +{ + return 0x1 << 5; +} +static inline u32 ram_in_page_dir_base_fault_replay_gcc_w(void) +{ + return 128; +} +static inline u32 ram_in_page_dir_base_fault_replay_gcc_true_f(void) +{ + return 0x20; +} +static inline u32 ram_in_big_page_size_f(u32 v) +{ + return (v & 0x1) << 11; +} +static inline u32 ram_in_big_page_size_m(void) +{ + return 0x1 << 11; +} +static inline u32 ram_in_big_page_size_w(void) +{ + return 128; +} +static inline u32 ram_in_big_page_size_128kb_f(void) +{ + return 0x0; +} +static inline u32 ram_in_big_page_size_64kb_f(void) +{ + return 0x800; +} +static inline u32 ram_in_page_dir_base_lo_f(u32 v) +{ + return (v & 0xfffff) << 12; +} +static inline u32 ram_in_page_dir_base_lo_w(void) +{ + return 128; +} +static inline u32 ram_in_page_dir_base_hi_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ram_in_page_dir_base_hi_w(void) +{ + return 129; +} +static inline u32 ram_in_engine_cs_w(void) +{ + return 132; +} +static inline u32 ram_in_engine_cs_wfi_v(void) +{ + return 0x00000000; +} +static inline u32 ram_in_engine_cs_wfi_f(void) +{ + return 0x0; +} +static inline u32 ram_in_engine_cs_fg_v(void) +{ + return 0x00000001; +} +static inline u32 ram_in_engine_cs_fg_f(void) +{ + return 0x8; +} +static inline u32 ram_in_engine_wfi_mode_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 ram_in_engine_wfi_mode_w(void) +{ + return 132; +} +static inline u32 ram_in_engine_wfi_mode_physical_v(void) +{ + return 0x00000000; +} +static inline u32 ram_in_engine_wfi_mode_virtual_v(void) +{ + return 0x00000001; +} +static inline u32 ram_in_engine_wfi_target_f(u32 v) +{ + return (v & 0x3) << 0; +} +static inline u32 ram_in_engine_wfi_target_w(void) +{ + return 132; +} +static inline u32 ram_in_engine_wfi_target_sys_mem_coh_v(void) +{ + return 0x00000002; +} +static inline u32 ram_in_engine_wfi_target_sys_mem_ncoh_v(void) +{ + return 0x00000003; +} +static inline u32 ram_in_engine_wfi_target_local_mem_v(void) +{ + return 0x00000000; +} +static inline u32 ram_in_engine_wfi_ptr_lo_f(u32 v) +{ + return (v & 0xfffff) << 12; +} +static inline u32 ram_in_engine_wfi_ptr_lo_w(void) +{ + return 132; +} +static inline u32 ram_in_engine_wfi_ptr_hi_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 ram_in_engine_wfi_ptr_hi_w(void) +{ + return 133; +} +static inline u32 ram_in_engine_wfi_veid_f(u32 v) +{ + return (v & 0x3f) << 0; +} +static inline u32 ram_in_engine_wfi_veid_w(void) +{ + return 134; +} +static inline u32 ram_in_eng_method_buffer_addr_lo_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ram_in_eng_method_buffer_addr_lo_w(void) +{ + return 136; +} +static inline u32 ram_in_eng_method_buffer_addr_hi_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 ram_in_eng_method_buffer_addr_hi_w(void) +{ + return 137; +} +static inline u32 ram_in_sc_page_dir_base_target_f(u32 v, u32 i) +{ + return (v & 0x3) << (0 + i*0); +} +static inline u32 ram_in_sc_page_dir_base_target__size_1_v(void) +{ + return 0x00000040; +} +static inline u32 ram_in_sc_page_dir_base_target_vid_mem_v(void) +{ + return 0x00000000; +} +static inline u32 ram_in_sc_page_dir_base_target_invalid_v(void) +{ + return 0x00000001; +} +static inline u32 ram_in_sc_page_dir_base_target_sys_mem_coh_v(void) +{ + return 0x00000002; +} +static inline u32 ram_in_sc_page_dir_base_target_sys_mem_ncoh_v(void) +{ + return 0x00000003; +} +static inline u32 ram_in_sc_page_dir_base_vol_f(u32 v, u32 i) +{ + return (v & 0x1) << (2 + i*0); +} +static inline u32 ram_in_sc_page_dir_base_vol__size_1_v(void) +{ + return 0x00000040; +} +static inline u32 ram_in_sc_page_dir_base_vol_true_v(void) +{ + return 0x00000001; +} +static inline u32 ram_in_sc_page_dir_base_vol_false_v(void) +{ + return 0x00000000; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_f(u32 v, u32 i) +{ + return (v & 0x1) << (4 + i*0); +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_tex__size_1_v(void) +{ + return 0x00000040; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_enabled_v(void) +{ + return 0x00000001; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_disabled_v(void) +{ + return 0x00000000; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_f(u32 v, u32 i) +{ + return (v & 0x1) << (5 + i*0); +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc__size_1_v(void) +{ + return 0x00000040; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_enabled_v(void) +{ + return 0x00000001; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_disabled_v(void) +{ + return 0x00000000; +} +static inline u32 ram_in_sc_use_ver2_pt_format_f(u32 v, u32 i) +{ + return (v & 0x1) << (10 + i*0); +} +static inline u32 ram_in_sc_use_ver2_pt_format__size_1_v(void) +{ + return 0x00000040; +} +static inline u32 ram_in_sc_use_ver2_pt_format_false_v(void) +{ + return 0x00000000; +} +static inline u32 ram_in_sc_use_ver2_pt_format_true_v(void) +{ + return 0x00000001; +} +static inline u32 ram_in_sc_big_page_size_f(u32 v, u32 i) +{ + return (v & 0x1) << (11 + i*0); +} +static inline u32 ram_in_sc_big_page_size__size_1_v(void) +{ + return 0x00000040; +} +static inline u32 ram_in_sc_big_page_size_64kb_v(void) +{ + return 0x00000001; +} +static inline u32 ram_in_sc_page_dir_base_lo_f(u32 v, u32 i) +{ + return (v & 0xfffff) << (12 + i*0); +} +static inline u32 ram_in_sc_page_dir_base_lo__size_1_v(void) +{ + return 0x00000040; +} +static inline u32 ram_in_sc_page_dir_base_hi_f(u32 v, u32 i) +{ + return (v & 0xffffffff) << (0 + i*0); +} +static inline u32 ram_in_sc_page_dir_base_hi__size_1_v(void) +{ + return 0x00000040; +} +static inline u32 ram_in_sc_page_dir_base_target_0_f(u32 v) +{ + return (v & 0x3) << 0; +} +static inline u32 ram_in_sc_page_dir_base_target_0_w(void) +{ + return 168; +} +static inline u32 ram_in_sc_page_dir_base_vol_0_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 ram_in_sc_page_dir_base_vol_0_w(void) +{ + return 168; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_0_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_0_w(void) +{ + return 168; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_0_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_0_w(void) +{ + return 168; +} +static inline u32 ram_in_sc_use_ver2_pt_format_0_f(u32 v) +{ + return (v & 0x1) << 10; +} +static inline u32 ram_in_sc_use_ver2_pt_format_0_w(void) +{ + return 168; +} +static inline u32 ram_in_sc_big_page_size_0_f(u32 v) +{ + return (v & 0x1) << 11; +} +static inline u32 ram_in_sc_big_page_size_0_w(void) +{ + return 168; +} +static inline u32 ram_in_sc_page_dir_base_lo_0_f(u32 v) +{ + return (v & 0xfffff) << 12; +} +static inline u32 ram_in_sc_page_dir_base_lo_0_w(void) +{ + return 168; +} +static inline u32 ram_in_sc_page_dir_base_hi_0_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ram_in_sc_page_dir_base_hi_0_w(void) +{ + return 169; +} +static inline u32 ram_in_base_shift_v(void) +{ + return 0x0000000c; +} +static inline u32 ram_in_alloc_size_v(void) +{ + return 0x00001000; +} +static inline u32 ram_fc_size_val_v(void) +{ + return 0x00000200; +} +static inline u32 ram_fc_gp_put_w(void) +{ + return 0; +} +static inline u32 ram_fc_userd_w(void) +{ + return 2; +} +static inline u32 ram_fc_userd_hi_w(void) +{ + return 3; +} +static inline u32 ram_fc_signature_w(void) +{ + return 4; +} +static inline u32 ram_fc_gp_get_w(void) +{ + return 5; +} +static inline u32 ram_fc_pb_get_w(void) +{ + return 6; +} +static inline u32 ram_fc_pb_get_hi_w(void) +{ + return 7; +} +static inline u32 ram_fc_pb_top_level_get_w(void) +{ + return 8; +} +static inline u32 ram_fc_pb_top_level_get_hi_w(void) +{ + return 9; +} +static inline u32 ram_fc_acquire_w(void) +{ + return 12; +} +static inline u32 ram_fc_sem_addr_hi_w(void) +{ + return 14; +} +static inline u32 ram_fc_sem_addr_lo_w(void) +{ + return 15; +} +static inline u32 ram_fc_sem_payload_lo_w(void) +{ + return 16; +} +static inline u32 ram_fc_sem_payload_hi_w(void) +{ + return 39; +} +static inline u32 ram_fc_sem_execute_w(void) +{ + return 17; +} +static inline u32 ram_fc_gp_base_w(void) +{ + return 18; +} +static inline u32 ram_fc_gp_base_hi_w(void) +{ + return 19; +} +static inline u32 ram_fc_gp_fetch_w(void) +{ + return 20; +} +static inline u32 ram_fc_pb_fetch_w(void) +{ + return 21; +} +static inline u32 ram_fc_pb_fetch_hi_w(void) +{ + return 22; +} +static inline u32 ram_fc_pb_put_w(void) +{ + return 23; +} +static inline u32 ram_fc_pb_put_hi_w(void) +{ + return 24; +} +static inline u32 ram_fc_pb_header_w(void) +{ + return 33; +} +static inline u32 ram_fc_pb_count_w(void) +{ + return 34; +} +static inline u32 ram_fc_subdevice_w(void) +{ + return 37; +} +static inline u32 ram_fc_target_w(void) +{ + return 43; +} +static inline u32 ram_fc_hce_ctrl_w(void) +{ + return 57; +} +static inline u32 ram_fc_chid_w(void) +{ + return 58; +} +static inline u32 ram_fc_chid_id_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 ram_fc_chid_id_w(void) +{ + return 0; +} +static inline u32 ram_fc_config_w(void) +{ + return 61; +} +static inline u32 ram_fc_runlist_timeslice_w(void) +{ + return 62; +} +static inline u32 ram_fc_set_channel_info_w(void) +{ + return 63; +} +static inline u32 ram_userd_base_shift_v(void) +{ + return 0x00000009; +} +static inline u32 ram_userd_chan_size_v(void) +{ + return 0x00000200; +} +static inline u32 ram_userd_put_w(void) +{ + return 16; +} +static inline u32 ram_userd_get_w(void) +{ + return 17; +} +static inline u32 ram_userd_ref_w(void) +{ + return 18; +} +static inline u32 ram_userd_put_hi_w(void) +{ + return 19; +} +static inline u32 ram_userd_ref_threshold_w(void) +{ + return 20; +} +static inline u32 ram_userd_top_level_get_w(void) +{ + return 22; +} +static inline u32 ram_userd_top_level_get_hi_w(void) +{ + return 23; +} +static inline u32 ram_userd_get_hi_w(void) +{ + return 24; +} +static inline u32 ram_userd_gp_get_w(void) +{ + return 34; +} +static inline u32 ram_userd_gp_put_w(void) +{ + return 35; +} +static inline u32 ram_userd_gp_top_level_get_w(void) +{ + return 22; +} +static inline u32 ram_userd_gp_top_level_get_hi_w(void) +{ + return 23; +} +static inline u32 ram_rl_entry_size_v(void) +{ + return 0x00000010; +} +static inline u32 ram_rl_entry_type_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 ram_rl_entry_type_channel_v(void) +{ + return 0x00000000; +} +static inline u32 ram_rl_entry_type_tsg_v(void) +{ + return 0x00000001; +} +static inline u32 ram_rl_entry_id_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 ram_rl_entry_chan_runqueue_selector_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 ram_rl_entry_chan_inst_target_f(u32 v) +{ + return (v & 0x3) << 4; +} +static inline u32 ram_rl_entry_chan_inst_target_sys_mem_ncoh_v(void) +{ + return 0x00000003; +} +static inline u32 ram_rl_entry_chan_userd_target_f(u32 v) +{ + return (v & 0x3) << 6; +} +static inline u32 ram_rl_entry_chan_userd_target_vid_mem_v(void) +{ + return 0x00000000; +} +static inline u32 ram_rl_entry_chan_userd_target_vid_mem_nvlink_coh_v(void) +{ + return 0x00000001; +} +static inline u32 ram_rl_entry_chan_userd_target_sys_mem_coh_v(void) +{ + return 0x00000002; +} +static inline u32 ram_rl_entry_chan_userd_target_sys_mem_ncoh_v(void) +{ + return 0x00000003; +} +static inline u32 ram_rl_entry_chan_userd_ptr_lo_f(u32 v) +{ + return (v & 0xffffff) << 8; +} +static inline u32 ram_rl_entry_chan_userd_ptr_hi_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ram_rl_entry_chid_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 ram_rl_entry_chan_inst_ptr_lo_f(u32 v) +{ + return (v & 0xfffff) << 12; +} +static inline u32 ram_rl_entry_chan_inst_ptr_hi_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ram_rl_entry_tsg_timeslice_scale_f(u32 v) +{ + return (v & 0xf) << 16; +} +static inline u32 ram_rl_entry_tsg_timeslice_scale_3_v(void) +{ + return 0x00000003; +} +static inline u32 ram_rl_entry_tsg_timeslice_timeout_f(u32 v) +{ + return (v & 0xff) << 24; +} +static inline u32 ram_rl_entry_tsg_timeslice_timeout_128_v(void) +{ + return 0x00000080; +} +static inline u32 ram_rl_entry_tsg_timeslice_timeout_disable_v(void) +{ + return 0x00000000; +} +static inline u32 ram_rl_entry_tsg_length_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 ram_rl_entry_tsg_length_init_v(void) +{ + return 0x00000000; +} +static inline u32 ram_rl_entry_tsg_length_min_v(void) +{ + return 0x00000001; +} +static inline u32 ram_rl_entry_tsg_length_max_v(void) +{ + return 0x00000080; +} +static inline u32 ram_rl_entry_tsg_tsgid_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 ram_rl_entry_chan_userd_ptr_align_shift_v(void) +{ + return 0x00000008; +} +static inline u32 ram_rl_entry_chan_userd_align_shift_v(void) +{ + return 0x00000008; +} +static inline u32 ram_rl_entry_chan_inst_ptr_align_shift_v(void) +{ + return 0x0000000c; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_therm_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_therm_gv100.h new file mode 100644 index 00000000..d98002c0 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_therm_gv100.h @@ -0,0 +1,293 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_therm_gv100_h_ +#define _hw_therm_gv100_h_ + +static inline u32 therm_weight_1_r(void) +{ + return 0x00020024; +} +static inline u32 therm_config1_r(void) +{ + return 0x00020050; +} +static inline u32 therm_config2_r(void) +{ + return 0x00020130; +} +static inline u32 therm_config2_slowdown_factor_extended_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 therm_config2_grad_enable_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 therm_gate_ctrl_r(u32 i) +{ + return 0x00020200 + i*4; +} +static inline u32 therm_gate_ctrl_eng_clk_m(void) +{ + return 0x3 << 0; +} +static inline u32 therm_gate_ctrl_eng_clk_run_f(void) +{ + return 0x0; +} +static inline u32 therm_gate_ctrl_eng_clk_auto_f(void) +{ + return 0x1; +} +static inline u32 therm_gate_ctrl_eng_clk_stop_f(void) +{ + return 0x2; +} +static inline u32 therm_gate_ctrl_blk_clk_m(void) +{ + return 0x3 << 2; +} +static inline u32 therm_gate_ctrl_blk_clk_run_f(void) +{ + return 0x0; +} +static inline u32 therm_gate_ctrl_blk_clk_auto_f(void) +{ + return 0x4; +} +static inline u32 therm_gate_ctrl_idle_holdoff_m(void) +{ + return 0x1 << 4; +} +static inline u32 therm_gate_ctrl_idle_holdoff_off_f(void) +{ + return 0x0; +} +static inline u32 therm_gate_ctrl_idle_holdoff_on_f(void) +{ + return 0x10; +} +static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v) +{ + return (v & 0x1f) << 8; +} +static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void) +{ + return 0x1f << 8; +} +static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v) +{ + return (v & 0x7) << 13; +} +static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void) +{ + return 0x7 << 13; +} +static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v) +{ + return (v & 0xf) << 16; +} +static inline u32 therm_gate_ctrl_eng_delay_before_m(void) +{ + return 0xf << 16; +} +static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v) +{ + return (v & 0xf) << 20; +} +static inline u32 therm_gate_ctrl_eng_delay_after_m(void) +{ + return 0xf << 20; +} +static inline u32 therm_fecs_idle_filter_r(void) +{ + return 0x00020288; +} +static inline u32 therm_fecs_idle_filter_value_m(void) +{ + return 0xffffffff << 0; +} +static inline u32 therm_hubmmu_idle_filter_r(void) +{ + return 0x0002028c; +} +static inline u32 therm_hubmmu_idle_filter_value_m(void) +{ + return 0xffffffff << 0; +} +static inline u32 therm_clk_slowdown_r(u32 i) +{ + return 0x00020160 + i*4; +} +static inline u32 therm_clk_slowdown_idle_factor_f(u32 v) +{ + return (v & 0x3f) << 16; +} +static inline u32 therm_clk_slowdown_idle_factor_m(void) +{ + return 0x3f << 16; +} +static inline u32 therm_clk_slowdown_idle_factor_v(u32 r) +{ + return (r >> 16) & 0x3f; +} +static inline u32 therm_clk_slowdown_idle_factor_disabled_f(void) +{ + return 0x0; +} +static inline u32 therm_grad_stepping_table_r(u32 i) +{ + return 0x000202c8 + i*4; +} +static inline u32 therm_grad_stepping_table_slowdown_factor0_f(u32 v) +{ + return (v & 0x3f) << 0; +} +static inline u32 therm_grad_stepping_table_slowdown_factor0_m(void) +{ + return 0x3f << 0; +} +static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f(void) +{ + return 0x1; +} +static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f(void) +{ + return 0x2; +} +static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f(void) +{ + return 0x6; +} +static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f(void) +{ + return 0xe; +} +static inline u32 therm_grad_stepping_table_slowdown_factor1_f(u32 v) +{ + return (v & 0x3f) << 6; +} +static inline u32 therm_grad_stepping_table_slowdown_factor1_m(void) +{ + return 0x3f << 6; +} +static inline u32 therm_grad_stepping_table_slowdown_factor2_f(u32 v) +{ + return (v & 0x3f) << 12; +} +static inline u32 therm_grad_stepping_table_slowdown_factor2_m(void) +{ + return 0x3f << 12; +} +static inline u32 therm_grad_stepping_table_slowdown_factor3_f(u32 v) +{ + return (v & 0x3f) << 18; +} +static inline u32 therm_grad_stepping_table_slowdown_factor3_m(void) +{ + return 0x3f << 18; +} +static inline u32 therm_grad_stepping_table_slowdown_factor4_f(u32 v) +{ + return (v & 0x3f) << 24; +} +static inline u32 therm_grad_stepping_table_slowdown_factor4_m(void) +{ + return 0x3f << 24; +} +static inline u32 therm_grad_stepping0_r(void) +{ + return 0x000202c0; +} +static inline u32 therm_grad_stepping0_feature_s(void) +{ + return 1; +} +static inline u32 therm_grad_stepping0_feature_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 therm_grad_stepping0_feature_m(void) +{ + return 0x1 << 0; +} +static inline u32 therm_grad_stepping0_feature_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 therm_grad_stepping0_feature_enable_f(void) +{ + return 0x1; +} +static inline u32 therm_grad_stepping1_r(void) +{ + return 0x000202c4; +} +static inline u32 therm_grad_stepping1_pdiv_duration_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 therm_clk_timing_r(u32 i) +{ + return 0x000203c0 + i*4; +} +static inline u32 therm_clk_timing_grad_slowdown_f(u32 v) +{ + return (v & 0x1) << 16; +} +static inline u32 therm_clk_timing_grad_slowdown_m(void) +{ + return 0x1 << 16; +} +static inline u32 therm_clk_timing_grad_slowdown_enabled_f(void) +{ + return 0x10000; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_timer_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_timer_gv100.h new file mode 100644 index 00000000..c71e9a7d --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_timer_gv100.h @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_timer_gv100_h_ +#define _hw_timer_gv100_h_ + +static inline u32 timer_pri_timeout_r(void) +{ + return 0x00009080; +} +static inline u32 timer_pri_timeout_period_f(u32 v) +{ + return (v & 0xffffff) << 0; +} +static inline u32 timer_pri_timeout_period_m(void) +{ + return 0xffffff << 0; +} +static inline u32 timer_pri_timeout_period_v(u32 r) +{ + return (r >> 0) & 0xffffff; +} +static inline u32 timer_pri_timeout_en_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 timer_pri_timeout_en_m(void) +{ + return 0x1 << 31; +} +static inline u32 timer_pri_timeout_en_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 timer_pri_timeout_en_en_enabled_f(void) +{ + return 0x80000000; +} +static inline u32 timer_pri_timeout_en_en_disabled_f(void) +{ + return 0x0; +} +static inline u32 timer_pri_timeout_save_0_r(void) +{ + return 0x00009084; +} +static inline u32 timer_pri_timeout_save_1_r(void) +{ + return 0x00009088; +} +static inline u32 timer_pri_timeout_fecs_errcode_r(void) +{ + return 0x0000908c; +} +static inline u32 timer_time_0_r(void) +{ + return 0x00009400; +} +static inline u32 timer_time_1_r(void) +{ + return 0x00009410; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h new file mode 100644 index 00000000..d993bddc --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h @@ -0,0 +1,229 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_top_gv100_h_ +#define _hw_top_gv100_h_ + +static inline u32 top_num_gpcs_r(void) +{ + return 0x00022430; +} +static inline u32 top_num_gpcs_value_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 top_tpc_per_gpc_r(void) +{ + return 0x00022434; +} +static inline u32 top_tpc_per_gpc_value_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 top_num_fbps_r(void) +{ + return 0x00022438; +} +static inline u32 top_num_fbps_value_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 top_ltc_per_fbp_r(void) +{ + return 0x00022450; +} +static inline u32 top_ltc_per_fbp_value_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 top_slices_per_ltc_r(void) +{ + return 0x0002245c; +} +static inline u32 top_slices_per_ltc_value_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 top_num_ltcs_r(void) +{ + return 0x00022454; +} +static inline u32 top_num_ces_r(void) +{ + return 0x00022444; +} +static inline u32 top_num_ces_value_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 top_device_info_r(u32 i) +{ + return 0x00022700 + i*4; +} +static inline u32 top_device_info__size_1_v(void) +{ + return 0x00000040; +} +static inline u32 top_device_info_chain_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 top_device_info_chain_enable_v(void) +{ + return 0x00000001; +} +static inline u32 top_device_info_engine_enum_v(u32 r) +{ + return (r >> 26) & 0xf; +} +static inline u32 top_device_info_runlist_enum_v(u32 r) +{ + return (r >> 21) & 0xf; +} +static inline u32 top_device_info_intr_enum_v(u32 r) +{ + return (r >> 15) & 0x1f; +} +static inline u32 top_device_info_reset_enum_v(u32 r) +{ + return (r >> 9) & 0x1f; +} +static inline u32 top_device_info_type_enum_v(u32 r) +{ + return (r >> 2) & 0x1fffffff; +} +static inline u32 top_device_info_type_enum_graphics_v(void) +{ + return 0x00000000; +} +static inline u32 top_device_info_type_enum_graphics_f(void) +{ + return 0x0; +} +static inline u32 top_device_info_type_enum_copy2_v(void) +{ + return 0x00000003; +} +static inline u32 top_device_info_type_enum_copy2_f(void) +{ + return 0xc; +} +static inline u32 top_device_info_type_enum_lce_v(void) +{ + return 0x00000013; +} +static inline u32 top_device_info_type_enum_lce_f(void) +{ + return 0x4c; +} +static inline u32 top_device_info_engine_v(u32 r) +{ + return (r >> 5) & 0x1; +} +static inline u32 top_device_info_runlist_v(u32 r) +{ + return (r >> 4) & 0x1; +} +static inline u32 top_device_info_intr_v(u32 r) +{ + return (r >> 3) & 0x1; +} +static inline u32 top_device_info_reset_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 top_device_info_entry_v(u32 r) +{ + return (r >> 0) & 0x3; +} +static inline u32 top_device_info_entry_not_valid_v(void) +{ + return 0x00000000; +} +static inline u32 top_device_info_entry_enum_v(void) +{ + return 0x00000002; +} +static inline u32 top_device_info_entry_data_v(void) +{ + return 0x00000001; +} +static inline u32 top_device_info_data_type_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 top_device_info_data_type_enum2_v(void) +{ + return 0x00000000; +} +static inline u32 top_device_info_data_inst_id_v(u32 r) +{ + return (r >> 26) & 0xf; +} +static inline u32 top_device_info_data_pri_base_v(u32 r) +{ + return (r >> 12) & 0xfff; +} +static inline u32 top_device_info_data_pri_base_align_v(void) +{ + return 0x0000000c; +} +static inline u32 top_device_info_data_fault_id_enum_v(u32 r) +{ + return (r >> 3) & 0x7f; +} +static inline u32 top_device_info_data_fault_id_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 top_device_info_data_fault_id_valid_v(void) +{ + return 0x00000001; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_usermode_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_usermode_gv100.h new file mode 100644 index 00000000..86045e51 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_usermode_gv100.h @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_usermode_gv100_h_ +#define _hw_usermode_gv100_h_ + +static inline u32 usermode_cfg0_r(void) +{ + return 0x00810000; +} +static inline u32 usermode_cfg0_class_id_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 usermode_cfg0_class_id_value_v(void) +{ + return 0x0000c361; +} +static inline u32 usermode_time_0_r(void) +{ + return 0x00810080; +} +static inline u32 usermode_time_0_nsec_f(u32 v) +{ + return (v & 0x7ffffff) << 5; +} +static inline u32 usermode_time_1_r(void) +{ + return 0x00810084; +} +static inline u32 usermode_time_1_nsec_f(u32 v) +{ + return (v & 0x1fffffff) << 0; +} +static inline u32 usermode_notify_channel_pending_r(void) +{ + return 0x00810090; +} +static inline u32 usermode_notify_channel_pending_id_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xp_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xp_gv100.h new file mode 100644 index 00000000..4f15b39d --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xp_gv100.h @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_xp_gv100_h_ +#define _hw_xp_gv100_h_ + +static inline u32 xp_dl_mgr_r(u32 i) +{ + return 0x0008b8c0 + i*4; +} +static inline u32 xp_dl_mgr_safe_timing_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 xp_pl_link_config_r(u32 i) +{ + return 0x0008c040 + i*4; +} +static inline u32 xp_pl_link_config_ltssm_status_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 xp_pl_link_config_ltssm_status_idle_v(void) +{ + return 0x00000000; +} +static inline u32 xp_pl_link_config_ltssm_directive_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 xp_pl_link_config_ltssm_directive_m(void) +{ + return 0xf << 0; +} +static inline u32 xp_pl_link_config_ltssm_directive_normal_operations_v(void) +{ + return 0x00000000; +} +static inline u32 xp_pl_link_config_ltssm_directive_change_speed_v(void) +{ + return 0x00000001; +} +static inline u32 xp_pl_link_config_max_link_rate_f(u32 v) +{ + return (v & 0x3) << 18; +} +static inline u32 xp_pl_link_config_max_link_rate_m(void) +{ + return 0x3 << 18; +} +static inline u32 xp_pl_link_config_max_link_rate_2500_mtps_v(void) +{ + return 0x00000002; +} +static inline u32 xp_pl_link_config_max_link_rate_5000_mtps_v(void) +{ + return 0x00000001; +} +static inline u32 xp_pl_link_config_max_link_rate_8000_mtps_v(void) +{ + return 0x00000000; +} +static inline u32 xp_pl_link_config_target_tx_width_f(u32 v) +{ + return (v & 0x7) << 20; +} +static inline u32 xp_pl_link_config_target_tx_width_m(void) +{ + return 0x7 << 20; +} +static inline u32 xp_pl_link_config_target_tx_width_x1_v(void) +{ + return 0x00000007; +} +static inline u32 xp_pl_link_config_target_tx_width_x2_v(void) +{ + return 0x00000006; +} +static inline u32 xp_pl_link_config_target_tx_width_x4_v(void) +{ + return 0x00000005; +} +static inline u32 xp_pl_link_config_target_tx_width_x8_v(void) +{ + return 0x00000004; +} +static inline u32 xp_pl_link_config_target_tx_width_x16_v(void) +{ + return 0x00000000; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xve_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xve_gv100.h new file mode 100644 index 00000000..f082fdc7 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xve_gv100.h @@ -0,0 +1,201 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_xve_gv100_h_ +#define _hw_xve_gv100_h_ + +static inline u32 xve_rom_ctrl_r(void) +{ + return 0x00000050; +} +static inline u32 xve_rom_ctrl_rom_shadow_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 xve_rom_ctrl_rom_shadow_disabled_f(void) +{ + return 0x0; +} +static inline u32 xve_rom_ctrl_rom_shadow_enabled_f(void) +{ + return 0x1; +} +static inline u32 xve_link_control_status_r(void) +{ + return 0x00000088; +} +static inline u32 xve_link_control_status_link_speed_m(void) +{ + return 0xf << 16; +} +static inline u32 xve_link_control_status_link_speed_v(u32 r) +{ + return (r >> 16) & 0xf; +} +static inline u32 xve_link_control_status_link_speed_link_speed_2p5_v(void) +{ + return 0x00000001; +} +static inline u32 xve_link_control_status_link_speed_link_speed_5p0_v(void) +{ + return 0x00000002; +} +static inline u32 xve_link_control_status_link_speed_link_speed_8p0_v(void) +{ + return 0x00000003; +} +static inline u32 xve_link_control_status_link_width_m(void) +{ + return 0x3f << 20; +} +static inline u32 xve_link_control_status_link_width_v(u32 r) +{ + return (r >> 20) & 0x3f; +} +static inline u32 xve_link_control_status_link_width_x1_v(void) +{ + return 0x00000001; +} +static inline u32 xve_link_control_status_link_width_x2_v(void) +{ + return 0x00000002; +} +static inline u32 xve_link_control_status_link_width_x4_v(void) +{ + return 0x00000004; +} +static inline u32 xve_link_control_status_link_width_x8_v(void) +{ + return 0x00000008; +} +static inline u32 xve_link_control_status_link_width_x16_v(void) +{ + return 0x00000010; +} +static inline u32 xve_priv_xv_r(void) +{ + return 0x00000150; +} +static inline u32 xve_priv_xv_cya_l0s_enable_f(u32 v) +{ + return (v & 0x1) << 7; +} +static inline u32 xve_priv_xv_cya_l0s_enable_m(void) +{ + return 0x1 << 7; +} +static inline u32 xve_priv_xv_cya_l0s_enable_v(u32 r) +{ + return (r >> 7) & 0x1; +} +static inline u32 xve_priv_xv_cya_l1_enable_f(u32 v) +{ + return (v & 0x1) << 8; +} +static inline u32 xve_priv_xv_cya_l1_enable_m(void) +{ + return 0x1 << 8; +} +static inline u32 xve_priv_xv_cya_l1_enable_v(u32 r) +{ + return (r >> 8) & 0x1; +} +static inline u32 xve_cya_2_r(void) +{ + return 0x00000704; +} +static inline u32 xve_reset_r(void) +{ + return 0x00000718; +} +static inline u32 xve_reset_reset_m(void) +{ + return 0x1 << 0; +} +static inline u32 xve_reset_gpu_on_sw_reset_m(void) +{ + return 0x1 << 1; +} +static inline u32 xve_reset_counter_en_m(void) +{ + return 0x1 << 2; +} +static inline u32 xve_reset_counter_val_f(u32 v) +{ + return (v & 0x7ff) << 4; +} +static inline u32 xve_reset_counter_val_m(void) +{ + return 0x7ff << 4; +} +static inline u32 xve_reset_counter_val_v(u32 r) +{ + return (r >> 4) & 0x7ff; +} +static inline u32 xve_reset_clock_on_sw_reset_m(void) +{ + return 0x1 << 15; +} +static inline u32 xve_reset_clock_counter_en_m(void) +{ + return 0x1 << 16; +} +static inline u32 xve_reset_clock_counter_val_f(u32 v) +{ + return (v & 0x7ff) << 17; +} +static inline u32 xve_reset_clock_counter_val_m(void) +{ + return 0x7ff << 17; +} +static inline u32 xve_reset_clock_counter_val_v(u32 r) +{ + return (r >> 17) & 0x7ff; +} +#endif diff --git a/drivers/gpu/nvgpu/nvgpu_gpuid_t19x.h b/drivers/gpu/nvgpu/nvgpu_gpuid_t19x.h index 63901445..71841484 100644 --- a/drivers/gpu/nvgpu/nvgpu_gpuid_t19x.h +++ b/drivers/gpu/nvgpu/nvgpu_gpuid_t19x.h @@ -17,16 +17,25 @@ #define NVGPU_GPUID_GV11B \ GK20A_GPUID(NVGPU_GPU_ARCH_GV110, NVGPU_GPU_IMPL_GV11B) +#define NVGPU_GPUID_GV100 \ + GK20A_GPUID(NVGPU_GPU_ARCH_GV100, NVGPU_GPU_IMPL_GV100) + #define NVGPU_COMPAT_TEGRA_GV11B "nvidia,gv11b" #define NVGPU_COMPAT_GENERIC_GV11B "nvidia,generic-gv11b" + #define TEGRA_19x_GPUID NVGPU_GPUID_GV11B #define TEGRA_19x_GPUID_HAL gv11b_init_hal #define TEGRA_19x_GPU_COMPAT_TEGRA NVGPU_COMPAT_TEGRA_GV11B #define TEGRA_19x_GPU_COMPAT_GENERIC NVGPU_COMPAT_GENERIC_GV11B + +#define BIGGPU_19x_GPUID NVGPU_GPUID_GV100 +#define BIGGPU_19x_GPUID_HAL gv100_init_hal + struct gpu_ops; extern int gv11b_init_hal(struct gk20a *); +extern int gv100_init_hal(struct gk20a *); extern struct gk20a_platform t19x_gpu_tegra_platform; #endif diff --git a/include/uapi/linux/nvgpu-t19x.h b/include/uapi/linux/nvgpu-t19x.h index bc37bc7c..f56bc9d7 100644 --- a/include/uapi/linux/nvgpu-t19x.h +++ b/include/uapi/linux/nvgpu-t19x.h @@ -25,7 +25,9 @@ #define _UAPI__LINUX_NVGPU_T19X_IOCTL_H_ #define NVGPU_GPU_ARCH_GV110 0x00000150 +#define NVGPU_GPU_ARCH_GV100 0x00000140 #define NVGPU_GPU_IMPL_GV11B 0x0000000B +#define NVGPU_GPU_IMPL_GV100 0x00000000 /* * this flag is used in struct nvgpu_as_map_buffer_ex_args -- cgit v1.2.2