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authorTerje Bergstrom <tbergstrom@nvidia.com>2018-07-06 13:03:31 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-07-09 20:45:21 -0400
commitda03aa782535e77e221a3c27b0676fe9c1c7980c (patch)
treecf250f2257b46f7d53c3ddeed4f115c75d9259f6
parentad3b170f43dbd5ddb2698c5a193968ae1e584491 (diff)
gpu: nvgpu: Move programming FB phys access to FB
FB physical access register for simulation was programmed in GR implementation. Move it to FB where it belongs. JIRA NVGPU-714 Change-Id: Ic5146a61c7d45eadffdb4f3b6b08906bfcdbc224 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1772915 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
-rw-r--r--drivers/gpu/nvgpu/gm20b/fb_gm20b.c6
-rw-r--r--drivers/gpu/nvgpu/gm20b/gr_gm20b.c5
-rw-r--r--drivers/gpu/nvgpu/gv11b/fb_gv11b.c6
-rw-r--r--drivers/gpu/nvgpu/gv11b/gr_gv11b.c5
4 files changed, 12 insertions, 10 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/fb_gm20b.c b/drivers/gpu/nvgpu/gm20b/fb_gm20b.c
index b2a815fb..2ca8d86c 100644
--- a/drivers/gpu/nvgpu/gm20b/fb_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/fb_gm20b.c
@@ -42,6 +42,12 @@ void fb_gm20b_init_fs_state(struct gk20a *g)
42 42
43 gk20a_writel(g, fb_fbhub_num_active_ltcs_r(), 43 gk20a_writel(g, fb_fbhub_num_active_ltcs_r(),
44 g->ltc_count); 44 g->ltc_count);
45
46 if (!nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {
47 /* Bypass MMU check for non-secure boot. For
48 * secure-boot,this register write has no-effect */
49 gk20a_writel(g, fb_priv_mmu_phy_secure_r(), 0xffffffffU);
50 }
45} 51}
46 52
47void gm20b_fb_set_mmu_page_size(struct gk20a *g) 53void gm20b_fb_set_mmu_page_size(struct gk20a *g)
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
index f9eb97ce..85da0d35 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
@@ -49,11 +49,6 @@ void gr_gm20b_init_gpc_mmu(struct gk20a *g)
49 49
50 nvgpu_log_info(g, "initialize gpc mmu"); 50 nvgpu_log_info(g, "initialize gpc mmu");
51 51
52 if (!nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {
53 /* Bypass MMU check for non-secure boot. For
54 * secure-boot,this register write has no-effect */
55 gk20a_writel(g, fb_priv_mmu_phy_secure_r(), 0xffffffff);
56 }
57 temp = gk20a_readl(g, fb_mmu_ctrl_r()); 52 temp = gk20a_readl(g, fb_mmu_ctrl_r());
58 temp &= gr_gpcs_pri_mmu_ctrl_vm_pg_size_m() | 53 temp &= gr_gpcs_pri_mmu_ctrl_vm_pg_size_m() |
59 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m() | 54 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m() |
diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c
index 39903405..d6e621eb 100644
--- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c
@@ -68,6 +68,12 @@ void gv11b_fb_init_fs_state(struct gk20a *g)
68 nvgpu_log(g, gpu_dbg_info, "mmu active ltcs %u", 68 nvgpu_log(g, gpu_dbg_info, "mmu active ltcs %u",
69 fb_mmu_num_active_ltcs_count_v( 69 fb_mmu_num_active_ltcs_count_v(
70 gk20a_readl(g, fb_mmu_num_active_ltcs_r()))); 70 gk20a_readl(g, fb_mmu_num_active_ltcs_r())));
71
72 if (!nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {
73 /* Bypass MMU check for non-secure boot. For
74 * secure-boot,this register write has no-effect */
75 gk20a_writel(g, fb_priv_mmu_phy_secure_r(), 0xffffffffU);
76 }
71} 77}
72 78
73void gv11b_fb_init_cbc(struct gk20a *g, struct gr_gk20a *gr) 79void gv11b_fb_init_cbc(struct gk20a *g, struct gr_gk20a *gr)
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index 4280e8ff..ef482ba8 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -4248,11 +4248,6 @@ void gr_gv11b_init_gpc_mmu(struct gk20a *g)
4248 4248
4249 nvgpu_log_info(g, "initialize gpc mmu"); 4249 nvgpu_log_info(g, "initialize gpc mmu");
4250 4250
4251 if (!nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {
4252 /* Bypass MMU check for non-secure boot. For
4253 * secure-boot,this register write has no-effect */
4254 gk20a_writel(g, fb_priv_mmu_phy_secure_r(), 0xffffffff);
4255 }
4256 temp = gk20a_readl(g, fb_mmu_ctrl_r()); 4251 temp = gk20a_readl(g, fb_mmu_ctrl_r());
4257 temp &= gr_gpcs_pri_mmu_ctrl_vm_pg_size_m() | 4252 temp &= gr_gpcs_pri_mmu_ctrl_vm_pg_size_m() |
4258 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m() | 4253 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m() |