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authorAparna Das <aparnad@nvidia.com>2018-02-16 20:50:05 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2018-03-16 10:34:12 -0400
commitae1b86ed4f9bb706a289848829a7909669a538d3 (patch)
tree0c8a0a776500782b08af420b1a2b862787853c72
parent34323b559590ed8f1c64ecbb7ffbd838a6478594 (diff)
gpu: nvgpu: add gpu_va to update_hwpm_ctxsw_mode parameters()
It'll allow the function to use fixed mapping. Jira VQRM-2982 Change-Id: I98159c5b199ce1854b1b40704392237cadb71ef2 Signed-off-by: Aparna Das <aparnad@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1660225 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: Nirav Patel <nipatel@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
-rw-r--r--drivers/gpu/nvgpu/common/linux/ioctl_dbg.c2
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.h1
-rw-r--r--drivers/gpu/nvgpu/gk20a/gr_gk20a.c4
-rw-r--r--drivers/gpu/nvgpu/gk20a/gr_gk20a.h1
-rw-r--r--drivers/gpu/nvgpu/vgpu/gr_vgpu.c7
-rw-r--r--drivers/gpu/nvgpu/vgpu/gr_vgpu.h2
6 files changed, 13 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_dbg.c b/drivers/gpu/nvgpu/common/linux/ioctl_dbg.c
index eb6156da..a15ac344 100644
--- a/drivers/gpu/nvgpu/common/linux/ioctl_dbg.c
+++ b/drivers/gpu/nvgpu/common/linux/ioctl_dbg.c
@@ -1045,7 +1045,7 @@ static int nvgpu_dbg_gpu_ioctl_hwpm_ctxsw_mode(struct dbg_session_gk20a *dbg_s,
1045 goto clean_up; 1045 goto clean_up;
1046 } 1046 }
1047 1047
1048 err = g->ops.gr.update_hwpm_ctxsw_mode(g, ch_gk20a, 1048 err = g->ops.gr.update_hwpm_ctxsw_mode(g, ch_gk20a, 0,
1049 args->mode == NVGPU_DBG_GPU_HWPM_CTXSW_MODE_CTXSW); 1049 args->mode == NVGPU_DBG_GPU_HWPM_CTXSW_MODE_CTXSW);
1050 if (err) 1050 if (err)
1051 nvgpu_err(g, 1051 nvgpu_err(g,
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 58570d6d..dd9cb3ce 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -298,6 +298,7 @@ struct gpu_ops {
298 bool enable); 298 bool enable);
299 int (*update_hwpm_ctxsw_mode)(struct gk20a *g, 299 int (*update_hwpm_ctxsw_mode)(struct gk20a *g,
300 struct channel_gk20a *c, 300 struct channel_gk20a *c,
301 u64 gpu_va,
301 bool enable); 302 bool enable);
302 int (*dump_gr_regs)(struct gk20a *g, 303 int (*dump_gr_regs)(struct gk20a *g,
303 struct gk20a_debug_output *o); 304 struct gk20a_debug_output *o);
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index a02c0e5d..94bfd224 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -1722,6 +1722,7 @@ out:
1722 1722
1723int gr_gk20a_update_hwpm_ctxsw_mode(struct gk20a *g, 1723int gr_gk20a_update_hwpm_ctxsw_mode(struct gk20a *g,
1724 struct channel_gk20a *c, 1724 struct channel_gk20a *c,
1725 u64 gpu_va,
1725 bool enable_hwpm_ctxsw) 1726 bool enable_hwpm_ctxsw)
1726{ 1727{
1727 struct tsg_gk20a *tsg; 1728 struct tsg_gk20a *tsg;
@@ -1787,8 +1788,9 @@ int gr_gk20a_update_hwpm_ctxsw_mode(struct gk20a *g,
1787 return ret; 1788 return ret;
1788 } 1789 }
1789 1790
1790 pm_ctx->mem.gpu_va = nvgpu_gmmu_map(c->vm, 1791 pm_ctx->mem.gpu_va = nvgpu_gmmu_map_fixed(c->vm,
1791 &pm_ctx->mem, 1792 &pm_ctx->mem,
1793 gpu_va,
1792 pm_ctx->mem.size, 1794 pm_ctx->mem.size,
1793 NVGPU_VM_MAP_CACHEABLE, 1795 NVGPU_VM_MAP_CACHEABLE,
1794 gk20a_mem_flag_none, true, 1796 gk20a_mem_flag_none, true,
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
index e4eb6c4a..7f89037e 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
@@ -643,6 +643,7 @@ int gr_gk20a_update_smpc_ctxsw_mode(struct gk20a *g,
643 bool enable_smpc_ctxsw); 643 bool enable_smpc_ctxsw);
644int gr_gk20a_update_hwpm_ctxsw_mode(struct gk20a *g, 644int gr_gk20a_update_hwpm_ctxsw_mode(struct gk20a *g,
645 struct channel_gk20a *c, 645 struct channel_gk20a *c,
646 u64 gpu_va,
646 bool enable_hwpm_ctxsw); 647 bool enable_hwpm_ctxsw);
647 648
648struct nvgpu_gr_ctx; 649struct nvgpu_gr_ctx;
diff --git a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c
index c7996fd9..1c72ca76 100644
--- a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c
@@ -1026,7 +1026,7 @@ int vgpu_gr_update_smpc_ctxsw_mode(struct gk20a *g,
1026} 1026}
1027 1027
1028int vgpu_gr_update_hwpm_ctxsw_mode(struct gk20a *g, 1028int vgpu_gr_update_hwpm_ctxsw_mode(struct gk20a *g,
1029 struct channel_gk20a *ch, bool enable) 1029 struct channel_gk20a *ch, u64 gpu_va, bool enable)
1030{ 1030{
1031 struct tsg_gk20a *tsg; 1031 struct tsg_gk20a *tsg;
1032 struct nvgpu_gr_ctx *ch_ctx; 1032 struct nvgpu_gr_ctx *ch_ctx;
@@ -1041,6 +1041,11 @@ int vgpu_gr_update_hwpm_ctxsw_mode(struct gk20a *g,
1041 if (!tsg) 1041 if (!tsg)
1042 return -EINVAL; 1042 return -EINVAL;
1043 1043
1044 if (gpu_va) {
1045 nvgpu_err(g, "gpu_va suppose to be allocated by this function.");
1046 return -EINVAL;
1047 }
1048
1044 ch_ctx = &tsg->gr_ctx; 1049 ch_ctx = &tsg->gr_ctx;
1045 pm_ctx = &ch_ctx->pm_ctx; 1050 pm_ctx = &ch_ctx->pm_ctx;
1046 1051
diff --git a/drivers/gpu/nvgpu/vgpu/gr_vgpu.h b/drivers/gpu/nvgpu/vgpu/gr_vgpu.h
index 1f55823c..d6b25b97 100644
--- a/drivers/gpu/nvgpu/vgpu/gr_vgpu.h
+++ b/drivers/gpu/nvgpu/vgpu/gr_vgpu.h
@@ -58,7 +58,7 @@ int vgpu_gr_set_sm_debug_mode(struct gk20a *g,
58int vgpu_gr_update_smpc_ctxsw_mode(struct gk20a *g, 58int vgpu_gr_update_smpc_ctxsw_mode(struct gk20a *g,
59 struct channel_gk20a *ch, bool enable); 59 struct channel_gk20a *ch, bool enable);
60int vgpu_gr_update_hwpm_ctxsw_mode(struct gk20a *g, 60int vgpu_gr_update_hwpm_ctxsw_mode(struct gk20a *g,
61 struct channel_gk20a *ch, bool enable); 61 struct channel_gk20a *ch, u64 gpu_va, bool enable);
62int vgpu_gr_clear_sm_error_state(struct gk20a *g, 62int vgpu_gr_clear_sm_error_state(struct gk20a *g,
63 struct channel_gk20a *ch, u32 sm_id); 63 struct channel_gk20a *ch, u32 sm_id);
64int vgpu_gr_suspend_contexts(struct gk20a *g, 64int vgpu_gr_suspend_contexts(struct gk20a *g,