From ae1b86ed4f9bb706a289848829a7909669a538d3 Mon Sep 17 00:00:00 2001 From: Aparna Das Date: Fri, 16 Feb 2018 17:50:05 -0800 Subject: gpu: nvgpu: add gpu_va to update_hwpm_ctxsw_mode parameters() It'll allow the function to use fixed mapping. Jira VQRM-2982 Change-Id: I98159c5b199ce1854b1b40704392237cadb71ef2 Signed-off-by: Aparna Das Reviewed-on: https://git-master.nvidia.com/r/1660225 Reviewed-by: Terje Bergstrom Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Tested-by: Richard Zhao Reviewed-by: Nirav Patel Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/linux/ioctl_dbg.c | 2 +- drivers/gpu/nvgpu/gk20a/gk20a.h | 1 + drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 4 +++- drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 1 + drivers/gpu/nvgpu/vgpu/gr_vgpu.c | 7 ++++++- drivers/gpu/nvgpu/vgpu/gr_vgpu.h | 2 +- 6 files changed, 13 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_dbg.c b/drivers/gpu/nvgpu/common/linux/ioctl_dbg.c index eb6156da..a15ac344 100644 --- a/drivers/gpu/nvgpu/common/linux/ioctl_dbg.c +++ b/drivers/gpu/nvgpu/common/linux/ioctl_dbg.c @@ -1045,7 +1045,7 @@ static int nvgpu_dbg_gpu_ioctl_hwpm_ctxsw_mode(struct dbg_session_gk20a *dbg_s, goto clean_up; } - err = g->ops.gr.update_hwpm_ctxsw_mode(g, ch_gk20a, + err = g->ops.gr.update_hwpm_ctxsw_mode(g, ch_gk20a, 0, args->mode == NVGPU_DBG_GPU_HWPM_CTXSW_MODE_CTXSW); if (err) nvgpu_err(g, diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 58570d6d..dd9cb3ce 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -298,6 +298,7 @@ struct gpu_ops { bool enable); int (*update_hwpm_ctxsw_mode)(struct gk20a *g, struct channel_gk20a *c, + u64 gpu_va, bool enable); int (*dump_gr_regs)(struct gk20a *g, struct gk20a_debug_output *o); diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index a02c0e5d..94bfd224 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c @@ -1722,6 +1722,7 @@ out: int gr_gk20a_update_hwpm_ctxsw_mode(struct gk20a *g, struct channel_gk20a *c, + u64 gpu_va, bool enable_hwpm_ctxsw) { struct tsg_gk20a *tsg; @@ -1787,8 +1788,9 @@ int gr_gk20a_update_hwpm_ctxsw_mode(struct gk20a *g, return ret; } - pm_ctx->mem.gpu_va = nvgpu_gmmu_map(c->vm, + pm_ctx->mem.gpu_va = nvgpu_gmmu_map_fixed(c->vm, &pm_ctx->mem, + gpu_va, pm_ctx->mem.size, NVGPU_VM_MAP_CACHEABLE, gk20a_mem_flag_none, true, diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index e4eb6c4a..7f89037e 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h @@ -643,6 +643,7 @@ int gr_gk20a_update_smpc_ctxsw_mode(struct gk20a *g, bool enable_smpc_ctxsw); int gr_gk20a_update_hwpm_ctxsw_mode(struct gk20a *g, struct channel_gk20a *c, + u64 gpu_va, bool enable_hwpm_ctxsw); struct nvgpu_gr_ctx; diff --git a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c index c7996fd9..1c72ca76 100644 --- a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c @@ -1026,7 +1026,7 @@ int vgpu_gr_update_smpc_ctxsw_mode(struct gk20a *g, } int vgpu_gr_update_hwpm_ctxsw_mode(struct gk20a *g, - struct channel_gk20a *ch, bool enable) + struct channel_gk20a *ch, u64 gpu_va, bool enable) { struct tsg_gk20a *tsg; struct nvgpu_gr_ctx *ch_ctx; @@ -1041,6 +1041,11 @@ int vgpu_gr_update_hwpm_ctxsw_mode(struct gk20a *g, if (!tsg) return -EINVAL; + if (gpu_va) { + nvgpu_err(g, "gpu_va suppose to be allocated by this function."); + return -EINVAL; + } + ch_ctx = &tsg->gr_ctx; pm_ctx = &ch_ctx->pm_ctx; diff --git a/drivers/gpu/nvgpu/vgpu/gr_vgpu.h b/drivers/gpu/nvgpu/vgpu/gr_vgpu.h index 1f55823c..d6b25b97 100644 --- a/drivers/gpu/nvgpu/vgpu/gr_vgpu.h +++ b/drivers/gpu/nvgpu/vgpu/gr_vgpu.h @@ -58,7 +58,7 @@ int vgpu_gr_set_sm_debug_mode(struct gk20a *g, int vgpu_gr_update_smpc_ctxsw_mode(struct gk20a *g, struct channel_gk20a *ch, bool enable); int vgpu_gr_update_hwpm_ctxsw_mode(struct gk20a *g, - struct channel_gk20a *ch, bool enable); + struct channel_gk20a *ch, u64 gpu_va, bool enable); int vgpu_gr_clear_sm_error_state(struct gk20a *g, struct channel_gk20a *ch, u32 sm_id); int vgpu_gr_suspend_contexts(struct gk20a *g, -- cgit v1.2.2