diff options
author | Vinod G <vinodg@nvidia.com> | 2018-06-26 21:09:57 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-07-14 18:36:53 -0400 |
commit | ac98827c9d81746020dce689f9eb8c4018a8c148 (patch) | |
tree | 142dea7d1109be3b12a4e94c738a01ab7b13ee89 | |
parent | b97bcb3c689426a1b099e88ceef4d55584e2362b (diff) |
gpu: nvgpu: Add L2 register read-backs following writes
LTC register write is followed by a register read
and if data doesn't match code will report the error.
Renamed existing nvgpu_writel_check function as
nvgpu_writel_loop as it loops until the write get success.
nvgpu_writel_check function write and read back and
compare the data.
Bug 2039150
Change-Id: I0a49be36aad23936f2d58aa82872710827da1d32
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1762344
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
-rw-r--r-- | drivers/gpu/nvgpu/Makefile | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/Makefile.sources | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/io_common.c | 29 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/posix/io.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/ltc_gm20b.c | 21 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 10 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/ltc_gp10b.c | 19 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/ltc_gv11b.c | 21 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/io.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/os/linux/io.c | 2 |
10 files changed, 70 insertions, 37 deletions
diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index e715e385..72795e08 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile | |||
@@ -176,6 +176,7 @@ nvgpu-y += \ | |||
176 | common/pmu/pmu_perfmon.o \ | 176 | common/pmu/pmu_perfmon.o \ |
177 | common/pmu/pmu_debug.o \ | 177 | common/pmu/pmu_debug.o \ |
178 | common/ltc.o \ | 178 | common/ltc.o \ |
179 | common/io_common.o \ | ||
179 | common/clock_gating/gm20b_gating_reglist.o \ | 180 | common/clock_gating/gm20b_gating_reglist.o \ |
180 | common/clock_gating/gp106_gating_reglist.o \ | 181 | common/clock_gating/gp106_gating_reglist.o \ |
181 | common/clock_gating/gp10b_gating_reglist.o \ | 182 | common/clock_gating/gp10b_gating_reglist.o \ |
diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index c0340545..55d7201c 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources | |||
@@ -48,6 +48,7 @@ srcs := common/mm/nvgpu_allocator.c \ | |||
48 | common/as.c \ | 48 | common/as.c \ |
49 | common/rbtree.c \ | 49 | common/rbtree.c \ |
50 | common/ltc.c \ | 50 | common/ltc.c \ |
51 | common/io_common.c \ | ||
51 | common/vbios/bios.c \ | 52 | common/vbios/bios.c \ |
52 | common/falcon/falcon.c \ | 53 | common/falcon/falcon.c \ |
53 | common/pmu/pmu.c \ | 54 | common/pmu/pmu.c \ |
diff --git a/drivers/gpu/nvgpu/common/io_common.c b/drivers/gpu/nvgpu/common/io_common.c new file mode 100644 index 00000000..e7041eb7 --- /dev/null +++ b/drivers/gpu/nvgpu/common/io_common.c | |||
@@ -0,0 +1,29 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | |||
14 | #include <nvgpu/io.h> | ||
15 | #include <nvgpu/types.h> | ||
16 | |||
17 | #include "gk20a/gk20a.h" | ||
18 | |||
19 | void nvgpu_writel_check(struct gk20a *g, u32 r, u32 v) | ||
20 | { | ||
21 | u32 read_val = 0U; | ||
22 | |||
23 | nvgpu_writel(g, r, v); | ||
24 | read_val = nvgpu_readl(g, r); | ||
25 | if (v != read_val) { | ||
26 | nvgpu_log(g, gpu_dbg_reg, "r=0x%x rd=0x%x wr=0x%x (mismatch)", | ||
27 | r, read_val, v); | ||
28 | } | ||
29 | } | ||
diff --git a/drivers/gpu/nvgpu/common/posix/io.c b/drivers/gpu/nvgpu/common/posix/io.c index dc32c20e..7bab8af6 100644 --- a/drivers/gpu/nvgpu/common/posix/io.c +++ b/drivers/gpu/nvgpu/common/posix/io.c | |||
@@ -54,7 +54,7 @@ u32 __nvgpu_readl(struct gk20a *g, u32 r) | |||
54 | return 0; | 54 | return 0; |
55 | } | 55 | } |
56 | 56 | ||
57 | void nvgpu_writel_check(struct gk20a *g, u32 r, u32 v) | 57 | void nvgpu_writel_loop(struct gk20a *g, u32 r, u32 v) |
58 | { | 58 | { |
59 | BUG(); | 59 | BUG(); |
60 | } | 60 | } |
diff --git a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c index a8cbca13..9812c8d8 100644 --- a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c | |||
@@ -276,7 +276,7 @@ void gm20b_flush_ltc(struct gk20a *g) | |||
276 | u32 ltc_stride = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE); | 276 | u32 ltc_stride = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE); |
277 | 277 | ||
278 | /* Clean... */ | 278 | /* Clean... */ |
279 | gk20a_writel(g, ltc_ltcs_ltss_tstg_cmgmt1_r(), | 279 | nvgpu_writel_check(g, ltc_ltcs_ltss_tstg_cmgmt1_r(), |
280 | ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f() | | 280 | ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f() | |
281 | ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f() | | 281 | ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f() | |
282 | ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f() | | 282 | ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f() | |
@@ -318,7 +318,7 @@ void gm20b_flush_ltc(struct gk20a *g) | |||
318 | } | 318 | } |
319 | 319 | ||
320 | /* And invalidate. */ | 320 | /* And invalidate. */ |
321 | gk20a_writel(g, ltc_ltcs_ltss_tstg_cmgmt0_r(), | 321 | nvgpu_writel_check(g, ltc_ltcs_ltss_tstg_cmgmt0_r(), |
322 | ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f() | | 322 | ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f() | |
323 | ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f() | | 323 | ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f() | |
324 | ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f() | | 324 | ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f() | |
@@ -393,15 +393,15 @@ void gm20b_ltc_set_zbc_color_entry(struct gk20a *g, | |||
393 | u32 i; | 393 | u32 i; |
394 | u32 real_index = index + GK20A_STARTOF_ZBC_TABLE; | 394 | u32 real_index = index + GK20A_STARTOF_ZBC_TABLE; |
395 | 395 | ||
396 | gk20a_writel(g, ltc_ltcs_ltss_dstg_zbc_index_r(), | 396 | nvgpu_writel_check(g, ltc_ltcs_ltss_dstg_zbc_index_r(), |
397 | ltc_ltcs_ltss_dstg_zbc_index_address_f(real_index)); | 397 | ltc_ltcs_ltss_dstg_zbc_index_address_f(real_index)); |
398 | 398 | ||
399 | for (i = 0; | 399 | for (i = 0; |
400 | i < ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(); i++) { | 400 | i < ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(); i++) { |
401 | gk20a_writel(g, ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(i), | 401 | nvgpu_writel_check(g, |
402 | color_val->color_l2[i]); | 402 | ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(i), |
403 | color_val->color_l2[i]); | ||
403 | } | 404 | } |
404 | gk20a_readl(g, ltc_ltcs_ltss_dstg_zbc_index_r()); | ||
405 | } | 405 | } |
406 | 406 | ||
407 | /* | 407 | /* |
@@ -413,13 +413,12 @@ void gm20b_ltc_set_zbc_depth_entry(struct gk20a *g, | |||
413 | { | 413 | { |
414 | u32 real_index = index + GK20A_STARTOF_ZBC_TABLE; | 414 | u32 real_index = index + GK20A_STARTOF_ZBC_TABLE; |
415 | 415 | ||
416 | gk20a_writel(g, ltc_ltcs_ltss_dstg_zbc_index_r(), | 416 | nvgpu_writel_check(g, ltc_ltcs_ltss_dstg_zbc_index_r(), |
417 | ltc_ltcs_ltss_dstg_zbc_index_address_f(real_index)); | 417 | ltc_ltcs_ltss_dstg_zbc_index_address_f(real_index)); |
418 | 418 | ||
419 | gk20a_writel(g, ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(), | 419 | nvgpu_writel_check(g, |
420 | depth_val->depth); | 420 | ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(), |
421 | 421 | depth_val->depth); | |
422 | gk20a_readl(g, ltc_ltcs_ltss_dstg_zbc_index_r()); | ||
423 | } | 422 | } |
424 | 423 | ||
425 | void gm20b_ltc_init_cbc(struct gk20a *g, struct gr_gk20a *gr) | 424 | void gm20b_ltc_init_cbc(struct gk20a *g, struct gr_gk20a *gr) |
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 6249992a..424c8490 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c | |||
@@ -537,18 +537,18 @@ int gr_gp10b_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr, | |||
537 | gr->zbc_col_tbl[index].format = color_val->format; | 537 | gr->zbc_col_tbl[index].format = color_val->format; |
538 | gr->zbc_col_tbl[index].ref_cnt++; | 538 | gr->zbc_col_tbl[index].ref_cnt++; |
539 | 539 | ||
540 | gk20a_writel_check(g, gr_gpcs_swdx_dss_zbc_color_r_r(index), | 540 | nvgpu_writel_loop(g, gr_gpcs_swdx_dss_zbc_color_r_r(index), |
541 | color_val->color_ds[0]); | 541 | color_val->color_ds[0]); |
542 | gk20a_writel_check(g, gr_gpcs_swdx_dss_zbc_color_g_r(index), | 542 | nvgpu_writel_loop(g, gr_gpcs_swdx_dss_zbc_color_g_r(index), |
543 | color_val->color_ds[1]); | 543 | color_val->color_ds[1]); |
544 | gk20a_writel_check(g, gr_gpcs_swdx_dss_zbc_color_b_r(index), | 544 | nvgpu_writel_loop(g, gr_gpcs_swdx_dss_zbc_color_b_r(index), |
545 | color_val->color_ds[2]); | 545 | color_val->color_ds[2]); |
546 | gk20a_writel_check(g, gr_gpcs_swdx_dss_zbc_color_a_r(index), | 546 | nvgpu_writel_loop(g, gr_gpcs_swdx_dss_zbc_color_a_r(index), |
547 | color_val->color_ds[3]); | 547 | color_val->color_ds[3]); |
548 | zbc_c = gk20a_readl(g, zbc_c_format_reg + (index & ~3)); | 548 | zbc_c = gk20a_readl(g, zbc_c_format_reg + (index & ~3)); |
549 | zbc_c &= ~(0x7f << ((index % 4) * 7)); | 549 | zbc_c &= ~(0x7f << ((index % 4) * 7)); |
550 | zbc_c |= color_val->format << ((index % 4) * 7); | 550 | zbc_c |= color_val->format << ((index % 4) * 7); |
551 | gk20a_writel_check(g, zbc_c_format_reg + (index & ~3), zbc_c); | 551 | nvgpu_writel_loop(g, zbc_c_format_reg + (index & ~3), zbc_c); |
552 | 552 | ||
553 | return 0; | 553 | return 0; |
554 | } | 554 | } |
diff --git a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c index b0938f75..1e5807d5 100644 --- a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c | |||
@@ -156,14 +156,16 @@ int gp10b_ltc_cbc_ctrl(struct gk20a *g, enum gk20a_cbc_op op, | |||
156 | nvgpu_log_info(g, "clearing CBC lines %u..%u", min, iter_max); | 156 | nvgpu_log_info(g, "clearing CBC lines %u..%u", min, iter_max); |
157 | 157 | ||
158 | if (op == gk20a_cbc_op_clear) { | 158 | if (op == gk20a_cbc_op_clear) { |
159 | gk20a_writel( | 159 | nvgpu_writel_check( |
160 | g, ltc_ltcs_ltss_cbc_ctrl2_r(), | 160 | g, ltc_ltcs_ltss_cbc_ctrl2_r(), |
161 | ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f( | 161 | ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f( |
162 | min)); | 162 | min)); |
163 | gk20a_writel( | 163 | |
164 | nvgpu_writel_check( | ||
164 | g, ltc_ltcs_ltss_cbc_ctrl3_r(), | 165 | g, ltc_ltcs_ltss_cbc_ctrl3_r(), |
165 | ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f( | 166 | ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f( |
166 | iter_max)); | 167 | iter_max)); |
168 | |||
167 | hw_op = ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(); | 169 | hw_op = ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(); |
168 | full_cache_op = false; | 170 | full_cache_op = false; |
169 | } else if (op == gk20a_cbc_op_clean) { | 171 | } else if (op == gk20a_cbc_op_clean) { |
@@ -251,10 +253,9 @@ void gp10b_ltc_isr(struct gk20a *g) | |||
251 | ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(ecc_stats_reg_val); | 253 | ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(ecc_stats_reg_val); |
252 | ecc_stats_reg_val &= | 254 | ecc_stats_reg_val &= |
253 | ~(ltc_ltc0_lts0_dstg_ecc_report_sec_count_m()); | 255 | ~(ltc_ltc0_lts0_dstg_ecc_report_sec_count_m()); |
254 | gk20a_writel(g, | 256 | nvgpu_writel_check(g, |
255 | ltc_ltc0_lts0_dstg_ecc_report_r() + offset, | 257 | ltc_ltc0_lts0_dstg_ecc_report_r() + offset, |
256 | ecc_stats_reg_val); | 258 | ecc_stats_reg_val); |
257 | |||
258 | g->ops.mm.l2_flush(g, true); | 259 | g->ops.mm.l2_flush(g, true); |
259 | } | 260 | } |
260 | if (ltc_intr & | 261 | if (ltc_intr & |
@@ -271,16 +272,16 @@ void gp10b_ltc_isr(struct gk20a *g) | |||
271 | ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(ecc_stats_reg_val); | 272 | ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(ecc_stats_reg_val); |
272 | ecc_stats_reg_val &= | 273 | ecc_stats_reg_val &= |
273 | ~(ltc_ltc0_lts0_dstg_ecc_report_ded_count_m()); | 274 | ~(ltc_ltc0_lts0_dstg_ecc_report_ded_count_m()); |
274 | gk20a_writel(g, | 275 | nvgpu_writel_check(g, |
275 | ltc_ltc0_lts0_dstg_ecc_report_r() + offset, | 276 | ltc_ltc0_lts0_dstg_ecc_report_r() + offset, |
276 | ecc_stats_reg_val); | 277 | ecc_stats_reg_val); |
277 | } | 278 | } |
278 | 279 | ||
279 | nvgpu_err(g, "ltc%d, slice %d: %08x", | 280 | nvgpu_err(g, "ltc%d, slice %d: %08x", |
280 | ltc, slice, ltc_intr); | 281 | ltc, slice, ltc_intr); |
281 | gk20a_writel(g, ltc_ltc0_lts0_intr_r() + | 282 | nvgpu_writel_check(g, ltc_ltc0_lts0_intr_r() + |
282 | ltc_stride * ltc + lts_stride * slice, | 283 | ltc_stride * ltc + lts_stride * slice, |
283 | ltc_intr); | 284 | ltc_intr); |
284 | } | 285 | } |
285 | } | 286 | } |
286 | } | 287 | } |
@@ -314,5 +315,5 @@ void gp10b_ltc_set_enabled(struct gk20a *g, bool enabled) | |||
314 | /* bypass enabled (no caching) */ | 315 | /* bypass enabled (no caching) */ |
315 | reg |= reg_f; | 316 | reg |= reg_f; |
316 | 317 | ||
317 | gk20a_writel(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r(), reg); | 318 | nvgpu_writel_check(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r(), reg); |
318 | } | 319 | } |
diff --git a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c index b64faaa6..48faa4d2 100644 --- a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c | |||
@@ -42,13 +42,12 @@ void gv11b_ltc_set_zbc_stencil_entry(struct gk20a *g, | |||
42 | { | 42 | { |
43 | u32 real_index = index + GK20A_STARTOF_ZBC_TABLE; | 43 | u32 real_index = index + GK20A_STARTOF_ZBC_TABLE; |
44 | 44 | ||
45 | gk20a_writel(g, ltc_ltcs_ltss_dstg_zbc_index_r(), | 45 | nvgpu_writel_check(g, ltc_ltcs_ltss_dstg_zbc_index_r(), |
46 | ltc_ltcs_ltss_dstg_zbc_index_address_f(real_index)); | 46 | ltc_ltcs_ltss_dstg_zbc_index_address_f(real_index)); |
47 | 47 | ||
48 | gk20a_writel(g, ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_r(), | 48 | nvgpu_writel_check(g, |
49 | stencil_val->depth); | 49 | ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_r(), |
50 | 50 | stencil_val->depth); | |
51 | gk20a_readl(g, ltc_ltcs_ltss_dstg_zbc_index_r()); | ||
52 | } | 51 | } |
53 | 52 | ||
54 | void gv11b_ltc_init_fs_state(struct gk20a *g) | 53 | void gv11b_ltc_init_fs_state(struct gk20a *g) |
@@ -72,13 +71,13 @@ void gv11b_ltc_init_fs_state(struct gk20a *g) | |||
72 | reg = gk20a_readl(g, ltc_ltcs_ltss_intr_r()); | 71 | reg = gk20a_readl(g, ltc_ltcs_ltss_intr_r()); |
73 | reg &= ~ltc_ltcs_ltss_intr_en_evicted_cb_m(); | 72 | reg &= ~ltc_ltcs_ltss_intr_en_evicted_cb_m(); |
74 | reg &= ~ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(); | 73 | reg &= ~ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(); |
75 | gk20a_writel(g, ltc_ltcs_ltss_intr_r(), reg); | 74 | nvgpu_writel_check(g, ltc_ltcs_ltss_intr_r(), reg); |
76 | 75 | ||
77 | /* Enable ECC interrupts */ | 76 | /* Enable ECC interrupts */ |
78 | ltc_intr = gk20a_readl(g, ltc_ltcs_ltss_intr_r()); | 77 | ltc_intr = gk20a_readl(g, ltc_ltcs_ltss_intr_r()); |
79 | ltc_intr |= ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f() | | 78 | ltc_intr |= ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f() | |
80 | ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f(); | 79 | ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f(); |
81 | gk20a_writel(g, ltc_ltcs_ltss_intr_r(), | 80 | nvgpu_writel_check(g, ltc_ltcs_ltss_intr_r(), |
82 | ltc_intr); | 81 | ltc_intr); |
83 | } | 82 | } |
84 | 83 | ||
@@ -133,14 +132,16 @@ void gv11b_ltc_isr(struct gk20a *g) | |||
133 | 132 | ||
134 | /* clear the interrupt */ | 133 | /* clear the interrupt */ |
135 | if ((corrected_delta > 0U) || corrected_overflow) { | 134 | if ((corrected_delta > 0U) || corrected_overflow) { |
136 | gk20a_writel(g, ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_r() + offset, 0); | 135 | nvgpu_writel_check(g, |
136 | ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_r() + offset, 0); | ||
137 | } | 137 | } |
138 | if ((uncorrected_delta > 0U) || uncorrected_overflow) { | 138 | if ((uncorrected_delta > 0U) || uncorrected_overflow) { |
139 | gk20a_writel(g, | 139 | nvgpu_writel_check(g, |
140 | ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_r() + offset, 0); | 140 | ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_r() + offset, 0); |
141 | } | 141 | } |
142 | 142 | ||
143 | gk20a_writel(g, ltc_ltc0_lts0_l2_cache_ecc_status_r() + offset, | 143 | nvgpu_writel_check(g, |
144 | ltc_ltc0_lts0_l2_cache_ecc_status_r() + offset, | ||
144 | ltc_ltc0_lts0_l2_cache_ecc_status_reset_task_f()); | 145 | ltc_ltc0_lts0_l2_cache_ecc_status_reset_task_f()); |
145 | 146 | ||
146 | /* update counters per slice */ | 147 | /* update counters per slice */ |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/io.h b/drivers/gpu/nvgpu/include/nvgpu/io.h index 8504829c..fb7783fe 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/io.h +++ b/drivers/gpu/nvgpu/include/nvgpu/io.h | |||
@@ -40,6 +40,7 @@ void nvgpu_writel_relaxed(struct gk20a *g, u32 r, u32 v); | |||
40 | u32 nvgpu_readl(struct gk20a *g, u32 r); | 40 | u32 nvgpu_readl(struct gk20a *g, u32 r); |
41 | u32 __nvgpu_readl(struct gk20a *g, u32 r); | 41 | u32 __nvgpu_readl(struct gk20a *g, u32 r); |
42 | void nvgpu_writel_check(struct gk20a *g, u32 r, u32 v); | 42 | void nvgpu_writel_check(struct gk20a *g, u32 r, u32 v); |
43 | void nvgpu_writel_loop(struct gk20a *g, u32 r, u32 v); | ||
43 | void nvgpu_bar1_writel(struct gk20a *g, u32 b, u32 v); | 44 | void nvgpu_bar1_writel(struct gk20a *g, u32 b, u32 v); |
44 | u32 nvgpu_bar1_readl(struct gk20a *g, u32 b); | 45 | u32 nvgpu_bar1_readl(struct gk20a *g, u32 b); |
45 | bool nvgpu_io_exists(struct gk20a *g); | 46 | bool nvgpu_io_exists(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/os/linux/io.c b/drivers/gpu/nvgpu/os/linux/io.c index 9a0e29d7..4b902f28 100644 --- a/drivers/gpu/nvgpu/os/linux/io.c +++ b/drivers/gpu/nvgpu/os/linux/io.c | |||
@@ -69,7 +69,7 @@ u32 __nvgpu_readl(struct gk20a *g, u32 r) | |||
69 | return v; | 69 | return v; |
70 | } | 70 | } |
71 | 71 | ||
72 | void nvgpu_writel_check(struct gk20a *g, u32 r, u32 v) | 72 | void nvgpu_writel_loop(struct gk20a *g, u32 r, u32 v) |
73 | { | 73 | { |
74 | struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); | 74 | struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); |
75 | 75 | ||