diff options
author | Tejal Kudav <tkudav@nvidia.com> | 2018-08-10 06:58:21 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-08-31 14:23:25 -0400 |
commit | 8c8cdacf7a022d1326ec519daa8b8da174aa8f3d (patch) | |
tree | 8e8b93c3b82e18c6178d645224b1fb23a33bb32e | |
parent | 90f268963c93025bdbb28a5a2b502cb738d5630d (diff) |
gpu: nvgpu: Use reset_enum to get mc engine mask
Currently, we need to include the MC hardware header in nvlink file
to generate reset mask.
We can use the reset_enum present in DEVICE_INFO table's IOCTRL entry
which is meant to index into NV_PMC_ENABLE_DEVICE register bitfields.
This allows us to not #include the MC hardware header in nvlink IP
file.
JIRA NVGPU-966
Change-Id: I037498038b12f795ee444916fb586355ebf04bb3
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1796819
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
-rw-r--r-- | drivers/gpu/nvgpu/gv100/nvlink_gv100.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gv100/nvlink_gv100.c b/drivers/gpu/nvgpu/gv100/nvlink_gv100.c index 0ad45540..b39e4165 100644 --- a/drivers/gpu/nvgpu/gv100/nvlink_gv100.c +++ b/drivers/gpu/nvgpu/gv100/nvlink_gv100.c | |||
@@ -2688,6 +2688,7 @@ void gv100_nvlink_get_connected_link_mask(u32 *link_mask) | |||
2688 | int gv100_nvlink_early_init(struct gk20a *g) | 2688 | int gv100_nvlink_early_init(struct gk20a *g) |
2689 | { | 2689 | { |
2690 | int err = 0; | 2690 | int err = 0; |
2691 | u32 mc_reset_nvlink_mask; | ||
2691 | 2692 | ||
2692 | if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_NVLINK)) | 2693 | if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_NVLINK)) |
2693 | return -EINVAL; | 2694 | return -EINVAL; |
@@ -2703,7 +2704,10 @@ int gv100_nvlink_early_init(struct gk20a *g) | |||
2703 | goto nvlink_init_exit; | 2704 | goto nvlink_init_exit; |
2704 | 2705 | ||
2705 | /* Enable NVLINK in MC */ | 2706 | /* Enable NVLINK in MC */ |
2706 | g->ops.mc.reset(g, mc_enable_nvlink_enabled_f()); | 2707 | mc_reset_nvlink_mask = BIT32(g->nvlink.ioctrl_table[0].reset_enum); |
2708 | nvgpu_log(g, gpu_dbg_nvlink, "mc_reset_nvlink_mask: 0x%x", | ||
2709 | mc_reset_nvlink_mask); | ||
2710 | g->ops.mc.reset(g, mc_reset_nvlink_mask); | ||
2707 | 2711 | ||
2708 | err = g->ops.nvlink.discover_link(g); | 2712 | err = g->ops.nvlink.discover_link(g); |
2709 | if (err || g->nvlink.discovered_links == 0) { | 2713 | if (err || g->nvlink.discovered_links == 0) { |