1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
|
/*
* Copyright (c) 2016-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_ACR_H
#define NVGPU_ACR_H
#include <nvgpu/falcon.h>
#include "gk20a/mm_gk20a.h"
#include "acr_lsfm.h"
#include "acr_flcnbl.h"
#include "acr_objlsfm.h"
#include "acr_objflcn.h"
struct nvgpu_firmware;
struct gk20a;
struct hs_acr_ops;
struct hs_acr;
struct nvgpu_acr;
#define HSBIN_ACR_BL_UCODE_IMAGE "pmu_bl.bin"
#define GM20B_HSBIN_ACR_PROD_UCODE "nv_acr_ucode_prod.bin"
#define GM20B_HSBIN_ACR_DBG_UCODE "nv_acr_ucode_dbg.bin"
#define HSBIN_ACR_UCODE_IMAGE "acr_ucode.bin"
#define HSBIN_ACR_PROD_UCODE "acr_ucode_prod.bin"
#define HSBIN_ACR_DBG_UCODE "acr_ucode_dbg.bin"
#define HSBIN_ACR_AHESASC_PROD_UCODE "acr_ahesasc_prod_ucode.bin"
#define HSBIN_ACR_ASB_PROD_UCODE "acr_asb_prod_ucode.bin"
#define HSBIN_ACR_AHESASC_DBG_UCODE "acr_ahesasc_dbg_ucode.bin"
#define HSBIN_ACR_ASB_DBG_UCODE "acr_asb_dbg_ucode.bin"
#define LSF_SEC2_UCODE_IMAGE_BIN "sec2_ucode_image.bin"
#define LSF_SEC2_UCODE_DESC_BIN "sec2_ucode_desc.bin"
#define LSF_SEC2_UCODE_SIG_BIN "sec2_sig.bin"
#define MAX_SUPPORTED_LSFM 3 /*PMU, FECS, GPCCS*/
#define ACR_COMPLETION_TIMEOUT_MS 10000 /*in msec */
#define PMU_SECURE_MODE (0x1)
#define PMU_LSFM_MANAGED (0x2)
struct bin_hdr {
/* 0x10de */
u32 bin_magic;
/* versioning of bin format */
u32 bin_ver;
/* Entire image size including this header */
u32 bin_size;
/*
* Header offset of executable binary metadata,
* start @ offset- 0x100 *
*/
u32 header_offset;
/*
* Start of executable binary data, start @
* offset- 0x200
*/
u32 data_offset;
/* Size of executable binary */
u32 data_size;
};
struct acr_fw_header {
u32 sig_dbg_offset;
u32 sig_dbg_size;
u32 sig_prod_offset;
u32 sig_prod_size;
u32 patch_loc;
u32 patch_sig;
u32 hdr_offset; /* This header points to acr_ucode_header_t210_load */
u32 hdr_size; /* Size of above header */
};
struct wpr_carveout_info {
u64 wpr_base;
u64 nonwpr_base;
u64 size;
};
/* ACR interfaces */
struct hs_flcn_bl {
char *bl_fw_name;
struct nvgpu_firmware *hs_bl_fw;
struct hsflcn_bl_desc *hs_bl_desc;
struct bin_hdr *hs_bl_bin_hdr;
struct nvgpu_mem hs_bl_ucode;
};
struct hs_acr {
u32 acr_type;
/* HS bootloader to validate & load ACR ucode */
struct hs_flcn_bl acr_hs_bl;
/* ACR ucode */
char *acr_fw_name;
struct nvgpu_firmware *acr_fw;
struct nvgpu_mem acr_ucode;
union {
struct flcn_bl_dmem_desc bl_dmem_desc;
struct flcn_bl_dmem_desc_v1 bl_dmem_desc_v1;
};
void *ptr_bl_dmem_desc;
u32 bl_dmem_desc_size;
union{
struct flcn_acr_desc *acr_dmem_desc;
struct flcn_acr_desc_v1 *acr_dmem_desc_v1;
};
/* Falcon used to execute ACR ucode */
struct nvgpu_falcon *acr_flcn;
int (*acr_flcn_setup_hw_and_bl_bootstrap)(struct gk20a *g,
struct hs_acr *acr_desc,
struct nvgpu_falcon_bl_info *bl_info);
};
#define ACR_DEFAULT 0U
#define ACR_AHESASC 1U
#define ACR_ASB 2U
struct nvgpu_acr {
struct gk20a *g;
u32 bootstrap_owner;
u32 max_supported_lsfm;
u32 capabilities;
/*
* non-wpr space to hold LSF ucodes,
* ACR does copy ucode from non-wpr to wpr
*/
struct nvgpu_mem ucode_blob;
/*
* Even though this mem_desc wouldn't be used,
* the wpr region needs to be reserved in the
* allocator in dGPU case.
*/
struct nvgpu_mem wpr_dummy;
/* ACR member for different types of ucode */
/* For older dgpu/tegra ACR cuode */
struct hs_acr acr;
/* ACR load split feature support */
struct hs_acr acr_ahesasc;
struct hs_acr acr_asb;
u32 pmu_args;
struct nvgpu_firmware *pmu_fw;
struct nvgpu_firmware *pmu_desc;
int (*prepare_ucode_blob)(struct gk20a *g, struct nvgpu_acr *acr);
void (*get_wpr_info)(struct gk20a *g, struct wpr_carveout_info *inf);
int (*alloc_blob_space)(struct gk20a *g, size_t size,
struct nvgpu_mem *mem);
int (*patch_wpr_info_to_ucode)(struct gk20a *g, struct nvgpu_acr *acr,
struct hs_acr *acr_desc, bool is_recovery);
int (*acr_fill_bl_dmem_desc)(struct gk20a *g,
struct nvgpu_acr *acr, struct hs_acr *acr_desc,
u32 *acr_ucode_header);
int (*bootstrap_hs_acr)(struct gk20a *g, struct nvgpu_acr *acr,
struct hs_acr *acr_desc);
void (*remove_support)(struct nvgpu_acr *acr);
};
#endif /* NVGPU_ACR_H */
|
