1 files changed, 5 insertions, 5 deletions

diff --git a/nvdebug.h b/nvdebug.h
index 7564f8c..9e0058d 100644
--- a/nvdebug.h
+++ b/nvdebug.h
@@ -1015,19 +1015,19 @@ typedef union {
   Page Table Entry (PTE) (13 bits) <--------------+        |
   Page Directory Entry (PDE) (13 bits) <-+        |        |
                                          ^        ^        ^
-                     Virtual address: [39, 25] [24, 12] [11, 0]
+                     Virtual address: [39, 26] [25, 12] [11, 0]
 
   == Figure 2: 128 KiB mode ==
   Page Offset (12 bits) <----------------------------------+
   Page Table Entry (PTE) (14 bits) <--------------+        |
   Page Directory Entry (PDE) (12 bits) <-+        |        |
                                          ^        ^        ^
-                     Virtual address: [39, 26] [25, 12] [11, 0]
+                     Virtual address: [39, 27] [26, 12] [11, 0]
 
 
   Support: Fermi, Kepler, Maxwell, Pascal*
   Note: *Pascal introduces Version 2 Page Tables, but is backwards-compatible.
-  Note: We only implement the 64-KiB-large-page mode in nvdebug.
+  Note: We only implement the 128-KiB-large-page mode in nvdebug.
 
   See also: mm_gk20a.c in nvgpu (Jetson GPU driver) and kern_gmmu_fmt_gm10x.c
             in open-gpu-kernel-modules (open-source NVRM variant). This is
@@ -1046,9 +1046,9 @@ typedef union {
   from the page table development process, and have no meaning now.
 */
 // Number of entries in the PDE and PTE levels
-static const int NV_MMU_PT_V1_SZ[2] = {8192, 8192};
+static const int NV_MMU_PT_V1_SZ[2] = {4096, 16384}; // 2^12 and 2^14
 // Which bit index is the least significant in indexing each page level
-static const int NV_MMU_PT_V1_LSB[2] = {25, 12};
+static const int NV_MMU_PT_V1_LSB[2] = {27, 12};
 
 // V1 Page Directory Entry target
 enum V1_PD_TARGET {