1 files changed, 288 insertions, 5 deletions

diff --git a/nvdebug.h b/nvdebug.h
index ca0f514..3ac8db4 100644
--- a/nvdebug.h
+++ b/nvdebug.h
@@ -2,6 +2,7 @@
  * SPDX-License-Identifier: MIT
  *
  * File outline:
+ * - Configuration options
  * - Runlist, preemption, and channel control (FIFO)
  * - Basic GPU information (MC)
  * - Detailed GPU information (PTOP, FUSE, and CE)
@@ -20,6 +21,27 @@
 // this, so declare as incomplete type to avoid pulling in the nvgpu headers.
 struct gk20a;
 
+// Uncomment to, upon BAR2 access failure, return a PRAMIN-based runlist pointer
+// in get_runlist_iter(). In order for this pointer to remain valid, PRAMIN
+// **must** not be moved during runlist traversal.
+// - The Jetson TX2 has no BAR2, and stores the runlist in VID_MEM, so this
+//   must be enabled to print the runlist on the TX2.
+// - On the A100 in Google Cloud and H100 in Paperspace, as of Aug 2024, this is
+//   needed, as nvdebug is not finding (at least) runlist0 mapped in BAR2/3.
+// Automatically disables printing Instance Block and Context State while
+// traversing the runlist, as these require conflicting uses of PRAMIN (it's
+// needed to search the page tables for the Instance Block in BAR2/3, and to
+// access anything in the Context State---aka CTXSW).
+#define FALLBACK_TO_PRAMIN
+
+// Starting offset for registers in the corresponding named range
+// Programmable First-In First-Out unit; also known as "Host"
+#define NV_PFIFO 0x00002000 // 8 KiB long; ends prior to 0x00004000
+// Programmable Channel Control System RAM
+#define NV_PCCSR 0x00800000 // 16 KiB long; ends prior to 0x00810000
+// Programmable TOPology registers
+#define NV_PTOP 0x00022400 // 1 KiB long; ends prior to 0x00022800
+
 /* Runlist Channel
   A timeslice group (TSG) is composed of channels. Each channel is a FIFO queue
   of GPU commands. These commands are typically queued from userspace.
@@ -202,7 +224,7 @@ typedef union {
   Support: Ampere, Hopper, Ada, [newer untested]
 */
 #define NV_RUNLIST_PREEMPT_GA100 0x098
-#define PREEMPT_TYPE_RUNLIST 0
+#define PREEMPT_TYPE_RUNLIST PREEMPT_TYPE_CHANNEL
 
 /*
   "Initiate a preempt of the engine by writing the bit associated with its
@@ -355,6 +377,14 @@ typedef union {
         uint64_t raw;
 } runlist_base_tu102_t;
 
+/*
+  LEN                   : Read/Write
+  OFFSET                : Read/Write
+  PREEMPTED_TSGID       : Read-only
+  VALID_PREEMPTED_TSGID : Read-only
+  IS_PENDING            : Read-only
+  PREEMPTED_OFFSET      : Read-only
+*/
 typedef union {
         struct {
                 uint16_t len:16;
@@ -416,6 +446,27 @@ typedef union {
         uint32_t raw;
 } runlist_channel_config_t;
 
+/* Context Switch Timeout Configuration
+  After a task's budget expires, there's a configurable grace period, a
+  "timeout", within which the context needs to complete. After this timeout
+  expires, an interrupt is raised to terminate the task.
+
+  This register configures if such a timeout is enabled and how long the
+  timeout is (the "period").
+
+  Support: Volta, Turing
+*/
+#define NV_PFIFO_ENG_CTXSW_TIMEOUT 0x00002A0C
+// Support: Ampere
+#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_CONFIG(i) (0x220+(i)*64)
+typedef union {
+        struct {
+                uint32_t period:31;
+                bool enabled:1;
+        } __attribute__((packed));
+        uint32_t raw;
+} ctxsw_timeout_t;
+
 /* Programmable Channel Control System RAM (PCCSR)
   512-entry array of channel control and status data structures.
 
@@ -477,8 +528,15 @@ typedef union {
                 bool busy:1;
                  uint32_t :3;
         } __attribute__((packed));
+        struct {
+                uint32_t word1;
+                uint32_t word2;
+        } __attribute__((packed));
         uint64_t raw;
-} channel_ctrl_t;
+} channel_ctrl_gf100_t;
+
+// TODO: Remove use of deprecated type name
+typedef channel_ctrl_gf100_t channel_ctrl_t;
 
 /* CHannel RAM (CHRAM) (PCCSR replacement on Ampere+)
   Starting with Ampere, channel IDs are no longer unique indexes into the
@@ -543,6 +601,8 @@ typedef union {
   Support: Fermi, Kepler, Maxwell, Pascal, Volta, Turing
 */
 #define NV_PFIFO_SCHED_DISABLE 0x00002630
+// Support: Ampere
+#define NV_RUNLIST_SCHED_DISABLE 0x094
 typedef union {
         struct {
                 bool runlist_0:1;
@@ -1018,7 +1078,7 @@ typedef union {
         struct {
                 uint32_t ptr:28;
                 enum INST_TARGET target:2;
-                 uint32_t :1;
+                 uint32_t :1; // disable_cya_debug for BAR2
                 bool is_virtual:1;
         } __attribute__((packed));
         uint32_t raw;
@@ -1091,6 +1151,9 @@ typedef union {
   Support: Tesla 2.0* through Ampere, Ada
    *FAULT_REPLAY_* fields are Pascal+ only
   See also: dev_ram.h (open-gpu-kernel-modules) or dev_ram.ref.txt (open-gpu-doc)
+
+  It appears that on Hopper, IS_VER2 continues to mean IS_VER2, but if unset, the
+  alternative is VER3.
 */
 #define NV_PRAMIN_PDB_CONFIG_OFF 0x200
 typedef union {
@@ -1101,7 +1164,7 @@ typedef union {
                 bool fault_replay_tex:1;
                 bool fault_replay_gcc:1;
                  uint32_t :4;
-                bool is_ver2:1;
+                bool is_ver2:1; // XXX: Not on Hopper. May be set or not for same page_dir.
                 bool is_64k_big_page:1;  // 128Kb otherwise
                 uint32_t page_dir_lo:20;
                 uint32_t page_dir_hi:32;
@@ -1421,6 +1484,182 @@ typedef union {
 } page_tbl_entry_v0_t;
 */
 
+/* Fifo Context RAM (RAMFC) and channel INstance RAM (RAMIN)
+
+  Each channel is configured with a 4 KiB instance block. The prefix of this
+  block is referred to as RAMFC and stores channel-specific state for the Host
+  (aka PFIFO).
+
+  "A GPU instance block is a block of memory that contains the state
+  for a GPU context.  A GPU context's instance block consists of Host state,
+  pointers to each engine's state, and memory management state.  A GPU instance
+  block also contains a pointer to a block of memory that contains that part of a
+  GPU context's state that a user-level driver may access.  A GPU instance block
+  fits within a single 4K-byte page of memory."
+
+  "The NV_RAMFC part of a GPU-instance block contains Host's part of a virtual
+  GPU's state.  Host is referred to as "FIFO". "FC" stands for FIFO Context.
+  When Host switches from serving one GPU context to serving a second, Host saves
+  state for the first GPU context to the first GPU context's RAMFC area, and loads
+  state for the second GPU context from the second GPU context's RAMFC area."
+
+  "Every Host word entry in RAMFC directly corresponds to a PRI-accessible
+  register.  For a description of the contents of a RAMFC entry, please see the
+  description of the corresponding register in "manuals/dev_pbdma.ref".  The
+  offsets of the fields within each entry in RAMFC match those of the
+  corresponding register in the associated PBDMA unit's PRI space."
+
+  In summary, RAMFC includes details such as the head and tail of the pushbuffer,
+  and RAMIN includes details such as the page table configuration(s).
+
+  The instance-global page table (as defined in the PDB field) is only used for
+  GPU engines which do not support subcontexts (non-VEID engines).
+
+  **Not all documented fields are currently populated below.**
+
+  Support: *Kepler, *Maxwell, *Pascal, Volta, Turing, Ampere, [newer untested]
+  *Pre-Volta GPUs do not support subcontexts.
+  See also: dev_ram.ref.txt and dev_pbdma.ref.txt in NVIDIA's open-gpu-doc
+*/
+
+// 16-byte (128-bit) substructure defining a subcontext configuration
+typedef struct {
+        page_dir_config_t pdb;
+        uint32_t pasid:20; // Process Address Space ID (PASID) used for ATS
+         uint32_t :11;
+        bool enable_ats:1; // Enable Address Translation Services (ATS)?
+         uint32_t pad;
+} __attribute__((packed)) subcontext_ctrl_t;
+
+typedef struct {
+// Start RAMFC (512 bytes)
+         uint32_t pad[43];
+        uint32_t fc_target:5; // NV_RAMFC_TARGET; off 43
+         uint32_t :27;
+         uint32_t pad2[17];
+        uint32_t fc_config_l2:1; // NV_RAMFC_CONFIG; off 61
+         uint32_t :3;
+        uint32_t fc_config_ce_split:1;
+        uint32_t fc_config_ce_no_throttle:1;
+         uint32_t :2;
+        uint32_t fc_config_is_priv:1; // ...AUTH_LEVEL
+         uint32_t :3;
+        uint32_t fc_config_userd_writeback:1; // ...USERD_WRITEBACK
+         uint32_t :19;
+         uint32_t pad3[1];
+        uint32_t fc_chan_info_scg:1; // ...SET_CHANNEL_INFO_SCG_TYPE
+         uint32_t :7;