1 files changed, 54 insertions, 13 deletions

diff --git a/nvdebug.h b/nvdebug.h
index f644500..409b013 100644
--- a/nvdebug.h
+++ b/nvdebug.h
@@ -484,6 +484,7 @@ typedef union {
 #define NV_CHIP_ID_AMPERE 0x170
 #define NV_CHIP_ID_HOPPER 0x180
 #define NV_CHIP_ID_ADA 0x190
+#define NV_CHIP_ID_BLACKWELL 0x1A0
 
 inline static const char* ARCH2NAME(uint32_t arch) {
         switch (arch) {
@@ -521,14 +522,18 @@ inline static const char* ARCH2NAME(uint32_t arch) {
                 return "Turing";
         case 0x17:
                 return "Ampere";
-        case 0x18:
+        case 0x18: // Despite the Chip ID, Hopper functionally proceeds Ada
                 return "Hopper";
         case 0x19:
                 return "Ada Lovelace";
-        case 0x20:
-                return "Blackwell (?)";
+        case 0x1A:
+                return "Blackwell";
+        case 0x1B:
+                return "Rubin (?)";
+        case 0x1F: // NVIDIA-internal simulator
+                return "AMODEL";
         default:
-                if (arch < 0x19)
+                if (arch < 0x1A)
                         return "[unknown historical architecture]";
                 else
                         return "[future]";
@@ -881,25 +886,57 @@ union reg_range {
 #define NV_CE_PCE_MAP_SIZE 32
 
 
-/* Location of the 1Kb instance block with page tables for BAR1 and BAR2.
-  Support: Fermi+ (?), Pascal
+/* Location of the 1Kb instance block with page tables for the BAR1/2 regions.
+
+  On the H100, the "BAR1 block" describes what is actually BAR2, and the
+  "BAR2 block" describes BAR4.
+
+  PTR : Upper 28 bits of the 40-bit, (4k-aligned) address where the instance
+        block configuration is for the listed BAR region.
+
+  "Hopper+ uses 64-bit BARs, so GPU BAR2 should be at BAR4/5 and GPU BAR1 is at
+  BAR2/3" (open-gpu-kernel-modules)
 */
+// Support: Fermi through Ampere, Ada
 #define NV_PBUS_BAR1_BLOCK 0x00001704
 #define NV_PBUS_BAR2_BLOCK 0x00001714
 typedef union {
         struct {
                 uint32_t ptr:28;
                 enum INST_TARGET target:2;
-                 uint32_t padding0:1;
+                 uint32_t :1;
                 bool is_virtual:1;
         } __attribute__((packed));
         uint32_t raw;
         struct {
                 uint32_t map:30;
-                 uint32_t padding1:2;
+                 uint32_t :2;
         } __attribute__((packed));
 } bar_config_block_t;
 
+// Support: Hopper, Blackwell+
+// This is a "VREG" (virtual register?) in the documentation, meaning that it
+// needs the VREG base added first.
+#define NV_VIRTUAL_FUNCTION_FULL_PHYS_OFFSET 0x00B80000
+#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK (NV_VIRTUAL_FUNCTION_FULL_PHYS_OFFSET+0x00000F70)
+typedef union {
+        struct {
+                bool is_pending:1;
+                bool is_outstanding:1;
+                 uint32_t :7;
+                bool is_virtual:1;
+                enum INST_TARGET target:2;
+                uint64_t ptr:40;
+                 uint32_t :12;
+        } __attribute__((packed));
+        uint64_t raw;
+        struct {
+                 uint32_t :10;
+                uint32_t map:22;
+                 uint32_t :32;
+        } __attribute__((packed));
+} bar_config_block_gh100_t;
+
 /* BAR0 PRAMIN (Private RAM Instance) window configuration
   One of the oldest ways to access video memory on NVIDIA GPUs is by using
   a configurable 1MB window into VRAM which is mapped into BAR0 (register)
@@ -914,21 +951,25 @@ typedef union {
   TARGET  : Which address space BASE points into
 
   Note: This seems to be set to 0x0bff00000 - 0x0c0000000 at least sometimes
-
-  Support: Tesla 2.0, Fermi, Kepler, Maxwell, Pascal, Turing, Ampere
 */
+// Support: Tesla 2.0, Fermi, Kepler, Maxwell, Pascal, Turing, Ampere, Ada
 #define NV_PBUS_BAR0_WINDOW 0x00001700
-#define NV_PRAMIN 0x00700000  // Goes until 0x00800000 (1MB window)
-#define NV_PRAMIN_LEN 0x00100000
+// On Hopper, and Blackwell+, TARGET must always be 0 (VIDMEM)
+// Support: Hopper, Blackwell+
+#define NV_XAL_EP_BAR0_WINDOW_BASE 0x0010fd40
 typedef union {
         struct {
                 uint32_t base:24;
                 enum INST_TARGET target:2;
-                 uint32_t padding0:6;
+                 uint32_t :6;
         } __attribute__((packed));
         uint32_t raw;
 } bar0_window_t;
 
+// Support: Tesla 2.0 through (at least) Blackwell
+#define NV_PRAMIN 0x00700000  // Goes until 0x00800000 (1MB window)
+#define NV_PRAMIN_LEN 0x00100000
+
 // Support: Tesla 2.0, Fermi, Kepler, Maxwell, Pascal, Turing, Ampere
 #define NV_PRAMIN_PDB_CONFIG_OFF 0x200
 typedef union {