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-rw-r--r--include/pstate/pstate.h74
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diff --git a/include/pstate/pstate.h b/include/pstate/pstate.h
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1/*
2 * general p state infrastructure
3 *
4 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24#ifndef NVGPU_PSTATE_H
25#define NVGPU_PSTATE_H
26
27#include "clk/clk.h"
28
29#define CTRL_PERF_PSTATE_TYPE_3X 0x3
30
31#define CTRL_PERF_PSTATE_P0 0
32#define CTRL_PERF_PSTATE_P5 5
33#define CTRL_PERF_PSTATE_P8 8
34
35#define CLK_SET_INFO_MAX_SIZE (32)
36
37struct gk20a;
38
39struct clk_set_info {
40 enum nv_pmu_clk_clkwhich clkwhich;
41 u32 nominal_mhz;
42 u16 min_mhz;
43 u16 max_mhz;
44};
45
46struct clk_set_info_list {
47 u32 num_info;
48 struct clk_set_info clksetinfo[CLK_SET_INFO_MAX_SIZE];
49};
50
51struct pstate {
52 struct boardobj super;
53 u32 num;
54 u8 lpwr_entry_idx;
55 struct clk_set_info_list clklist;
56};
57
58struct pstates {
59 struct boardobjgrp_e32 super;
60 u32 num_levels;
61 struct nvgpu_cond pstate_notifier_wq;
62 u32 is_pstate_switch_on;
63 struct nvgpu_mutex pstate_mutex; /* protect is_pstate_switch_on */
64};
65
66int gk20a_init_pstate_support(struct gk20a *g);
67void gk20a_deinit_pstate_support(struct gk20a *g);
68int gk20a_init_pstate_pmu_support(struct gk20a *g);
69
70struct clk_set_info *pstate_get_clk_set_info(struct gk20a *g, u32 pstate_num,
71 enum nv_pmu_clk_clkwhich clkwhich);
72struct pstate *pstate_find(struct gk20a *g, u32 num);
73
74#endif /* NVGPU_PSTATE_H */