1 files changed, 0 insertions, 136 deletions
diff --git a/include/pmgr/pwrpolicy.h b/include/pmgr/pwrpolicy.h
deleted file mode 100644
index 74f4937..0000000
--- a/include/pmgr/pwrpolicy.h
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
- * general power channel structures & definitions
- *
- * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-#ifndef NVGPU_PMGR_PWRPOLICY_H
-#define NVGPU_PMGR_PWRPOLICY_H
-#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
-#include "boardobj/boardobjgrp.h"
-#include "boardobj/boardobj.h"
-#include "ctrl/ctrlpmgr.h"
-#define PWR_POLICY_EXT_POWER_STATE_ID_COUNT 0x4U
-enum pwr_policy_limit_id {
-        PWR_POLICY_LIMIT_ID_MIN    = 0x00000000,
-        PWR_POLICY_LIMIT_ID_RATED,
-        PWR_POLICY_LIMIT_ID_MAX,
-        PWR_POLICY_LIMIT_ID_CURR,
-        PWR_POLICY_LIMIT_ID_BATT,
-};
-struct pwr_policy {
-        struct boardobj super;
-        u8 ch_idx;
-        u8 num_limit_inputs;
-        u8 limit_unit;
-        s32 limit_delta;
-        u32 limit_min;
-        u32 limit_rated;
-        u32 limit_max;
-        u32 limit_batt;
-        struct ctrl_pmgr_pwr_policy_info_integral integral;
-        struct ctrl_pmgr_pwr_policy_limit_arbitration limit_arb_min;
-        struct ctrl_pmgr_pwr_policy_limit_arbitration limit_arb_rated;
-        struct ctrl_pmgr_pwr_policy_limit_arbitration limit_arb_max;
-        struct ctrl_pmgr_pwr_policy_limit_arbitration limit_arb_batt;
-        struct ctrl_pmgr_pwr_policy_limit_arbitration limit_arb_curr;
-        u8 sample_mult;
-        enum ctrl_pmgr_pwr_policy_filter_type filter_type;
-        union ctrl_pmgr_pwr_policy_filter_param filter_param;
-};
-struct pwr_policy_ext_limit {
-        u8 policy_table_idx;
-        u32 limit;
-};
-struct pwr_policy_batt_workitem {
-        u32 power_state;
-        bool b_full_deflection;
-};
-struct pwr_policy_client_workitem {
-        u32 limit;
-        bool b_pending;
-};
-struct pwr_policy_relationship {
-        struct boardobj super;
-        u8 policy_idx;
-};
-struct pmgr_pwr_policy {
-        u8 version;
-        bool b_enabled;
-        struct nv_pmu_perf_domain_group_limits global_ceiling;
-        u8 policy_idxs[CTRL_PMGR_PWR_POLICY_IDX_NUM_INDEXES];
-        struct pwr_policy_ext_limit ext_limits[PWR_POLICY_EXT_POWER_STATE_ID_COUNT];
-        s32 ext_power_state;
-        u16 base_sample_period;
-        u16 min_client_sample_period;
-        u8 low_sampling_mult;
-        struct boardobjgrp_e32 pwr_policies;
-        struct boardobjgrp_e32 pwr_policy_rels;
-        struct boardobjgrp_e32 pwr_violations;
-        struct pwr_policy_client_workitem client_work_item;
-};
-struct pwr_policy_limit {
-        struct pwr_policy super;
-};
-struct pwr_policy_hw_threshold {
-        struct pwr_policy_limit super;
-        u8 threshold_idx;
-        u8 low_threshold_idx;
-        bool b_use_low_threshold;
-        u16 low_threshold_value;
-};
-struct pwr_policy_sw_threshold {
-        struct pwr_policy_limit super;
-        u8 threshold_idx;
-        u8 low_threshold_idx;
-        bool b_use_low_threshold;
-        u16 low_threshold_value;
-        u8 event_id;
-};
-union pwr_policy_data_union {
-        struct boardobj boardobj;
-        struct pwr_policy pwrpolicy;
-        struct pwr_policy_hw_threshold hw_threshold;
-        struct pwr_policy_sw_threshold sw_threshold;
-} ;
-#define PMGR_GET_PWR_POLICY(g, policy_idx)                                 \
-        ((struct pwr_policy *)BOARDOBJGRP_OBJ_GET_BY_IDX(                                 \
-                &(g->pmgr_pmu.pmgr_policyobjs.pwr_policies.super), (policy_idx)))
-#define PMGR_PWR_POLICY_INCREMENT_LIMIT_INPUT_COUNT(ppolicy)                 \
-        ((ppolicy)->num_limit_inputs++)
-int pmgr_policy_sw_setup(struct gk20a *g);
-#endif /* NVGPU_PMGR_PWRPOLICY_H */

diff --git a/include/pmgr/pwrpolicy.h b/include/pmgr/pwrpolicy.h deleted file mode 100644 index 74f4937..0000000 --- a/include/pmgr/pwrpolicy.h +++ /dev/null
@@ -1,136 +0,0 @@
1	/*
2	* general power channel structures & definitions
3	*
4	* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
5	*
6	* Permission is hereby granted, free of charge, to any person obtaining a
7	* copy of this software and associated documentation files (the "Software"),
8	* to deal in the Software without restriction, including without limitation
9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
10	* and/or sell copies of the Software, and to permit persons to whom the
11	* Software is furnished to do so, subject to the following conditions:
12	*
13	* The above copyright notice and this permission notice shall be included in
14	* all copies or substantial portions of the Software.
15	*
16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22	* DEALINGS IN THE SOFTWARE.
23	*/
24	#ifndef NVGPU_PMGR_PWRPOLICY_H
25	#define NVGPU_PMGR_PWRPOLICY_H
26
27	#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
28	#include "boardobj/boardobjgrp.h"
29	#include "boardobj/boardobj.h"
30	#include "ctrl/ctrlpmgr.h"
31
32	#define PWR_POLICY_EXT_POWER_STATE_ID_COUNT 0x4U
33
34	enum pwr_policy_limit_id {
35	PWR_POLICY_LIMIT_ID_MIN = 0x00000000,
36	PWR_POLICY_LIMIT_ID_RATED,
37	PWR_POLICY_LIMIT_ID_MAX,
38	PWR_POLICY_LIMIT_ID_CURR,
39	PWR_POLICY_LIMIT_ID_BATT,
40	};
41
42	struct pwr_policy {
43	struct boardobj super;
44	u8 ch_idx;
45	u8 num_limit_inputs;
46	u8 limit_unit;
47	s32 limit_delta;
48	u32 limit_min;
49	u32 limit_rated;
50	u32 limit_max;
51	u32 limit_batt;
52	struct ctrl_pmgr_pwr_policy_info_integral integral;
53	struct ctrl_pmgr_pwr_policy_limit_arbitration limit_arb_min;
54	struct ctrl_pmgr_pwr_policy_limit_arbitration limit_arb_rated;
55	struct ctrl_pmgr_pwr_policy_limit_arbitration limit_arb_max;
56	struct ctrl_pmgr_pwr_policy_limit_arbitration limit_arb_batt;
57	struct ctrl_pmgr_pwr_policy_limit_arbitration limit_arb_curr;
58	u8 sample_mult;
59	enum ctrl_pmgr_pwr_policy_filter_type filter_type;
60	union ctrl_pmgr_pwr_policy_filter_param filter_param;
61	};
62
63	struct pwr_policy_ext_limit {
64	u8 policy_table_idx;
65	u32 limit;
66	};
67
68	struct pwr_policy_batt_workitem {
69	u32 power_state;
70	bool b_full_deflection;
71	};
72
73	struct pwr_policy_client_workitem {
74	u32 limit;
75	bool b_pending;
76	};
77
78	struct pwr_policy_relationship {
79	struct boardobj super;
80	u8 policy_idx;
81	};
82
83	struct pmgr_pwr_policy {
84	u8 version;
85	bool b_enabled;
86	struct nv_pmu_perf_domain_group_limits global_ceiling;
87	u8 policy_idxs[CTRL_PMGR_PWR_POLICY_IDX_NUM_INDEXES];
88	struct pwr_policy_ext_limit ext_limits[PWR_POLICY_EXT_POWER_STATE_ID_COUNT];
89	s32 ext_power_state;
90	u16 base_sample_period;
91	u16 min_client_sample_period;
92	u8 low_sampling_mult;
93	struct boardobjgrp_e32 pwr_policies;
94	struct boardobjgrp_e32 pwr_policy_rels;
95	struct boardobjgrp_e32 pwr_violations;
96	struct pwr_policy_client_workitem client_work_item;
97	};
98
99	struct pwr_policy_limit {
100	struct pwr_policy super;
101	};
102
103	struct pwr_policy_hw_threshold {
104	struct pwr_policy_limit super;
105	u8 threshold_idx;
106	u8 low_threshold_idx;
107	bool b_use_low_threshold;
108	u16 low_threshold_value;
109	};
110
111	struct pwr_policy_sw_threshold {
112	struct pwr_policy_limit super;
113	u8 threshold_idx;
114	u8 low_threshold_idx;
115	bool b_use_low_threshold;
116	u16 low_threshold_value;
117	u8 event_id;
118	};
119
120	union pwr_policy_data_union {
121	struct boardobj boardobj;
122	struct pwr_policy pwrpolicy;
123	struct pwr_policy_hw_threshold hw_threshold;
124	struct pwr_policy_sw_threshold sw_threshold;
125	} ;
126
127	#define PMGR_GET_PWR_POLICY(g, policy_idx) \
128	((struct pwr_policy *)BOARDOBJGRP_OBJ_GET_BY_IDX( \
129	&(g->pmgr_pmu.pmgr_policyobjs.pwr_policies.super), (policy_idx)))
130
131	#define PMGR_PWR_POLICY_INCREMENT_LIMIT_INPUT_COUNT(ppolicy) \
132	((ppolicy)->num_limit_inputs++)
133
134	int pmgr_policy_sw_setup(struct gk20a *g);
135
136	#endif /* NVGPU_PMGR_PWRPOLICY_H */