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-rw-r--r--include/pmgr/pwrpolicy.c782
1 files changed, 0 insertions, 782 deletions
diff --git a/include/pmgr/pwrpolicy.c b/include/pmgr/pwrpolicy.c
deleted file mode 100644
index 3bf6f32..0000000
--- a/include/pmgr/pwrpolicy.c
+++ /dev/null
@@ -1,782 +0,0 @@
1/*
2 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#include <nvgpu/bios.h>
24#include <nvgpu/bug.h>
25#include <nvgpu/gk20a.h>
26
27#include "pwrpolicy.h"
28#include "boardobj/boardobjgrp.h"
29#include "boardobj/boardobjgrp_e32.h"
30#include "gp106/bios_gp106.h"
31
32#define _pwr_policy_limitarboutputget_helper(p_limit_arb) (p_limit_arb)->output
33#define _pwr_policy_limitdeltaapply(limit, delta) ((u32)max(((s32)limit) + (delta), 0))
34
35static u32 _pwr_policy_limitarbinputset_helper(struct gk20a *g,
36 struct ctrl_pmgr_pwr_policy_limit_arbitration *p_limit_arb,
37 u8 client_idx,
38 u32 limit_value)
39{
40 u8 indx;
41 bool b_found = false;
42 u32 status = 0;
43 u32 output = limit_value;
44
45 for (indx = 0; indx< p_limit_arb->num_inputs; indx++) {
46 if (p_limit_arb->inputs[indx].pwr_policy_idx == client_idx) {
47 p_limit_arb->inputs[indx].limit_value = limit_value;
48 b_found = true;
49 } else if (p_limit_arb->b_arb_max) {
50 output = max(output, p_limit_arb->inputs[indx].limit_value);
51 } else {
52 output = min(output, p_limit_arb->inputs[indx].limit_value);
53 }
54 }
55
56 if (!b_found) {
57 if (p_limit_arb->num_inputs <
58 CTRL_PMGR_PWR_POLICY_MAX_LIMIT_INPUTS) {
59 p_limit_arb->inputs[
60 p_limit_arb->num_inputs].pwr_policy_idx = client_idx;
61 p_limit_arb->inputs[
62 p_limit_arb->num_inputs].limit_value = limit_value;
63 p_limit_arb->num_inputs++;
64 } else {
65 nvgpu_err(g, "No entries remaining for clientIdx=%d",
66 client_idx);
67 status = -EINVAL;
68 }
69 }
70
71 if (!status) {
72 p_limit_arb->output = output;
73 }
74
75 return status;
76}
77
78static u32 _pwr_policy_limitid_translate(struct gk20a *g,
79 struct pwr_policy *ppolicy,
80 enum pwr_policy_limit_id limit_id,
81 struct ctrl_pmgr_pwr_policy_limit_arbitration **p_limit_arb,
82 struct ctrl_pmgr_pwr_policy_limit_arbitration **p_limit_arb_sec)
83{
84 u32 status = 0;
85
86 switch (limit_id) {
87 case PWR_POLICY_LIMIT_ID_MIN:
88 *p_limit_arb = &ppolicy->limit_arb_min;
89 break;
90
91 case PWR_POLICY_LIMIT_ID_RATED:
92 *p_limit_arb = &ppolicy->limit_arb_rated;
93
94 if (p_limit_arb_sec != NULL) {
95 *p_limit_arb_sec = &ppolicy->limit_arb_curr;
96 }
97 break;
98
99 case PWR_POLICY_LIMIT_ID_MAX:
100 *p_limit_arb = &ppolicy->limit_arb_max;
101 break;
102
103 case PWR_POLICY_LIMIT_ID_CURR:
104 *p_limit_arb = &ppolicy->limit_arb_curr;
105 break;
106
107 case PWR_POLICY_LIMIT_ID_BATT:
108 *p_limit_arb = &ppolicy->limit_arb_batt;
109 break;
110
111 default:
112 nvgpu_err(g, "Unsupported limitId=%d",
113 limit_id);
114 status = -EINVAL;
115 break;
116 }
117
118 return status;
119}
120
121static u32 _pwr_policy_limitarbinputset(struct gk20a *g,
122 struct pwr_policy *ppolicy,
123 enum pwr_policy_limit_id limit_id,
124 u8 client_idx,
125 u32 limit)
126{
127 u32 status = 0;
128 struct ctrl_pmgr_pwr_policy_limit_arbitration *p_limit_arb = NULL;
129 struct ctrl_pmgr_pwr_policy_limit_arbitration *p_limit_arb_sec = NULL;
130
131 status = _pwr_policy_limitid_translate(g,
132 ppolicy,
133 limit_id,
134 &p_limit_arb,
135 &p_limit_arb_sec);
136 if (status) {
137 goto exit;
138 }
139
140 status = _pwr_policy_limitarbinputset_helper(g, p_limit_arb, client_idx, limit);
141 if (status) {
142 nvgpu_err(g,
143 "Error setting client limit value: status=0x%08x, limitId=0x%x, clientIdx=0x%x, limit=%d",
144 status, limit_id, client_idx, limit);
145 goto exit;
146 }
147
148 if (NULL != p_limit_arb_sec) {
149 status = _pwr_policy_limitarbinputset_helper(g, p_limit_arb_sec,
150 CTRL_PMGR_PWR_POLICY_LIMIT_INPUT_CLIENT_IDX_RM,
151 _pwr_policy_limitarboutputget_helper(p_limit_arb));
152 }
153
154exit:
155 return status;
156}
157
158static inline void _pwr_policy_limitarbconstruct(
159 struct ctrl_pmgr_pwr_policy_limit_arbitration *p_limit_arb,
160 bool b_arb_max)
161{
162 p_limit_arb->num_inputs = 0;
163 p_limit_arb->b_arb_max = b_arb_max;
164}
165
166static u32 _pwr_policy_limitarboutputget(struct gk20a *g,
167 struct pwr_policy *ppolicy,
168 enum pwr_policy_limit_id limit_id)
169{
170 u32 status = 0;
171 struct ctrl_pmgr_pwr_policy_limit_arbitration *p_limit_arb = NULL;
172
173 status = _pwr_policy_limitid_translate(g,
174 ppolicy,
175 limit_id,
176 &p_limit_arb,
177 NULL);
178 if (status) {
179 return 0;
180 }
181
182 return _pwr_policy_limitarboutputget_helper(p_limit_arb);
183}
184
185static int _pwr_domains_pmudatainit_hw_threshold(struct gk20a *g,
186 struct boardobj *board_obj_ptr,
187 struct nv_pmu_boardobj *ppmudata)
188{
189 struct nv_pmu_pmgr_pwr_policy_hw_threshold *pmu_hw_threshold_data;
190 struct pwr_policy_hw_threshold *p_hw_threshold;
191 struct pwr_policy *p_pwr_policy;
192 struct nv_pmu_pmgr_pwr_policy *pmu_pwr_policy;
193 int status = 0;
194
195 status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata);
196 if (status) {
197 nvgpu_err(g,
198 "error updating pmu boardobjgrp for pwr sensor 0x%x",
199 status);
200 status = -ENOMEM;
201 goto done;
202 }
203
204 p_hw_threshold = (struct pwr_policy_hw_threshold *)board_obj_ptr;
205 pmu_hw_threshold_data = (struct nv_pmu_pmgr_pwr_policy_hw_threshold *) ppmudata;
206 pmu_pwr_policy = (struct nv_pmu_pmgr_pwr_policy *) ppmudata;
207 p_pwr_policy = (struct pwr_policy *)&(p_hw_threshold->super.super);
208
209 pmu_pwr_policy->ch_idx = 0;
210 pmu_pwr_policy->limit_unit = p_pwr_policy->limit_unit;
211 pmu_pwr_policy->num_limit_inputs = p_pwr_policy->num_limit_inputs;
212
213 pmu_pwr_policy->limit_min = _pwr_policy_limitdeltaapply(
214 _pwr_policy_limitarboutputget(g, p_pwr_policy,
215 PWR_POLICY_LIMIT_ID_MIN),
216 p_pwr_policy->limit_delta);
217
218 pmu_pwr_policy->limit_max = _pwr_policy_limitdeltaapply(
219 _pwr_policy_limitarboutputget(g, p_pwr_policy,
220 PWR_POLICY_LIMIT_ID_MAX),
221 p_pwr_policy->limit_delta);
222
223 pmu_pwr_policy->limit_curr = _pwr_policy_limitdeltaapply(
224 _pwr_policy_limitarboutputget(g, p_pwr_policy,
225 PWR_POLICY_LIMIT_ID_CURR),
226 p_pwr_policy->limit_delta);
227
228 memcpy(&pmu_pwr_policy->integral, &p_pwr_policy->integral,
229 sizeof(struct ctrl_pmgr_pwr_policy_info_integral));
230
231 pmu_pwr_policy->sample_mult = p_pwr_policy->sample_mult;
232 pmu_pwr_policy->filter_type = p_pwr_policy->filter_type;
233 pmu_pwr_policy->filter_param = p_pwr_policy->filter_param;
234
235 pmu_hw_threshold_data->threshold_idx = p_hw_threshold->threshold_idx;
236 pmu_hw_threshold_data->low_threshold_idx = p_hw_threshold->low_threshold_idx;
237 pmu_hw_threshold_data->b_use_low_threshold = p_hw_threshold->b_use_low_threshold;
238 pmu_hw_threshold_data->low_threshold_value = p_hw_threshold->low_threshold_value;
239
240 if (BOARDOBJ_GET_TYPE(board_obj_ptr) ==
241 CTRL_PMGR_PWR_POLICY_TYPE_SW_THRESHOLD) {
242 struct nv_pmu_pmgr_pwr_policy_sw_threshold *pmu_sw_threshold_data;
243 struct pwr_policy_sw_threshold *p_sw_threshold;
244
245 p_sw_threshold = (struct pwr_policy_sw_threshold *)board_obj_ptr;
246 pmu_sw_threshold_data =
247 (struct nv_pmu_pmgr_pwr_policy_sw_threshold *) ppmudata;
248 pmu_sw_threshold_data->event_id =
249 p_sw_threshold->event_id;
250 }
251done:
252 return status;
253}
254
255static struct boardobj *construct_pwr_policy(struct gk20a *g,
256 void *pargs, u16 pargs_size, u8 type)
257{
258 struct boardobj *board_obj_ptr = NULL;
259 int status;
260 struct pwr_policy_hw_threshold *pwrpolicyhwthreshold;
261 struct pwr_policy *pwrpolicy;
262 struct pwr_policy *pwrpolicyparams = (struct pwr_policy*)pargs;
263 struct pwr_policy_hw_threshold *hwthreshold = (struct pwr_policy_hw_threshold*)pargs;
264
265 status = boardobj_construct_super(g, &board_obj_ptr,
266 pargs_size, pargs);
267 if (status) {
268 return NULL;
269 }
270
271 pwrpolicyhwthreshold = (struct pwr_policy_hw_threshold*)board_obj_ptr;
272 pwrpolicy = (struct pwr_policy *)board_obj_ptr;
273
274 nvgpu_log_fn(g, "min=%u rated=%u max=%u",
275 pwrpolicyparams->limit_min,
276 pwrpolicyparams->limit_rated,
277 pwrpolicyparams->limit_max);
278
279 /* Set Super class interfaces */
280 board_obj_ptr->pmudatainit = _pwr_domains_pmudatainit_hw_threshold;
281
282 pwrpolicy->ch_idx = pwrpolicyparams->ch_idx;
283 pwrpolicy->num_limit_inputs = 0;
284 pwrpolicy->limit_unit = pwrpolicyparams->limit_unit;
285 pwrpolicy->filter_type = (enum ctrl_pmgr_pwr_policy_filter_type)(pwrpolicyparams->filter_type);
286 pwrpolicy->sample_mult = pwrpolicyparams->sample_mult;
287 switch (pwrpolicy->filter_type)
288 {
289 case CTRL_PMGR_PWR_POLICY_FILTER_TYPE_NONE:
290 break;
291
292 case CTRL_PMGR_PWR_POLICY_FILTER_TYPE_BLOCK:
293 pwrpolicy->filter_param.block.block_size =
294 pwrpolicyparams->filter_param.block.block_size;
295 break;
296
297 case CTRL_PMGR_PWR_POLICY_FILTER_TYPE_MOVING_AVERAGE:
298 pwrpolicy->filter_param.moving_avg.window_size =
299 pwrpolicyparams->filter_param.moving_avg.window_size;
300 break;
301
302 case CTRL_PMGR_PWR_POLICY_FILTER_TYPE_IIR:
303 pwrpolicy->filter_param.iir.divisor = pwrpolicyparams->filter_param.iir.divisor;
304 break;
305
306 default:
307 nvgpu_err(g, "Error: unrecognized Power Policy filter type: %d",
308 pwrpolicy->filter_type);
309 }
310
311 _pwr_policy_limitarbconstruct(&pwrpolicy->limit_arb_curr, false);
312
313 pwrpolicy->limit_delta = 0;
314
315 _pwr_policy_limitarbconstruct(&pwrpolicy->limit_arb_min, true);
316 status = _pwr_policy_limitarbinputset(g,
317 pwrpolicy,
318 PWR_POLICY_LIMIT_ID_MIN,
319 CTRL_PMGR_PWR_POLICY_LIMIT_INPUT_CLIENT_IDX_RM,
320 pwrpolicyparams->limit_min);
321
322 _pwr_policy_limitarbconstruct(&pwrpolicy->limit_arb_max, false);
323 status = _pwr_policy_limitarbinputset(g,
324 pwrpolicy,
325 PWR_POLICY_LIMIT_ID_MAX,
326 CTRL_PMGR_PWR_POLICY_LIMIT_INPUT_CLIENT_IDX_RM,
327 pwrpolicyparams->limit_max);
328
329 _pwr_policy_limitarbconstruct(&pwrpolicy->limit_arb_rated, false);
330 status = _pwr_policy_limitarbinputset(g,
331 pwrpolicy,
332 PWR_POLICY_LIMIT_ID_RATED,
333 CTRL_PMGR_PWR_POLICY_LIMIT_INPUT_CLIENT_IDX_RM,
334 pwrpolicyparams->limit_rated);
335
336 _pwr_policy_limitarbconstruct(&pwrpolicy->limit_arb_batt, false);
337 status = _pwr_policy_limitarbinputset(g,
338 pwrpolicy,
339 PWR_POLICY_LIMIT_ID_BATT,
340 CTRL_PMGR_PWR_POLICY_LIMIT_INPUT_CLIENT_IDX_RM,
341 ((pwrpolicyparams->limit_batt != 0U) ?
342 pwrpolicyparams->limit_batt:
343 CTRL_PMGR_PWR_POLICY_LIMIT_MAX));
344
345 memcpy(&pwrpolicy->integral, &pwrpolicyparams->integral,
346 sizeof(struct ctrl_pmgr_pwr_policy_info_integral));
347
348 pwrpolicyhwthreshold->threshold_idx = hwthreshold->threshold_idx;
349 pwrpolicyhwthreshold->b_use_low_threshold = hwthreshold->b_use_low_threshold;
350 pwrpolicyhwthreshold->low_threshold_idx = hwthreshold->low_threshold_idx;
351 pwrpolicyhwthreshold->low_threshold_value = hwthreshold->low_threshold_value;
352
353 if (type == CTRL_PMGR_PWR_POLICY_TYPE_SW_THRESHOLD) {
354 struct pwr_policy_sw_threshold *pwrpolicyswthreshold;
355 struct pwr_policy_sw_threshold *swthreshold =
356 (struct pwr_policy_sw_threshold*)pargs;
357
358 pwrpolicyswthreshold = (struct pwr_policy_sw_threshold*)board_obj_ptr;
359 pwrpolicyswthreshold->event_id = swthreshold->event_id;
360 }
361
362 nvgpu_log_info(g, " Done");
363
364 return board_obj_ptr;
365}
366
367static int _pwr_policy_construct_WAR_SW_Threshold_policy(struct gk20a *g,
368 struct pmgr_pwr_policy *ppwrpolicyobjs,
369 union pwr_policy_data_union *ppwrpolicydata,
370 u16 pwr_policy_size,
371 u32 obj_index)
372{
373 int status = 0;
374 struct boardobj *boardobj;
375
376 /* WARN policy */
377 ppwrpolicydata->pwrpolicy.limit_unit = 0;
378 ppwrpolicydata->pwrpolicy.limit_min = 10000;
379 ppwrpolicydata->pwrpolicy.limit_rated = 100000;
380 ppwrpolicydata->pwrpolicy.limit_max = 100000;
381 ppwrpolicydata->sw_threshold.threshold_idx = 1;
382 ppwrpolicydata->pwrpolicy.filter_type =
383 CTRL_PMGR_PWR_POLICY_FILTER_TYPE_MOVING_AVERAGE;
384 ppwrpolicydata->pwrpolicy.sample_mult = 5;
385
386 /* Filled the entry.filterParam value in the filterParam */
387 ppwrpolicydata->pwrpolicy.filter_param.moving_avg.window_size = 10;
388
389 ppwrpolicydata->sw_threshold.event_id = 0x01;
390
391 ppwrpolicydata->boardobj.type = CTRL_PMGR_PWR_POLICY_TYPE_SW_THRESHOLD;
392
393 boardobj = construct_pwr_policy(g, ppwrpolicydata,
394 pwr_policy_size, ppwrpolicydata->boardobj.type);
395
396 if (!boardobj) {
397 nvgpu_err(g,
398 "unable to create pwr policy for type %d", ppwrpolicydata->boardobj.type);
399 status = -EINVAL;
400 goto done;
401 }
402
403 status = boardobjgrp_objinsert(&ppwrpolicyobjs->pwr_policies.super,
404 boardobj, obj_index);
405
406 if (status) {
407 nvgpu_err(g,
408 "unable to insert pwr policy boardobj for %d", obj_index);
409 status = -EINVAL;
410 goto done;
411 }
412done:
413 return status;
414}
415
416struct pwr_policy_3x_header_unpacked {
417 u8 version;
418 u8 header_size;
419 u8 table_entry_size;
420 u8 num_table_entries;
421 u16 base_sample_period;
422 u16 min_client_sample_period;
423 u8 table_rel_entry_size;
424 u8 num_table_rel_entries;
425 u8 tgp_policy_idx;
426 u8 rtp_policy_idx;
427 u8 mxm_policy_idx;
428 u8 dnotifier_policy_idx;
429 u32 d2_limit;
430 u32 d3_limit;
431 u32 d4_limit;
432 u32 d5_limit;
433 u8 low_sampling_mult;
434 u8 pwr_tgt_policy_idx;
435 u8 pwr_tgt_floor_policy_idx;
436 u8 sm_bus_policy_idx;
437 u8 table_viol_entry_size;
438 u8 num_table_viol_entries;
439};
440
441#define __UNPACK_FIELD(unpacked, packed, field) \
442 __builtin_memcpy(&unpacked->field, &packed->field, \
443 sizeof(unpacked->field))
444
445static inline void devinit_unpack_pwr_policy_header(
446 struct pwr_policy_3x_header_unpacked *unpacked,
447 struct pwr_policy_3x_header_struct *packed)
448{
449 __UNPACK_FIELD(unpacked, packed, version);
450 __UNPACK_FIELD(unpacked, packed, header_size);
451 __UNPACK_FIELD(unpacked, packed, table_entry_size);
452 __UNPACK_FIELD(unpacked, packed, num_table_entries);
453 __UNPACK_FIELD(unpacked, packed, base_sample_period);
454 __UNPACK_FIELD(unpacked, packed, min_client_sample_period);
455 __UNPACK_FIELD(unpacked, packed, table_rel_entry_size);
456 __UNPACK_FIELD(unpacked, packed, num_table_rel_entries);
457 __UNPACK_FIELD(unpacked, packed, tgp_policy_idx);
458 __UNPACK_FIELD(unpacked, packed, rtp_policy_idx);
459 __UNPACK_FIELD(unpacked, packed, mxm_policy_idx);
460 __UNPACK_FIELD(unpacked, packed, dnotifier_policy_idx);
461 __UNPACK_FIELD(unpacked, packed, d2_limit);
462 __UNPACK_FIELD(unpacked, packed, d3_limit);
463 __UNPACK_FIELD(unpacked, packed, d4_limit);
464 __UNPACK_FIELD(unpacked, packed, d5_limit);
465 __UNPACK_FIELD(unpacked, packed, low_sampling_mult);
466 __UNPACK_FIELD(unpacked, packed, pwr_tgt_policy_idx);
467 __UNPACK_FIELD(unpacked, packed, pwr_tgt_floor_policy_idx);
468 __UNPACK_FIELD(unpacked, packed, sm_bus_policy_idx);
469 __UNPACK_FIELD(unpacked, packed, table_viol_entry_size);
470 __UNPACK_FIELD(unpacked, packed, num_table_viol_entries);
471}
472
473struct pwr_policy_3x_entry_unpacked {
474 u8 flags0;
475 u8 ch_idx;
476 u32 limit_min;
477 u32 limit_rated;
478 u32 limit_max;
479 u32 param0;
480 u32 param1;
481 u32 param2;
482 u32 param3;
483 u32 limit_batt;
484 u8 flags1;
485 u8 past_length;
486 u8 next_length;
487 u16 ratio_min;
488 u16 ratio_max;
489 u8 sample_mult;
490 u32 filter_param;
491};
492
493static inline void devinit_unpack_pwr_policy_entry(
494 struct pwr_policy_3x_entry_unpacked *unpacked,
495 struct pwr_policy_3x_entry_struct *packed)
496{
497 __UNPACK_FIELD(unpacked, packed, flags0);
498 __UNPACK_FIELD(unpacked, packed, ch_idx);
499 __UNPACK_FIELD(unpacked, packed, limit_min);
500 __UNPACK_FIELD(unpacked, packed, limit_rated);
501 __UNPACK_FIELD(unpacked, packed, limit_max);
502 __UNPACK_FIELD(unpacked, packed, param0);
503 __UNPACK_FIELD(unpacked, packed, param1);
504 __UNPACK_FIELD(unpacked, packed, param2);
505 __UNPACK_FIELD(unpacked, packed, param3);
506 __UNPACK_FIELD(unpacked, packed, limit_batt);
507 __UNPACK_FIELD(unpacked, packed, flags1);
508 __UNPACK_FIELD(unpacked, packed, past_length);
509 __UNPACK_FIELD(unpacked, packed, next_length);
510 __UNPACK_FIELD(unpacked, packed, ratio_min);
511 __UNPACK_FIELD(unpacked, packed, ratio_max);
512 __UNPACK_FIELD(unpacked, packed, sample_mult);
513 __UNPACK_FIELD(unpacked, packed, filter_param);
514}
515
516static int devinit_get_pwr_policy_table(struct gk20a *g,
517 struct pmgr_pwr_policy *ppwrpolicyobjs)
518{
519 int status = 0;
520 u8 *ptr = NULL;
521 struct boardobj *boardobj;
522 struct pwr_policy_3x_header_struct *packed_hdr;
523 struct pwr_policy_3x_header_unpacked hdr;
524 u32 index;
525 u32 obj_index = 0;
526 u16 pwr_policy_size;
527 bool integral_control = false;
528 u32 hw_threshold_policy_index = 0;
529 union pwr_policy_data_union pwr_policy_data;
530
531 nvgpu_log_info(g, " ");
532
533 ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
534 g->bios.perf_token, POWER_CAPPING_TABLE);
535 if (ptr == NULL) {
536 status = -EINVAL;
537 goto done;
538 }
539
540 packed_hdr = (struct pwr_policy_3x_header_struct *)ptr;
541
542 if (packed_hdr->version !=
543 VBIOS_POWER_POLICY_VERSION_3X) {
544 status = -EINVAL;
545 goto done;
546 }
547
548 if (packed_hdr->header_size <
549 VBIOS_POWER_POLICY_3X_HEADER_SIZE_25) {
550 status = -EINVAL;
551 goto done;
552 }
553
554 if (packed_hdr->table_entry_size <
555 VBIOS_POWER_POLICY_3X_ENTRY_SIZE_2E) {
556 status = -EINVAL;
557 goto done;
558 }
559
560 /* unpack power policy table header */
561 devinit_unpack_pwr_policy_header(&hdr, packed_hdr);
562
563 ptr += (u32)hdr.header_size;
564
565 for (index = 0; index < hdr.num_table_entries;
566 index++, ptr += (u32)hdr.table_entry_size) {
567
568 struct pwr_policy_3x_entry_struct *packed_entry;
569 struct pwr_policy_3x_entry_unpacked entry;
570
571 u8 class_type;
572
573 packed_entry = (struct pwr_policy_3x_entry_struct *)ptr;
574
575 class_type = (u8)BIOS_GET_FIELD(
576 packed_entry->flags0,
577 NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS);
578
579 if (class_type != NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS_HW_THRESHOLD) {
580 continue;
581 }
582
583 /* unpack power policy table entry */
584 devinit_unpack_pwr_policy_entry(&entry, packed_entry);
585
586 ppwrpolicyobjs->version =
587 CTRL_PMGR_PWR_POLICY_TABLE_VERSION_3X;
588 ppwrpolicyobjs->base_sample_period = hdr.base_sample_period;
589 ppwrpolicyobjs->min_client_sample_period =
590 hdr.min_client_sample_period;
591 ppwrpolicyobjs->low_sampling_mult = hdr.low_sampling_mult;
592
593 ppwrpolicyobjs->policy_idxs[1] = hdr.tgp_policy_idx;
594 ppwrpolicyobjs->policy_idxs[0] = hdr.rtp_policy_idx;
595 ppwrpolicyobjs->policy_idxs[2] = hdr.mxm_policy_idx;
596 ppwrpolicyobjs->policy_idxs[3] = hdr.dnotifier_policy_idx;
597 ppwrpolicyobjs->ext_limits[0].limit = hdr.d2_limit;
598 ppwrpolicyobjs->ext_limits[1].limit = hdr.d3_limit;
599 ppwrpolicyobjs->ext_limits[2].limit = hdr.d4_limit;
600 ppwrpolicyobjs->ext_limits[3].limit = hdr.d5_limit;
601 ppwrpolicyobjs->policy_idxs[4] = hdr.pwr_tgt_policy_idx;
602 ppwrpolicyobjs->policy_idxs[5] = hdr.pwr_tgt_floor_policy_idx;
603 ppwrpolicyobjs->policy_idxs[6] = hdr.sm_bus_policy_idx;
604
605 integral_control = (bool)BIOS_GET_FIELD(entry.flags1,
606 NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_INTEGRAL_CONTROL);
607
608 if (integral_control == 0x01) {
609 pwr_policy_data.pwrpolicy.integral.past_sample_count =
610 entry.past_length;
611 pwr_policy_data.pwrpolicy.integral.next_sample_count =
612 entry.next_length;
613 pwr_policy_data.pwrpolicy.integral.ratio_limit_max =
614 entry.ratio_max;
615 pwr_policy_data.pwrpolicy.integral.ratio_limit_min =
616 entry.ratio_min;
617 } else {
618 memset(&(pwr_policy_data.pwrpolicy.integral), 0x0,
619 sizeof(struct ctrl_pmgr_pwr_policy_info_integral));
620 }
621 pwr_policy_data.hw_threshold.threshold_idx = (u8)
622 BIOS_GET_FIELD(entry.param0,
623 NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_THRES_IDX);
624
625 pwr_policy_data.hw_threshold.b_use_low_threshold =
626 BIOS_GET_FIELD(entry.param0,
627 NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_LOW_THRESHOLD_USE);
628
629 if (pwr_policy_data.hw_threshold.b_use_low_threshold) {
630 pwr_policy_data.hw_threshold.low_threshold_idx = (u8)
631 BIOS_GET_FIELD(entry.param0,
632 NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_LOW_THRESHOLD_IDX);
633
634 pwr_policy_data.hw_threshold.low_threshold_value = (u16)
635 BIOS_GET_FIELD(entry.param1,
636 NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM1_HW_THRESHOLD_LOW_THRESHOLD_VAL);
637 }
638
639 pwr_policy_size = sizeof(struct pwr_policy_hw_threshold);
640
641 /* Initialize data for the parent class */
642 pwr_policy_data.boardobj.type =
643 CTRL_PMGR_PWR_POLICY_TYPE_HW_THRESHOLD;
644 pwr_policy_data.pwrpolicy.ch_idx = entry.ch_idx;
645 pwr_policy_data.pwrpolicy.limit_unit = (u8)
646 BIOS_GET_FIELD(entry.flags0,
647 NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_LIMIT_UNIT);
648 pwr_policy_data.pwrpolicy.filter_type =
649 (enum ctrl_pmgr_pwr_policy_filter_type)
650 BIOS_GET_FIELD(entry.flags1,
651 NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_FILTER_TYPE);
652
653 pwr_policy_data.pwrpolicy.limit_min = entry.limit_min;
654 pwr_policy_data.pwrpolicy.limit_rated = entry.limit_rated;
655 pwr_policy_data.pwrpolicy.limit_max = entry.limit_max;
656 pwr_policy_data.pwrpolicy.limit_batt = entry.limit_batt;
657
658 pwr_policy_data.pwrpolicy.sample_mult = (u8)entry.sample_mult;
659
660 /* Filled the entry.filterParam value in the filterParam */
661 pwr_policy_data.pwrpolicy.filter_param.block.block_size = 0;
662 pwr_policy_data.pwrpolicy.filter_param.moving_avg.window_size = 0;
663 pwr_policy_data.pwrpolicy.filter_param.iir.divisor = 0;
664
665 hw_threshold_policy_index |=
666 BIT(pwr_policy_data.hw_threshold.threshold_idx);
667
668 boardobj = construct_pwr_policy(g, &pwr_policy_data,
669 pwr_policy_size, pwr_policy_data.boardobj.type);
670
671 if (!boardobj) {
672 nvgpu_err(g,
673 "unable to create pwr policy for %d type %d",
674 index, pwr_policy_data.boardobj.type);
675 status = -EINVAL;
676 goto done;
677 }
678
679 status = boardobjgrp_objinsert(&ppwrpolicyobjs->pwr_policies.super,
680 boardobj, obj_index);
681
682 if (status) {
683 nvgpu_err(g,
684 "unable to insert pwr policy boardobj for %d",
685 index);
686 status = -EINVAL;
687 goto done;
688 }
689
690 ++obj_index;
691 }
692
693 if (g->hardcode_sw_threshold) {
694 status = _pwr_policy_construct_WAR_SW_Threshold_policy(g,
695 ppwrpolicyobjs,
696 &pwr_policy_data,
697 sizeof(struct pwr_policy_sw_threshold),
698 obj_index);
699 if (status) {
700 nvgpu_err(g, "unable to construct_WAR_policy");
701 status = -EINVAL;
702 goto done;
703 }
704 ++obj_index;
705 }
706
707done:
708 nvgpu_log_info(g, " done status %x", status);
709 return status;
710}
711
712int pmgr_policy_sw_setup(struct gk20a *g)
713{
714 int status;
715 struct boardobjgrp *pboardobjgrp = NULL;
716 struct pwr_policy *ppolicy;
717 struct pmgr_pwr_policy *ppwrpolicyobjs;
718 u8 indx = 0;
719
720 /* Construct the Super Class and override the Interfaces */
721 status = boardobjgrpconstruct_e32(g,
722 &g->pmgr_pmu.pmgr_policyobjs.pwr_policies);
723 if (status) {
724 nvgpu_err(g,
725 "error creating boardobjgrp for pmgr policy, status - 0x%x",
726 status);
727 goto done;
728 }
729
730 status = boardobjgrpconstruct_e32(g,
731 &g->pmgr_pmu.pmgr_policyobjs.pwr_policy_rels);
732 if (status) {
733 nvgpu_err(g,
734 "error creating boardobjgrp for pmgr policy rels, status - 0x%x",
735 status);
736 goto done;
737 }
738
739 status = boardobjgrpconstruct_e32(g,
740 &g->pmgr_pmu.pmgr_policyobjs.pwr_violations);
741 if (status) {
742 nvgpu_err(g,
743 "error creating boardobjgrp for pmgr violations, status - 0x%x",
744 status);
745 goto done;
746 }
747
748 memset(g->pmgr_pmu.pmgr_policyobjs.policy_idxs, CTRL_PMGR_PWR_POLICY_INDEX_INVALID,
749 sizeof(u8) * CTRL_PMGR_PWR_POLICY_IDX_NUM_INDEXES);
750
751 /* Initialize external power limit policy indexes to _INVALID/0xFF */
752 for (indx = 0; indx < PWR_POLICY_EXT_POWER_STATE_ID_COUNT; indx++) {
753 g->pmgr_pmu.pmgr_policyobjs.ext_limits[indx].policy_table_idx =
754 CTRL_PMGR_PWR_POLICY_INDEX_INVALID;
755 }
756
757 /* Initialize external power state to _D1 */
758 g->pmgr_pmu.pmgr_policyobjs.ext_power_state = 0xFFFFFFFF;
759
760 ppwrpolicyobjs = &(g->pmgr_pmu.pmgr_policyobjs);
761 pboardobjgrp = &(g->pmgr_pmu.pmgr_policyobjs.pwr_policies.super);
762
763 status = devinit_get_pwr_policy_table(g, ppwrpolicyobjs);
764 if (status) {
765 goto done;
766 }
767
768 g->pmgr_pmu.pmgr_policyobjs.b_enabled = true;
769
770 BOARDOBJGRP_FOR_EACH(pboardobjgrp, struct pwr_policy *, ppolicy, indx) {
771 PMGR_PWR_POLICY_INCREMENT_LIMIT_INPUT_COUNT(ppolicy);
772 }
773
774 g->pmgr_pmu.pmgr_policyobjs.global_ceiling.values[0] =
775 0xFF;
776
777 g->pmgr_pmu.pmgr_policyobjs.client_work_item.b_pending = false;
778
779done:
780 nvgpu_log_info(g, " done status %x", status);
781 return status;
782}
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-30 18:15:47 -0400