diff options
Diffstat (limited to 'include/os/linux/ioctl_clk_arb.c')
-rw-r--r-- | include/os/linux/ioctl_clk_arb.c | 574 |
1 files changed, 574 insertions, 0 deletions
diff --git a/include/os/linux/ioctl_clk_arb.c b/include/os/linux/ioctl_clk_arb.c new file mode 100644 index 0000000..477222d --- /dev/null +++ b/include/os/linux/ioctl_clk_arb.c | |||
@@ -0,0 +1,574 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This software is licensed under the terms of the GNU General Public | ||
5 | * License version 2, as published by the Free Software Foundation, and | ||
6 | * may be copied, distributed, and modified under those terms. | ||
7 | * | ||
8 | * This program is distributed in the hope that it will be useful, | ||
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
11 | * GNU General Public License for more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | |||
17 | #include <linux/cdev.h> | ||
18 | #include <linux/file.h> | ||
19 | #include <linux/anon_inodes.h> | ||
20 | #include <linux/uaccess.h> | ||
21 | #include <linux/poll.h> | ||
22 | #ifdef CONFIG_DEBUG_FS | ||
23 | #include <linux/debugfs.h> | ||
24 | #endif | ||
25 | #include <uapi/linux/nvgpu.h> | ||
26 | |||
27 | #include <nvgpu/bitops.h> | ||
28 | #include <nvgpu/lock.h> | ||
29 | #include <nvgpu/kmem.h> | ||
30 | #include <nvgpu/atomic.h> | ||
31 | #include <nvgpu/bug.h> | ||
32 | #include <nvgpu/kref.h> | ||
33 | #include <nvgpu/log.h> | ||
34 | #include <nvgpu/barrier.h> | ||
35 | #include <nvgpu/cond.h> | ||
36 | #include <nvgpu/list.h> | ||
37 | #include <nvgpu/clk_arb.h> | ||
38 | #include <nvgpu/gk20a.h> | ||
39 | |||
40 | #include "clk/clk.h" | ||
41 | #include "pstate/pstate.h" | ||
42 | #include "lpwr/lpwr.h" | ||
43 | #include "volt/volt.h" | ||
44 | |||
45 | #ifdef CONFIG_DEBUG_FS | ||
46 | #include "os_linux.h" | ||
47 | #endif | ||
48 | |||
49 | static int nvgpu_clk_arb_release_completion_dev(struct inode *inode, | ||
50 | struct file *filp) | ||
51 | { | ||
52 | struct nvgpu_clk_dev *dev = filp->private_data; | ||
53 | struct nvgpu_clk_session *session = dev->session; | ||
54 | |||
55 | |||
56 | clk_arb_dbg(session->g, " "); | ||
57 | |||
58 | /* This is done to account for the extra refcount taken in | ||
59 | * nvgpu_clk_arb_commit_request_fd without events support in iGPU | ||
60 | */ | ||
61 | if (!session->g->clk_arb->clk_arb_events_supported) { | ||
62 | nvgpu_ref_put(&dev->refcount, nvgpu_clk_arb_free_fd); | ||
63 | } | ||
64 | |||
65 | nvgpu_ref_put(&session->refcount, nvgpu_clk_arb_free_session); | ||
66 | nvgpu_ref_put(&dev->refcount, nvgpu_clk_arb_free_fd); | ||
67 | return 0; | ||
68 | } | ||
69 | |||
70 | static inline unsigned int nvgpu_convert_poll_mask(unsigned int nvgpu_poll_mask) | ||
71 | { | ||
72 | unsigned int poll_mask = 0; | ||
73 | |||
74 | if (nvgpu_poll_mask & NVGPU_POLLIN) | ||
75 | poll_mask |= POLLIN; | ||
76 | if (nvgpu_poll_mask & NVGPU_POLLPRI) | ||
77 | poll_mask |= POLLPRI; | ||
78 | if (nvgpu_poll_mask & NVGPU_POLLOUT) | ||
79 | poll_mask |= POLLOUT; | ||
80 | if (nvgpu_poll_mask & NVGPU_POLLRDNORM) | ||
81 | poll_mask |= POLLRDNORM; | ||
82 | if (nvgpu_poll_mask & NVGPU_POLLHUP) | ||
83 | poll_mask |= POLLHUP; | ||
84 | |||
85 | return poll_mask; | ||
86 | } | ||
87 | |||
88 | static unsigned int nvgpu_clk_arb_poll_dev(struct file *filp, poll_table *wait) | ||
89 | { | ||
90 | struct nvgpu_clk_dev *dev = filp->private_data; | ||
91 | |||
92 | clk_arb_dbg(dev->session->g, " "); | ||
93 | |||
94 | poll_wait(filp, &dev->readout_wq.wq, wait); | ||
95 | return nvgpu_convert_poll_mask(nvgpu_atomic_xchg(&dev->poll_mask, 0)); | ||
96 | } | ||
97 | |||
98 | void nvgpu_clk_arb_event_post_event(struct nvgpu_clk_dev *dev) | ||
99 | { | ||
100 | nvgpu_cond_broadcast_interruptible(&dev->readout_wq); | ||
101 | } | ||
102 | |||
103 | static int nvgpu_clk_arb_release_event_dev(struct inode *inode, | ||
104 | struct file *filp) | ||
105 | { | ||
106 | struct nvgpu_clk_dev *dev = filp->private_data; | ||
107 | struct nvgpu_clk_session *session = dev->session; | ||
108 | struct nvgpu_clk_arb *arb; | ||
109 | |||
110 | arb = session->g->clk_arb; | ||
111 | |||
112 | clk_arb_dbg(session->g, " "); | ||
113 | |||
114 | if (arb) { | ||
115 | nvgpu_spinlock_acquire(&arb->users_lock); | ||
116 | nvgpu_list_del(&dev->link); | ||
117 | nvgpu_spinlock_release(&arb->users_lock); | ||
118 | nvgpu_clk_notification_queue_free(arb->g, &dev->queue); | ||
119 | } | ||
120 | |||
121 | nvgpu_ref_put(&session->refcount, nvgpu_clk_arb_free_session); | ||
122 | nvgpu_ref_put(&dev->refcount, nvgpu_clk_arb_free_fd); | ||
123 | |||
124 | return 0; | ||
125 | } | ||
126 | |||
127 | static inline u32 nvgpu_convert_gpu_event(u32 nvgpu_event) | ||
128 | { | ||
129 | u32 nvgpu_gpu_event; | ||
130 | |||
131 | switch (nvgpu_event) { | ||
132 | case NVGPU_EVENT_VF_UPDATE: | ||
133 | nvgpu_gpu_event = NVGPU_GPU_EVENT_VF_UPDATE; | ||
134 | break; | ||
135 | case NVGPU_EVENT_ALARM_TARGET_VF_NOT_POSSIBLE: | ||
136 | nvgpu_gpu_event = NVGPU_GPU_EVENT_ALARM_TARGET_VF_NOT_POSSIBLE; | ||
137 | break; | ||
138 | case NVGPU_EVENT_ALARM_LOCAL_TARGET_VF_NOT_POSSIBLE: | ||
139 | nvgpu_gpu_event = NVGPU_GPU_EVENT_ALARM_LOCAL_TARGET_VF_NOT_POSSIBLE; | ||
140 | break; | ||
141 | case NVGPU_EVENT_ALARM_CLOCK_ARBITER_FAILED: | ||
142 | nvgpu_gpu_event = NVGPU_GPU_EVENT_ALARM_CLOCK_ARBITER_FAILED; | ||
143 | break; | ||
144 | case NVGPU_EVENT_ALARM_VF_TABLE_UPDATE_FAILED: | ||
145 | nvgpu_gpu_event = NVGPU_GPU_EVENT_ALARM_VF_TABLE_UPDATE_FAILED; | ||
146 | break; | ||
147 | case NVGPU_EVENT_ALARM_THERMAL_ABOVE_THRESHOLD: | ||
148 | nvgpu_gpu_event = NVGPU_GPU_EVENT_ALARM_THERMAL_ABOVE_THRESHOLD; | ||
149 | break; | ||
150 | case NVGPU_EVENT_ALARM_POWER_ABOVE_THRESHOLD: | ||
151 | nvgpu_gpu_event = NVGPU_GPU_EVENT_ALARM_POWER_ABOVE_THRESHOLD; | ||
152 | break; | ||
153 | case NVGPU_EVENT_ALARM_GPU_LOST: | ||
154 | nvgpu_gpu_event = NVGPU_GPU_EVENT_ALARM_GPU_LOST; | ||
155 | break; | ||
156 | default: | ||
157 | /* Control shouldn't come here */ | ||
158 | nvgpu_gpu_event = NVGPU_GPU_EVENT_ALARM_GPU_LOST + 1; | ||
159 | break; | ||
160 | } | ||
161 | return nvgpu_gpu_event; | ||
162 | } | ||
163 | |||
164 | static inline u32 __pending_event(struct nvgpu_clk_dev *dev, | ||
165 | struct nvgpu_gpu_event_info *info) { | ||
166 | |||
167 | u32 tail, head; | ||
168 | u32 events = 0; | ||
169 | struct nvgpu_clk_notification *p_notif; | ||
170 | |||
171 | tail = nvgpu_atomic_read(&dev->queue.tail); | ||
172 | head = nvgpu_atomic_read(&dev->queue.head); | ||
173 | |||
174 | head = (tail - head) < dev->queue.size ? head : tail - dev->queue.size; | ||
175 | |||
176 | if (_WRAPGTEQ(tail, head) && info) { | ||
177 | head++; | ||
178 | p_notif = &dev->queue.notifications[head % dev->queue.size]; | ||
179 | events |= nvgpu_convert_gpu_event(p_notif->notification); | ||
180 | info->event_id = ffs(events) - 1; | ||
181 | info->timestamp = p_notif->timestamp; | ||
182 | nvgpu_atomic_set(&dev->queue.head, head); | ||
183 | } | ||
184 | |||
185 | return events; | ||
186 | } | ||
187 | |||
188 | static ssize_t nvgpu_clk_arb_read_event_dev(struct file *filp, char __user *buf, | ||
189 | size_t size, loff_t *off) | ||
190 | { | ||
191 | struct nvgpu_clk_dev *dev = filp->private_data; | ||
192 | struct nvgpu_gpu_event_info info; | ||
193 | ssize_t err; | ||
194 | |||
195 | clk_arb_dbg(dev->session->g, | ||
196 | "filp=%p, buf=%p, size=%zu", filp, buf, size); | ||
197 | |||
198 | if ((size - *off) < sizeof(info)) | ||
199 | return 0; | ||
200 | |||
201 | memset(&info, 0, sizeof(info)); | ||
202 | /* Get the oldest event from the queue */ | ||
203 | while (!__pending_event(dev, &info)) { | ||
204 | if (filp->f_flags & O_NONBLOCK) | ||
205 | return -EAGAIN; | ||
206 | err = NVGPU_COND_WAIT_INTERRUPTIBLE(&dev->readout_wq, | ||
207 | __pending_event(dev, &info), 0); | ||
208 | if (err) | ||
209 | return err; | ||
210 | if (info.timestamp) | ||
211 | break; | ||
212 | } | ||
213 | |||
214 | if (copy_to_user(buf + *off, &info, sizeof(info))) | ||
215 | return -EFAULT; | ||
216 | |||
217 | return sizeof(info); | ||
218 | } | ||
219 | |||
220 | static int nvgpu_clk_arb_set_event_filter(struct nvgpu_clk_dev *dev, | ||
221 | struct nvgpu_gpu_set_event_filter_args *args) | ||
222 | { | ||
223 | struct gk20a *g = dev->session->g; | ||
224 | u32 mask; | ||
225 | |||
226 | nvgpu_log(g, gpu_dbg_fn, " "); | ||
227 | |||
228 | if (args->flags) | ||
229 | return -EINVAL; | ||
230 | |||
231 | if (args->size != 1) | ||
232 | return -EINVAL; | ||
233 | |||
234 | if (copy_from_user(&mask, (void __user *) args->buffer, | ||
235 | args->size * sizeof(u32))) | ||
236 | return -EFAULT; | ||
237 | |||
238 | /* update alarm mask */ | ||
239 | nvgpu_atomic_set(&dev->enabled_mask, mask); | ||
240 | |||
241 | return 0; | ||
242 | } | ||
243 | |||
244 | static long nvgpu_clk_arb_ioctl_event_dev(struct file *filp, unsigned int cmd, | ||
245 | unsigned long arg) | ||
246 | { | ||
247 | struct nvgpu_clk_dev *dev = filp->private_data; | ||
248 | struct gk20a *g = dev->session->g; | ||
249 | u8 buf[NVGPU_EVENT_IOCTL_MAX_ARG_SIZE]; | ||
250 | int err = 0; | ||
251 | |||
252 | nvgpu_log(g, gpu_dbg_fn, "nr=%d", _IOC_NR(cmd)); | ||
253 | |||
254 | if ((_IOC_TYPE(cmd) != NVGPU_EVENT_IOCTL_MAGIC) || (_IOC_NR(cmd) == 0) | ||
255 | || (_IOC_NR(cmd) > NVGPU_EVENT_IOCTL_LAST)) | ||
256 | return -EINVAL; | ||
257 | |||
258 | BUG_ON(_IOC_SIZE(cmd) > NVGPU_EVENT_IOCTL_MAX_ARG_SIZE); | ||
259 | |||
260 | memset(buf, 0, sizeof(buf)); | ||
261 | if (_IOC_DIR(cmd) & _IOC_WRITE) { | ||
262 | if (copy_from_user(buf, (void __user *) arg, _IOC_SIZE(cmd))) | ||
263 | return -EFAULT; | ||
264 | } | ||
265 | |||
266 | switch (cmd) { | ||
267 | case NVGPU_EVENT_IOCTL_SET_FILTER: | ||
268 | err = nvgpu_clk_arb_set_event_filter(dev, | ||
269 | (struct nvgpu_gpu_set_event_filter_args *)buf); | ||
270 | break; | ||
271 | default: | ||
272 | nvgpu_warn(g, "unrecognized event ioctl cmd: 0x%x", cmd); | ||
273 | err = -ENOTTY; | ||
274 | } | ||
275 | |||
276 | if ((err == 0) && (_IOC_DIR(cmd) & _IOC_READ)) | ||
277 | err = copy_to_user((void __user *) arg, buf, _IOC_SIZE(cmd)); | ||
278 | |||
279 | return err; | ||
280 | } | ||
281 | |||
282 | static const struct file_operations completion_dev_ops = { | ||
283 | .owner = THIS_MODULE, | ||
284 | .release = nvgpu_clk_arb_release_completion_dev, | ||
285 | .poll = nvgpu_clk_arb_poll_dev, | ||
286 | }; | ||
287 | |||
288 | static const struct file_operations event_dev_ops = { | ||
289 | .owner = THIS_MODULE, | ||
290 | .release = nvgpu_clk_arb_release_event_dev, | ||
291 | .poll = nvgpu_clk_arb_poll_dev, | ||
292 | .read = nvgpu_clk_arb_read_event_dev, | ||
293 | #ifdef CONFIG_COMPAT | ||
294 | .compat_ioctl = nvgpu_clk_arb_ioctl_event_dev, | ||
295 | #endif | ||
296 | .unlocked_ioctl = nvgpu_clk_arb_ioctl_event_dev, | ||
297 | }; | ||
298 | |||
299 | static int nvgpu_clk_arb_install_fd(struct gk20a *g, | ||
300 | struct nvgpu_clk_session *session, | ||
301 | const struct file_operations *fops, | ||
302 | struct nvgpu_clk_dev **_dev) | ||
303 | { | ||
304 | struct file *file; | ||
305 | int fd; | ||
306 | int err; | ||
307 | int status; | ||
308 | char name[64]; | ||
309 | struct nvgpu_clk_dev *dev; | ||
310 | |||
311 | clk_arb_dbg(g, " "); | ||
312 | |||
313 | dev = nvgpu_kzalloc(g, sizeof(*dev)); | ||
314 | if (!dev) | ||
315 | return -ENOMEM; | ||
316 | |||
317 | status = nvgpu_clk_notification_queue_alloc(g, &dev->queue, | ||
318 | DEFAULT_EVENT_NUMBER); | ||
319 | if (status < 0) { | ||
320 | err = status; | ||
321 | goto fail; | ||
322 | } | ||
323 | |||
324 | fd = get_unused_fd_flags(O_RDWR); | ||
325 | if (fd < 0) { | ||
326 | err = fd; | ||
327 | goto fail; | ||
328 | } | ||
329 | |||
330 | snprintf(name, sizeof(name), "%s-clk-fd%d", g->name, fd); | ||
331 | file = anon_inode_getfile(name, fops, dev, O_RDWR); | ||
332 | if (IS_ERR(file)) { | ||
333 | err = PTR_ERR(file); | ||
334 | goto fail_fd; | ||
335 | } | ||
336 | |||
337 | fd_install(fd, file); | ||
338 | |||
339 | nvgpu_cond_init(&dev->readout_wq); | ||
340 | |||
341 | nvgpu_atomic_set(&dev->poll_mask, 0); | ||
342 | |||
343 | dev->session = session; | ||
344 | nvgpu_ref_init(&dev->refcount); | ||
345 | |||
346 | nvgpu_ref_get(&session->refcount); | ||
347 | |||
348 | *_dev = dev; | ||
349 | |||
350 | return fd; | ||
351 | |||
352 | fail_fd: | ||
353 | put_unused_fd(fd); | ||
354 | fail: | ||
355 | nvgpu_kfree(g, dev); | ||
356 | |||
357 | return err; | ||
358 | } | ||
359 | |||
360 | int nvgpu_clk_arb_install_event_fd(struct gk20a *g, | ||
361 | struct nvgpu_clk_session *session, int *event_fd, u32 alarm_mask) | ||
362 | { | ||
363 | struct nvgpu_clk_arb *arb = g->clk_arb; | ||
364 | struct nvgpu_clk_dev *dev; | ||
365 | int fd; | ||
366 | |||
367 | clk_arb_dbg(g, " "); | ||
368 | |||
369 | fd = nvgpu_clk_arb_install_fd(g, session, &event_dev_ops, &dev); | ||
370 | if (fd < 0) | ||
371 | return fd; | ||
372 | |||
373 | /* TODO: alarm mask needs to be set to default value to prevent | ||
374 | * failures of legacy tests. This will be removed when sanity is | ||
375 | * updated | ||
376 | */ | ||
377 | if (alarm_mask) | ||
378 | nvgpu_atomic_set(&dev->enabled_mask, alarm_mask); | ||
379 | else | ||
380 | nvgpu_atomic_set(&dev->enabled_mask, EVENT(VF_UPDATE)); | ||
381 | |||
382 | dev->arb_queue_head = nvgpu_atomic_read(&arb->notification_queue.head); | ||
383 | |||
384 | nvgpu_spinlock_acquire(&arb->users_lock); | ||
385 | nvgpu_list_add_tail(&dev->link, &arb->users); | ||
386 | nvgpu_spinlock_release(&arb->users_lock); | ||
387 | |||
388 | *event_fd = fd; | ||
389 | |||
390 | return 0; | ||
391 | } | ||
392 | |||
393 | int nvgpu_clk_arb_install_request_fd(struct gk20a *g, | ||
394 | struct nvgpu_clk_session *session, int *request_fd) | ||
395 | { | ||
396 | struct nvgpu_clk_dev *dev; | ||
397 | int fd; | ||
398 | |||
399 | clk_arb_dbg(g, " "); | ||
400 | |||
401 | fd = nvgpu_clk_arb_install_fd(g, session, &completion_dev_ops, &dev); | ||
402 | if (fd < 0) | ||
403 | return fd; | ||
404 | |||
405 | *request_fd = fd; | ||
406 | |||
407 | return 0; | ||
408 | } | ||
409 | |||
410 | int nvgpu_clk_arb_commit_request_fd(struct gk20a *g, | ||
411 | struct nvgpu_clk_session *session, int request_fd) | ||
412 | { | ||
413 | struct nvgpu_clk_arb *arb = g->clk_arb; | ||
414 | struct nvgpu_clk_dev *dev; | ||
415 | struct fd fd; | ||
416 | int err = 0; | ||
417 | |||
418 | clk_arb_dbg(g, " "); | ||
419 | |||
420 | fd = fdget(request_fd); | ||
421 | if (!fd.file) | ||
422 | return -EINVAL; | ||
423 | |||
424 | if (fd.file->f_op != &completion_dev_ops) { | ||
425 | err = -EINVAL; | ||
426 | goto fdput_fd; | ||
427 | } | ||
428 | |||
429 | dev = (struct nvgpu_clk_dev *) fd.file->private_data; | ||
430 | |||
431 | if (!dev || dev->session != session) { | ||
432 | err = -EINVAL; | ||
433 | goto fdput_fd; | ||
434 | } | ||
435 | |||
436 | clk_arb_dbg(g, "requested target = %u\n", | ||
437 | (u32)dev->gpc2clk_target_mhz); | ||
438 | |||
439 | nvgpu_atomic_inc(&g->clk_arb_global_nr); | ||
440 | nvgpu_ref_get(&dev->refcount); | ||
441 | nvgpu_spinlock_acquire(&session->session_lock); | ||
442 | nvgpu_list_add(&dev->node, &session->targets); | ||
443 | nvgpu_spinlock_release(&session->session_lock); | ||
444 | nvgpu_clk_arb_worker_enqueue(g, &arb->update_arb_work_item); | ||
445 | |||
446 | fdput_fd: | ||
447 | fdput(fd); | ||
448 | return err; | ||
449 | } | ||
450 | |||
451 | int nvgpu_clk_arb_set_session_target_mhz(struct nvgpu_clk_session *session, | ||
452 | int request_fd, u32 api_domain, u16 target_mhz) | ||
453 | { | ||
454 | struct nvgpu_clk_dev *dev; | ||
455 | struct fd fd; | ||
456 | int err = 0; | ||
457 | |||
458 | clk_arb_dbg(session->g, | ||
459 | "domain=0x%08x target_mhz=%u", api_domain, target_mhz); | ||
460 | |||
461 | fd = fdget(request_fd); | ||
462 | if (!fd.file) | ||
463 | return -EINVAL; | ||
464 | |||
465 | if (fd.file->f_op != &completion_dev_ops) { | ||
466 | err = -EINVAL; | ||
467 | goto fdput_fd; | ||
468 | } | ||
469 | |||
470 | dev = fd.file->private_data; | ||
471 | if (!dev || dev->session != session) { | ||
472 | err = -EINVAL; | ||
473 | goto fdput_fd; | ||
474 | } | ||
475 | |||
476 | switch (api_domain) { | ||
477 | case NVGPU_CLK_DOMAIN_MCLK: | ||
478 | dev->mclk_target_mhz = target_mhz; | ||
479 | break; | ||
480 | |||
481 | case NVGPU_CLK_DOMAIN_GPCCLK: | ||
482 | dev->gpc2clk_target_mhz = target_mhz * 2ULL; | ||
483 | break; | ||
484 | |||
485 | default: | ||
486 | err = -EINVAL; | ||
487 | } | ||
488 | |||
489 | fdput_fd: | ||
490 | fdput(fd); | ||
491 | return err; | ||
492 | } | ||
493 | |||
494 | u32 nvgpu_clk_arb_get_arbiter_clk_domains(struct gk20a *g) | ||
495 | { | ||
496 | u32 clk_domains = g->ops.clk_arb.get_arbiter_clk_domains(g); | ||
497 | u32 api_domains = 0; | ||
498 | |||
499 | if (clk_domains & CTRL_CLK_DOMAIN_GPC2CLK) | ||
500 | api_domains |= BIT(NVGPU_GPU_CLK_DOMAIN_GPCCLK); | ||
501 | |||
502 | if (clk_domains & CTRL_CLK_DOMAIN_MCLK) | ||
503 | api_domains |= BIT(NVGPU_GPU_CLK_DOMAIN_MCLK); | ||
504 | |||
505 | return api_domains; | ||
506 | } | ||
507 | |||
508 | #ifdef CONFIG_DEBUG_FS | ||
509 | static int nvgpu_clk_arb_stats_show(struct seq_file *s, void *unused) | ||
510 | { | ||
511 | struct gk20a *g = s->private; | ||
512 | struct nvgpu_clk_arb *arb = g->clk_arb; | ||
513 | struct nvgpu_clk_arb_debug *debug; | ||
514 | |||
515 | u64 num; | ||
516 | s64 tmp, avg, std, max, min; | ||
517 | |||
518 | debug = NV_ACCESS_ONCE(arb->debug); | ||
519 | /* Make copy of structure and ensure no reordering */ | ||
520 | nvgpu_smp_rmb(); | ||
521 | if (!debug) | ||
522 | return -EINVAL; | ||
523 | |||
524 | std = debug->switch_std; | ||
525 | avg = debug->switch_avg; | ||
526 | max = debug->switch_max; | ||
527 | min = debug->switch_min; | ||
528 | num = debug->switch_num; | ||
529 | |||
530 | tmp = std; | ||
531 | do_div(tmp, num); | ||
532 | seq_printf(s, "Number of transitions: %lld\n", | ||
533 | num); | ||
534 | seq_printf(s, "max / min : %lld / %lld usec\n", | ||
535 | max, min); | ||
536 | seq_printf(s, "avg / std : %lld / %ld usec\n", | ||
537 | avg, int_sqrt(tmp)); | ||
538 | |||
539 | return 0; | ||
540 | } | ||
541 | |||
542 | static int nvgpu_clk_arb_stats_open(struct inode *inode, struct file *file) | ||
543 | { | ||
544 | return single_open(file, nvgpu_clk_arb_stats_show, inode->i_private); | ||
545 | } | ||
546 | |||
547 | static const struct file_operations nvgpu_clk_arb_stats_fops = { | ||
548 | .open = nvgpu_clk_arb_stats_open, | ||
549 | .read = seq_read, | ||
550 | .llseek = seq_lseek, | ||
551 | .release = single_release, | ||
552 | }; | ||
553 | |||
554 | |||
555 | int nvgpu_clk_arb_debugfs_init(struct gk20a *g) | ||
556 | { | ||
557 | struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); | ||
558 | struct dentry *gpu_root = l->debugfs; | ||
559 | struct dentry *d; | ||
560 | |||
561 | nvgpu_log(g, gpu_dbg_info, "g=%p", g); | ||
562 | |||
563 | d = debugfs_create_file( | ||
564 | "arb_stats", | ||
565 | S_IRUGO, | ||
566 | gpu_root, | ||
567 | g, | ||
568 | &nvgpu_clk_arb_stats_fops); | ||
569 | if (!d) | ||
570 | return -ENOMEM; | ||
571 | |||
572 | return 0; | ||
573 | } | ||
574 | #endif | ||