aboutsummaryrefslogtreecommitdiffstats
path: root/include/nvgpu/sec2if
diff options
context:
space:
mode:
Diffstat (limited to 'include/nvgpu/sec2if')
-rw-r--r--include/nvgpu/sec2if/sec2_cmd_if.h50
-rw-r--r--include/nvgpu/sec2if/sec2_if_acr.h96
-rw-r--r--include/nvgpu/sec2if/sec2_if_cmn.h73
-rw-r--r--include/nvgpu/sec2if/sec2_if_sec2.h75
4 files changed, 0 insertions, 294 deletions
diff --git a/include/nvgpu/sec2if/sec2_cmd_if.h b/include/nvgpu/sec2if/sec2_cmd_if.h
deleted file mode 100644
index 839743f..0000000
--- a/include/nvgpu/sec2if/sec2_cmd_if.h
+++ /dev/null
@@ -1,50 +0,0 @@
1/*
2 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef NVGPU_SEC2_CMD_IF_H
24#define NVGPU_SEC2_CMD_IF_H
25
26#include <nvgpu/sec2if/sec2_if_sec2.h>
27#include <nvgpu/sec2if/sec2_if_acr.h>
28
29struct nv_flcn_cmd_sec2 {
30 struct pmu_hdr hdr;
31 union {
32 union nv_sec2_acr_cmd acr;
33 } cmd;
34};
35
36struct nv_flcn_msg_sec2 {
37 struct pmu_hdr hdr;
38
39 union {
40 union nv_flcn_msg_sec2_init init;
41 union nv_sec2_acr_msg acr;
42 } msg;
43};
44
45#define NV_SEC2_UNIT_REWIND NV_FLCN_UNIT_ID_REWIND
46#define NV_SEC2_UNIT_INIT (0x01U)
47#define NV_SEC2_UNIT_ACR (0x07U)
48#define NV_SEC2_UNIT_END (0x0AU)
49
50#endif /* NVGPU_SEC2_CMD_IF_H */
diff --git a/include/nvgpu/sec2if/sec2_if_acr.h b/include/nvgpu/sec2if/sec2_if_acr.h
deleted file mode 100644
index 5b41958..0000000
--- a/include/nvgpu/sec2if/sec2_if_acr.h
+++ /dev/null
@@ -1,96 +0,0 @@
1/*
2 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef NVGPU_SEC2_IF_ACR_H
24#define NVGPU_SEC2_IF_ACR_H
25
26#include <nvgpu/types.h>
27
28/*
29 * ACR Command Types
30 * _BOOT_FALCON
31 * NVGPU sends a Falcon ID and LSB offset to SEC2 to boot
32 * the falcon in LS mode.
33 * SEC2 needs to hanlde the case since UCODE of falcons are
34 * stored in secured location on FB.
35 */
36#define NV_SEC2_ACR_CMD_ID_BOOTSTRAP_FALCON 0U
37
38/* nvgpu provides the Falcon ID to bootstrap */
39struct nv_sec2_acr_cmd_bootstrap_falcon {
40 /* Command must be first as this struct is the part of union */
41 u8 cmd_type;
42
43 /* Additional bootstrapping flags */
44 u32 flags;
45
46 /* ID to identify Falcon, ref LSF_FALCON_ID_<XYZ> */
47 u32 falcon_id;
48};
49
50#define NV_SEC2_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET 0U
51#define NV_SEC2_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_NO 1U
52#define NV_SEC2_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES 0U
53
54/* A union of all ACR Commands */
55union nv_sec2_acr_cmd {
56 /* Command type */
57 u8 cmd_type;
58
59 /* Bootstrap Falcon */
60 struct nv_sec2_acr_cmd_bootstrap_falcon bootstrap_falcon;
61};
62
63/* ACR Message Status */
64
65/* Returns the Bootstrapped falcon ID to RM */
66#define NV_SEC2_ACR_MSG_ID_BOOTSTRAP_FALCON 0U
67
68/* Returns the Error Status for Invalid Command */
69#define NV_SEC2_ACR_MSG_ID_INVALID_COMMAND 2U
70
71/*
72 * SEC2 notifies nvgpu about bootstrap status of falcon
73 */
74struct nv_sec2_acr_msg_bootstrap_falcon {
75 /* Message must be at start */
76 u8 msg_type;
77
78 /* Falcon Error Code returned by message */
79 u32 error_code;
80
81 /* Bootstrapped falcon ID by ACR */
82 u32 falcon_id;
83} ;
84
85/*
86 * A union of all ACR Messages.
87 */
88union nv_sec2_acr_msg {
89 /* Message type */
90 u8 msg_type;
91
92 /* Bootstrap details of falcon and status code */
93 struct nv_sec2_acr_msg_bootstrap_falcon msg_flcn;
94};
95
96#endif /* NVGPU_SEC2_IF_ACR_H */
diff --git a/include/nvgpu/sec2if/sec2_if_cmn.h b/include/nvgpu/sec2if/sec2_if_cmn.h
deleted file mode 100644
index a40f8f9..0000000
--- a/include/nvgpu/sec2if/sec2_if_cmn.h
+++ /dev/null
@@ -1,73 +0,0 @@
1/*
2 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef NVGPU_SEC2_IF_CMN_H
24#define NVGPU_SEC2_IF_CMN_H
25
26/*
27 * Define the maximum number of command sequences that can be in flight at
28 * any given time. This is dictated by the width of the sequence number
29 * id ('seqNumId') stored in each sequence packet (currently 8-bits).
30 */
31#define NV_SEC2_MAX_NUM_SEQUENCES 256U
32
33/*
34 * Compares an unit id against the values in the unit_id enumeration and
35 * verifies that the id is valid. It is expected that the id is specified
36 * as an unsigned integer.
37 */
38#define NV_SEC2_UNITID_IS_VALID(id) (((id) < NV_SEC2_UNIT_END))
39
40/*
41 * Defines the size of the surface/buffer that will be allocated to store
42 * debug spew from the SEC2 ucode application when falcon-trace is enabled.
43 */
44#define NV_SEC2_DEBUG_SURFACE_SIZE (32U*1024U)
45
46/*
47 * SEC2's frame-buffer interface block has several slots/indices which can
48 * be bound to support DMA to various surfaces in memory. This is an
49 * enumeration that gives name to each index based on type of memory-aperture
50 * the index is used to access.
51 *
52 * Pre-Turing, NV_SEC2_DMAIDX_PHYS_VID_FN0 == NV_SEC2_DMAIDX_GUEST_PHYS_VID_BOUND.
53 * From Turing, engine context is stored in GPA, requiring a separate aperture.
54 *
55 * Traditionally, video falcons have used the 6th index for ucode, and we will
56 * continue to use that to allow legacy ucode to work seamlessly.
57 *
58 * Note: DO NOT CHANGE THE VALUE OF NV_SEC2_DMAIDX_UCODE. That value is used by
59 * both the legacy SEC2 ucode, which assumes that it will use index 6, and by
60 * SEC2 RTOS. Changing it will break legacy SEC2 ucode, unless it is updated to
61 * reflect the new value.
62 */
63
64#define NV_SEC2_DMAIDX_GUEST_PHYS_VID_BOUND 0U
65#define NV_SEC2_DMAIDX_VIRT 1U
66#define NV_SEC2_DMAIDX_PHYS_VID_FN0 2U
67#define NV_SEC2_DMAIDX_PHYS_SYS_COH_FN0 3U
68#define NV_SEC2_DMAIDX_PHYS_SYS_NCOH_FN0 4U
69#define NV_SEC2_DMAIDX_GUEST_PHYS_SYS_COH_BOUND 5U
70#define NV_SEC2_DMAIDX_UCODE 6U
71#define NV_SEC2_DMAIDX_GUEST_PHYS_SYS_NCOH_BOUND 7U
72
73#endif /* NVGPU_SEC2_IF_CMN_H */
diff --git a/include/nvgpu/sec2if/sec2_if_sec2.h b/include/nvgpu/sec2if/sec2_if_sec2.h
deleted file mode 100644
index c895c41..0000000
--- a/include/nvgpu/sec2if/sec2_if_sec2.h
+++ /dev/null
@@ -1,75 +0,0 @@
1/*
2 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef NVGPU_SEC2_IF_SEC2_H
24#define NVGPU_SEC2_IF_SEC2_H
25
26/*
27 * SEC2 Command/Message Interfaces - SEC2 Management
28 */
29
30/*
31 * Defines the identifiers various high-level types of sequencer commands and
32 * messages.
33 * _SEC2_INIT - sec2_init_msg_sec2_init
34 */
35enum
36{
37 NV_SEC2_INIT_MSG_ID_SEC2_INIT = 0U,
38};
39
40/*
41 * Defines the logical queue IDs that must be used when submitting commands
42 * to or reading messages from SEC2. The identifiers must begin with zero and
43 * should increment sequentially. _CMDQ_LOG_ID__LAST must always be set to the
44 * last command queue identifier. _NUM must always be set to the last
45 * identifier plus one.
46 */
47#define SEC2_NV_CMDQ_LOG_ID 0U
48#define SEC2_NV_CMDQ_LOG_ID__LAST 0U
49#define SEC2_NV_MSGQ_LOG_ID 1U
50#define SEC2_QUEUE_NUM 2U
51
52struct sec2_init_msg_sec2_init {
53 u8 msg_type;
54 u8 num_queues;
55
56 u16 os_debug_entry_point;
57
58 struct
59 {
60 u32 queue_offset;
61 u16 queue_size;
62 u8 queue_phy_id;
63 u8 queue_log_id;
64 } q_info[SEC2_QUEUE_NUM];
65
66 u32 nv_managed_area_offset;
67 u16 nv_managed_area_size;
68};
69
70union nv_flcn_msg_sec2_init {
71 u8 msg_type;
72 struct sec2_init_msg_sec2_init sec2_init;
73};
74
75#endif /* NVGPU_SEC2_IF_SEC2_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-30 10:19:21 -0400