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1/*
2* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3*
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21*/
22#ifndef NVGPU_PMUIF_GPMUIFSEQ_H
23#define NVGPU_PMUIF_GPMUIFSEQ_H
24
25#include <nvgpu/flcnif_cmn.h>
26
27#define PMU_UNIT_SEQ (0x02)
28
29/*!
30* @file gpmuifseq.h
31* @brief PMU Command/Message Interfaces - Sequencer
32*/
33
34/*!
35* Defines the identifiers various high-level types of sequencer commands.
36*
37* _RUN_SCRIPT @ref NV_PMU_SEQ_CMD_RUN_SCRIPT
38*/
39enum {
40 NV_PMU_SEQ_CMD_ID_RUN_SCRIPT = 0,
41};
42
43struct nv_pmu_seq_cmd_run_script {
44 u8 cmd_type;
45 u8 pad[3];
46 struct pmu_allocation_v3 script_alloc;
47 struct pmu_allocation_v3 reg_alloc;
48};
49
50#define NV_PMU_SEQ_CMD_ALLOC_OFFSET 4
51
52#define NV_PMU_SEQ_MSG_ALLOC_OFFSET \
53 (NV_PMU_SEQ_CMD_ALLOC_OFFSET + NV_PMU_CMD_ALLOC_SIZE)
54
55struct nv_pmu_seq_cmd {
56 struct pmu_hdr hdr;
57 union {
58 u8 cmd_type;
59 struct nv_pmu_seq_cmd_run_script run_script;
60 };
61};
62
63enum {
64 NV_PMU_SEQ_MSG_ID_RUN_SCRIPT = 0,
65};
66
67struct nv_pmu_seq_msg_run_script {
68 u8 msg_type;
69 u8 error_code;
70 u16 error_pc;
71 u32 timeout_stat;
72};
73
74struct nv_pmu_seq_msg {
75 struct pmu_hdr hdr;
76 union {
77 u8 msg_type;
78 struct nv_pmu_seq_msg_run_script run_script;
79 };
80};
81
82#endif /* NVGPU_PMUIF_GPMUIFSEQ_H */