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-rw-r--r--include/nvgpu/pmuif/gpmuifclk.h573
1 files changed, 0 insertions, 573 deletions
diff --git a/include/nvgpu/pmuif/gpmuifclk.h b/include/nvgpu/pmuif/gpmuifclk.h
deleted file mode 100644
index 70a913b..0000000
--- a/include/nvgpu/pmuif/gpmuifclk.h
+++ /dev/null
@@ -1,573 +0,0 @@
1/*
2* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3*
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21*/
22
23#ifndef NVGPU_PMUIF_GPMUIFCLK_H
24#define NVGPU_PMUIF_GPMUIFCLK_H
25
26#include "ctrl/ctrlboardobj.h"
27#include "ctrl/ctrlvolt.h"
28#include "ctrl/ctrlperf.h"
29#include "ctrl/ctrlclk.h"
30#include "gpmuifboardobj.h"
31#include "gpmuifvolt.h"
32#include <nvgpu/flcnif_cmn.h>
33
34
35/*
36 * Try to get gpc2clk, mclk, sys2clk, xbar2clk work for Pascal
37 *
38 * mclk is same for both
39 * gpc2clk is 17 for Pascal and 13 for Volta, making it 17
40 * as volta uses gpcclk
41 * sys2clk is 20 in Pascal and 15 in Volta.
42 * Changing for Pascal would break nvdclk of Volta
43 * xbar2clk is 19 in Pascal and 14 in Volta
44 * Changing for Pascal would break pwrclk of Volta
45 */
46enum nv_pmu_clk_clkwhich {
47 clkwhich_gpcclk = 1,
48 clkwhich_xbarclk = 2,
49 clkwhich_sysclk = 3,
50 clkwhich_hubclk = 4,
51 clkwhich_mclk = 5,
52 clkwhich_hostclk = 6,
53 clkwhich_dispclk = 7,
54 clkwhich_xclk = 12,
55 clkwhich_gpc2clk = 17,
56 clkwhich_xbar2clk = 14,
57 clkwhich_sys2clk = 15,
58 clkwhich_hub2clk = 16,
59 clkwhich_pwrclk = 19,
60 clkwhich_nvdclk = 20,
61 clkwhich_pciegenclk = 26,
62};
63
64/*
65 * Enumeration of BOARDOBJGRP class IDs within OBJCLK. Used as "classId"
66 * argument for communications between Kernel and PMU via the various generic
67 * BOARDOBJGRP interfaces.
68 */
69#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_CLK_DOMAIN 0x00
70#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_CLK_PROG 0x01
71#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_VIN_DEVICE 0x02
72#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_FLL_DEVICE 0x03
73#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_CLK_VF_POINT 0x04
74#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_CLK_FREQ_CONTROLLER 0x05
75
76/*!
77* CLK_DOMAIN BOARDOBJGRP Header structure. Describes global state about the
78* CLK_DOMAIN feature.
79*/
80struct nv_pmu_clk_clk_domain_boardobjgrp_set_header {
81 struct nv_pmu_boardobjgrp_e32 super;
82 u32 vbios_domains;
83 struct ctrl_boardobjgrp_mask_e32 prog_domains_mask;
84 struct ctrl_boardobjgrp_mask_e32 master_domains_mask;
85 u16 cntr_sampling_periodms;
86 u8 version;
87 bool b_override_o_v_o_c;
88 bool b_debug_mode;
89 bool b_enforce_vf_monotonicity;
90 bool b_enforce_vf_smoothening;
91 u8 volt_rails_max;
92 struct ctrl_clk_clk_delta deltas;
93};
94
95struct nv_pmu_clk_clk_domain_boardobj_set {
96 struct nv_pmu_boardobj super;
97 enum nv_pmu_clk_clkwhich domain;
98 u32 api_domain;
99 u8 perf_domain_grp_idx;
100};
101
102struct nv_pmu_clk_clk_domain_3x_boardobj_set {
103 struct nv_pmu_clk_clk_domain_boardobj_set super;
104 bool b_noise_aware_capable;
105};
106
107struct nv_pmu_clk_clk_domain_3x_fixed_boardobj_set {
108 struct nv_pmu_clk_clk_domain_3x_boardobj_set super;
109 u16 freq_mhz;
110};
111
112struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set {
113 struct nv_pmu_clk_clk_domain_3x_boardobj_set super;
114 u8 clk_prog_idx_first;
115 u8 clk_prog_idx_last;
116 bool b_force_noise_unaware_ordering;
117 struct ctrl_clk_freq_delta factory_delta;
118 short freq_delta_min_mhz;
119 short freq_delta_max_mhz;
120 struct ctrl_clk_clk_delta deltas;
121};
122
123struct nv_pmu_clk_clk_domain_30_prog_boardobj_set {
124 struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set super;
125 u8 noise_unaware_ordering_index;
126 u8 noise_aware_ordering_index;
127};
128
129struct nv_pmu_clk_clk_domain_3x_master_boardobj_set {
130 u8 rsvd; /* Stubbing for RM_PMU_BOARDOBJ_INTERFACE */
131 u32 slave_idxs_mask;
132};
133
134struct nv_pmu_clk_clk_domain_30_master_boardobj_set {
135 struct nv_pmu_clk_clk_domain_30_prog_boardobj_set super;
136 struct nv_pmu_clk_clk_domain_3x_master_boardobj_set master;
137};
138
139struct nv_pmu_clk_clk_domain_3x_slave_boardobj_set {
140 u8 rsvd; /* Stubbing for RM_PMU_BOARDOBJ_INTERFACE */
141 u8 master_idx;
142};
143
144struct nv_pmu_clk_clk_domain_30_slave_boardobj_set {
145 struct nv_pmu_clk_clk_domain_30_prog_boardobj_set super;
146 struct nv_pmu_clk_clk_domain_3x_slave_boardobj_set slave;
147};
148
149struct nv_pmu_clk_clk_domain_35_prog_boardobj_set {
150 struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set super;
151 u8 pre_volt_ordering_index;
152 u8 post_volt_ordering_index;
153 u8 clk_pos;
154 u8 clk_vf_curve_count;
155};
156
157struct nv_pmu_clk_clk_domain_35_master_boardobj_set {
158 struct nv_pmu_clk_clk_domain_35_prog_boardobj_set super;
159 struct nv_pmu_clk_clk_domain_3x_master_boardobj_set master;
160 u32 master_slave_domains_grp_mask;
161};
162
163
164struct nv_pmu_clk_clk_domain_35_slave_boardobj_set {
165 struct nv_pmu_clk_clk_domain_35_prog_boardobj_set super;
166 struct nv_pmu_clk_clk_domain_3x_slave_boardobj_set slave;
167};
168
169union nv_pmu_clk_clk_domain_boardobj_set_union {
170 struct nv_pmu_boardobj board_obj;
171 struct nv_pmu_clk_clk_domain_boardobj_set super;
172 struct nv_pmu_clk_clk_domain_3x_boardobj_set v3x;
173 struct nv_pmu_clk_clk_domain_3x_fixed_boardobj_set v3x_fixed;
174 struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set v3x_prog;
175 struct nv_pmu_clk_clk_domain_30_prog_boardobj_set v30_prog;
176 struct nv_pmu_clk_clk_domain_30_master_boardobj_set v30_master;
177 struct nv_pmu_clk_clk_domain_30_slave_boardobj_set v30_slave;
178 struct nv_pmu_clk_clk_domain_35_prog_boardobj_set v35_prog;
179 struct nv_pmu_clk_clk_domain_35_master_boardobj_set v35_master;
180 struct nv_pmu_clk_clk_domain_35_slave_boardobj_set v35_slave;
181};
182
183NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_domain);
184
185struct nv_pmu_clk_clk_prog_boardobjgrp_set_header {
186 struct nv_pmu_boardobjgrp_e255 super;
187 u8 slave_entry_count;
188 u8 vf_entry_count;
189};
190
191struct nv_pmu_clk_clk_prog_boardobj_set {
192 struct nv_pmu_boardobj super;
193};
194
195struct nv_pmu_clk_clk_prog_1x_boardobj_set {
196 struct nv_pmu_clk_clk_prog_boardobj_set super;
197 u8 source;
198 u16 freq_max_mhz;
199 union ctrl_clk_clk_prog_1x_source_data source_data;
200};
201
202struct nv_pmu_clk_clk_prog_1x_master_boardobj_set {
203 struct nv_pmu_clk_clk_prog_1x_boardobj_set super;
204 u8 rsvd; /* Stubbing for RM_PMU_BOARDOBJ_INTERFACE */
205 bool b_o_c_o_v_enabled;
206 struct ctrl_clk_clk_prog_1x_master_vf_entry vf_entries[
207 CTRL_CLK_CLK_PROG_1X_MASTER_VF_ENTRY_MAX_ENTRIES];
208 struct ctrl_clk_clk_delta deltas;
209 union ctrl_clk_clk_prog_1x_master_source_data source_data;
210};
211
212struct nv_pmu_clk_clk_prog_1x_master_ratio_boardobj_set {
213 struct nv_pmu_clk_clk_prog_1x_master_boardobj_set super;
214 u8 rsvd; /* Stubbing for RM_PMU_BOARDOBJ_INTERFACE */
215 struct ctrl_clk_clk_prog_1x_master_ratio_slave_entry slave_entries[
216 CTRL_CLK_PROG_1X_MASTER_MAX_SLAVE_ENTRIES];
217};
218
219struct nv_pmu_clk_clk_prog_1x_master_table_boardobj_set {
220 struct nv_pmu_clk_clk_prog_1x_master_boardobj_set super;
221 u8 rsvd; /* Stubbing for RM_PMU_BOARDOBJ_INTERFACE */
222 struct ctrl_clk_clk_prog_1x_master_table_slave_entry
223 slave_entries[CTRL_CLK_PROG_1X_MASTER_MAX_SLAVE_ENTRIES];
224};
225
226union nv_pmu_clk_clk_prog_boardobj_set_union {
227 struct nv_pmu_boardobj board_obj;
228 struct nv_pmu_clk_clk_prog_boardobj_set super;
229 struct nv_pmu_clk_clk_prog_1x_boardobj_set v1x;
230 struct nv_pmu_clk_clk_prog_1x_master_boardobj_set v1x_master;
231 struct nv_pmu_clk_clk_prog_1x_master_ratio_boardobj_set v1x_master_ratio;
232 struct nv_pmu_clk_clk_prog_1x_master_table_boardobj_set v1x_master_table;
233};
234
235NV_PMU_BOARDOBJ_GRP_SET_MAKE_E255(clk, clk_prog);
236
237struct nv_pmu_clk_lut_device_desc {
238 u8 vselect_mode;
239 u16 hysteresis_threshold;
240};
241
242struct nv_pmu_clk_regime_desc {
243 u8 regime_id;
244 u8 target_regime_id_override;
245 u16 fixed_freq_regime_limit_mhz;
246};
247
248struct nv_pmu_clk_clk_fll_device_boardobjgrp_set_header {
249 struct nv_pmu_boardobjgrp_e32 super;
250 struct ctrl_boardobjgrp_mask_e32 lut_prog_master_mask;
251 u32 lut_step_size_uv;
252 u32 lut_min_voltage_uv;
253 u8 lut_num_entries;
254 u16 max_min_freq_mhz;
255};
256
257struct nv_pmu_clk_clk_fll_device_boardobj_set {
258 struct nv_pmu_boardobj super;
259 u8 id;
260 u8 mdiv;
261 u8 vin_idx_logic;
262 u8 vin_idx_sram;
263 u8 rail_idx_for_lut;
264 u16 input_freq_mhz;
265 u32 clk_domain;
266 struct nv_pmu_clk_lut_device_desc lut_device;
267 struct nv_pmu_clk_regime_desc regime_desc;
268 u8 min_freq_vfe_idx;
269 u8 freq_ctrl_idx;
270 bool b_skip_pldiv_below_dvco_min;
271 bool b_dvco_1x;
272 struct ctrl_boardobjgrp_mask_e32 lut_prog_broadcast_slave_mask;
273};
274
275union nv_pmu_clk_clk_fll_device_boardobj_set_union {
276 struct nv_pmu_boardobj board_obj;
277 struct nv_pmu_clk_clk_fll_device_boardobj_set super;
278};
279
280NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_fll_device);
281
282struct nv_pmu_clk_clk_vin_device_boardobjgrp_set_header {
283 struct nv_pmu_boardobjgrp_e32 super;
284 bool b_vin_is_disable_allowed;
285};
286
287struct nv_pmu_clk_clk_vin_device_boardobj_set {
288 struct nv_pmu_boardobj super;
289 u8 id;
290 u8 volt_domain;
291 u32 flls_shared_mask;
292};
293
294struct nv_pmu_clk_clk_vin_device_v10_boardobj_set {
295 struct nv_pmu_clk_clk_vin_device_boardobj_set super;
296 struct ctrl_clk_vin_device_info_data_v10 data;
297};
298
299struct nv_pmu_clk_clk_vin_device_v20_boardobj_set {
300 struct nv_pmu_clk_clk_vin_device_boardobj_set super;
301 struct ctrl_clk_vin_device_info_data_v20 data;
302};
303
304union nv_pmu_clk_clk_vin_device_boardobj_set_union {
305 struct nv_pmu_boardobj board_obj;
306 struct nv_pmu_clk_clk_vin_device_boardobj_set super;
307 struct nv_pmu_clk_clk_vin_device_v10_boardobj_set v10;
308 struct nv_pmu_clk_clk_vin_device_v20_boardobj_set v20;
309};
310
311NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_vin_device);
312
313struct nv_pmu_clk_clk_vf_point_boardobjgrp_set_header {
314 struct nv_pmu_boardobjgrp_e255 super;
315};
316
317struct nv_pmu_clk_clk_vf_point_boardobj_set {
318 struct nv_pmu_boardobj super;
319 u8 vfe_equ_idx;
320 u8 volt_rail_idx;
321};
322
323struct nv_pmu_clk_clk_vf_point_freq_boardobj_set {
324 struct nv_pmu_clk_clk_vf_point_boardobj_set super;
325 u16 freq_mhz;
326 int volt_delta_uv;
327};
328
329struct nv_pmu_clk_clk_vf_point_volt_boardobj_set {
330 struct nv_pmu_clk_clk_vf_point_boardobj_set super;
331 u32 source_voltage_uv;
332 struct ctrl_clk_freq_delta freq_delta;
333};
334
335union nv_pmu_clk_clk_vf_point_boardobj_set_union {
336 struct nv_pmu_boardobj board_obj;
337 struct nv_pmu_clk_clk_vf_point_boardobj_set super;
338 struct nv_pmu_clk_clk_vf_point_freq_boardobj_set freq;
339 struct nv_pmu_clk_clk_vf_point_volt_boardobj_set volt;
340};
341
342NV_PMU_BOARDOBJ_GRP_SET_MAKE_E255(clk, clk_vf_point);
343
344struct nv_pmu_clk_clk_vf_point_boardobjgrp_get_status_header {
345 struct nv_pmu_boardobjgrp_e255 super;
346 u32 vf_points_cahce_counter;
347};
348
349struct nv_pmu_clk_clk_vf_point_boardobj_get_status {
350 struct nv_pmu_boardobj super;
351 struct ctrl_clk_vf_pair pair;
352 u8 dummy[38];
353};
354
355struct nv_pmu_clk_clk_vf_point_volt_boardobj_get_status {
356 struct nv_pmu_clk_clk_vf_point_boardobj_get_status super;
357 u16 vf_gain_value;
358};
359
360union nv_pmu_clk_clk_vf_point_boardobj_get_status_union {
361 struct nv_pmu_boardobj board_obj;
362 struct nv_pmu_clk_clk_vf_point_boardobj_get_status super;
363 struct nv_pmu_clk_clk_vf_point_volt_boardobj_get_status volt;
364};
365
366NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E255(clk, clk_vf_point);
367
368#define NV_PMU_VF_INJECT_MAX_CLOCK_DOMAINS (12)
369
370struct nv_pmu_clk_clk_domain_list {
371 u8 num_domains;
372 struct ctrl_clk_clk_domain_list_item clk_domains[
373 NV_PMU_VF_INJECT_MAX_CLOCK_DOMAINS];
374};
375
376struct nv_pmu_clk_clk_domain_list_v1 {
377 u8 num_domains;
378 struct ctrl_clk_clk_domain_list_item_v1 clk_domains[
379 NV_PMU_VF_INJECT_MAX_CLOCK_DOMAINS];
380};
381
382struct nv_pmu_clk_vf_change_inject {
383 u8 flags;
384 struct nv_pmu_clk_clk_domain_list clk_list;
385 struct nv_pmu_volt_volt_rail_list volt_list;
386};
387
388struct nv_pmu_clk_vf_change_inject_v1 {
389 u8 flags;
390 struct nv_pmu_clk_clk_domain_list_v1 clk_list;
391 struct nv_pmu_volt_volt_rail_list_v1 volt_list;
392};
393
394#define NV_NV_PMU_CLK_LOAD_FEATURE_VIN (0x00000002)
395#define NV_NV_PMU_CLK_LOAD_ACTION_MASK_VIN_HW_CAL_PROGRAM_YES (0x00000001)
396
397struct nv_pmu_clk_load_payload_freq_controllers {
398 struct ctrl_boardobjgrp_mask_e32 load_mask;
399};
400
401struct nv_pmu_clk_load {
402 u8 feature;
403 u32 action_mask;
404 union {
405 struct nv_pmu_clk_load_payload_freq_controllers freq_controllers;
406 } payload;
407};
408
409struct nv_pmu_clk_freq_effective_avg {
410 u32 clkDomainMask;
411 u32 freqkHz[CTRL_BOARDOBJ_MAX_BOARD_OBJECTS];
412};
413
414/* CLK_FREQ_CONTROLLER */
415#define NV_NV_PMU_CLK_LOAD_FEATURE_FREQ_CONTROLLER (0x00000003)
416
417#define NV_NV_PMU_CLK_LOAD_ACTION_MASK_FREQ_CONTROLLER_CALLBACK_NO (0x00000000)
418#define NV_NV_PMU_CLK_LOAD_ACTION_MASK_FREQ_CONTROLLER_CALLBACK_YES (0x00000002)
419
420struct nv_pmu_clk_clk_freq_controller_boardobjgrp_set_header {
421 struct nv_pmu_boardobjgrp_e32 super;
422 u32 sampling_period_ms;
423 u8 volt_policy_idx;
424};
425
426struct nv_pmu_clk_clk_freq_controller_boardobj_set {
427 struct nv_pmu_boardobj super;
428 u8 controller_id;
429 u8 parts_freq_mode;
430 bool bdisable;
431 u32 clk_domain;
432 s16 freq_cap_noise_unaware_vmin_above;
433 s16 freq_cap_noise_unaware_vmin_below;
434 s16 freq_hyst_pos_mhz;
435 s16 freq_hyst_neg_mhz;
436};
437
438struct nv_pmu_clk_clk_freq_controller_pi_boardobj_set {
439 struct nv_pmu_clk_clk_freq_controller_boardobj_set super;
440 s32 prop_gain;
441 s32 integ_gain;
442 s32 integ_decay;
443 s32 volt_delta_min;
444 s32 volt_delta_max;
445 u8 slowdown_pct_min;
446 bool bpoison;
447};
448
449union nv_pmu_clk_clk_freq_controller_boardobj_set_union {
450 struct nv_pmu_boardobj board_obj;
451 struct nv_pmu_clk_clk_freq_controller_boardobj_set super;
452 struct nv_pmu_clk_clk_freq_controller_pi_boardobj_set pi;
453};
454
455NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_freq_controller);
456
457#define NV_NV_PMU_CLK_LOAD_FEATURE_FREQ_EFFECTIVE_AVG (0x00000004)
458#define NV_NV_PMU_CLK_LOAD_ACTION_MASK_FREQ_EFFECTIVE_AVG_CALLBACK_NO (0x00000000)
459#define NV_NV_PMU_CLK_LOAD_ACTION_MASK_FREQ_EFFECTIVE_AVG_CALLBACK_YES (0x00000004)
460
461/* CLK CMD ID definitions. */
462#define NV_PMU_CLK_CMD_ID_BOARDOBJ_GRP_SET (0x00000001)
463#define NV_PMU_CLK_CMD_ID_RPC (0x00000000)
464#define NV_PMU_CLK_CMD_ID_BOARDOBJ_GRP_GET_STATUS (0x00000002)
465
466#define NV_PMU_CLK_RPC_ID_LOAD (0x00000001)
467#define NV_PMU_CLK_RPC_ID_CLK_VF_CHANGE_INJECT (0x00000000)
468#define NV_PMU_CLK_RPC_ID_CLK_FREQ_EFF_AVG (0x00000002)
469
470struct nv_pmu_clk_cmd_rpc {
471 u8 cmd_type;
472 u8 pad[3];
473 struct nv_pmu_allocation request;
474};
475
476struct nv_pmu_clk_cmd_generic {
477 u8 cmd_type;
478 bool b_perf_daemon_cmd;
479 u8 pad[2];
480};
481
482#define NV_PMU_CLK_CMD_RPC_ALLOC_OFFSET \
483 (offsetof(struct nv_pmu_clk_cmd_rpc, request))
484
485struct nv_pmu_clk_cmd {
486 union {
487 u8 cmd_type;
488 struct nv_pmu_boardobj_cmd_grp grp_set;
489 struct nv_pmu_clk_cmd_generic generic;
490 struct nv_pmu_clk_cmd_rpc rpc;
491 struct nv_pmu_boardobj_cmd_grp grp_get_status;
492 };
493};
494
495struct nv_pmu_clk_rpc {
496 u8 function;
497 bool b_supported;
498 bool b_success;
499 flcn_status flcn_status;
500 union {
501 struct nv_pmu_clk_vf_change_inject clk_vf_change_inject;
502 struct nv_pmu_clk_vf_change_inject_v1 clk_vf_change_inject_v1;
503 struct nv_pmu_clk_load clk_load;
504 struct nv_pmu_clk_freq_effective_avg clk_freq_effective_avg;
505 } params;
506};
507
508/* CLK MSG ID definitions */
509#define NV_PMU_CLK_MSG_ID_BOARDOBJ_GRP_SET (0x00000001)
510#define NV_PMU_CLK_MSG_ID_RPC (0x00000000)
511#define NV_PMU_CLK_MSG_ID_BOARDOBJ_GRP_GET_STATUS (0x00000002)
512
513struct nv_pmu_clk_msg_rpc {
514 u8 msg_type;
515 u8 rsvd[3];
516 struct nv_pmu_allocation response;
517};
518
519#define NV_PMU_CLK_MSG_RPC_ALLOC_OFFSET \
520 offsetof(struct nv_pmu_clk_msg_rpc, response)
521
522struct nv_pmu_clk_msg {
523 union {
524 u8 msg_type;
525 struct nv_pmu_boardobj_msg_grp grp_set;
526 struct nv_pmu_clk_msg_rpc rpc;
527 struct nv_pmu_boardobj_msg_grp grp_get_status;
528 };
529};
530
531struct nv_pmu_clk_clk_vin_device_boardobjgrp_get_status_header {
532 struct nv_pmu_boardobjgrp_e32 super;
533};
534
535struct nv_pmu_clk_clk_vin_device_boardobj_get_status {
536 struct nv_pmu_boardobj_query super;
537 u32 actual_voltage_uv;
538 u32 corrected_voltage_uv;
539 u8 sampled_code;
540 u8 override_code;
541};
542
543union nv_pmu_clk_clk_vin_device_boardobj_get_status_union {
544 struct nv_pmu_boardobj_query board_obj;
545 struct nv_pmu_clk_clk_vin_device_boardobj_get_status super;
546};
547
548NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(clk, clk_vin_device);
549
550struct nv_pmu_clk_lut_vf_entry {
551 u32 entry;
552};
553
554struct nv_pmu_clk_clk_fll_device_boardobjgrp_get_status_header {
555 struct nv_pmu_boardobjgrp_e32 super;
556};
557
558struct nv_pmu_clk_clk_fll_device_boardobj_get_status {
559 struct nv_pmu_boardobj_query super;
560 u8 current_regime_id;
561 bool b_dvco_min_reached;
562 u16 min_freq_mhz;
563 struct nv_pmu_clk_lut_vf_entry lut_vf_curve[NV_UNSIGNED_ROUNDED_DIV(CTRL_CLK_LUT_NUM_ENTRIES_MAX, 2)];
564};
565
566union nv_pmu_clk_clk_fll_device_boardobj_get_status_union {
567 struct nv_pmu_boardobj_query board_obj;
568 struct nv_pmu_clk_clk_fll_device_boardobj_get_status super;
569};
570
571NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(clk, clk_fll_device);
572
573#endif /*NVGPU_PMUIF_GPMUIFCLK_H*/
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-30 16:24:19 -0400