diff options
Diffstat (limited to 'include/nvgpu/pmuif/gpmuif_pmu.h')
-rw-r--r-- | include/nvgpu/pmuif/gpmuif_pmu.h | 193 |
1 files changed, 0 insertions, 193 deletions
diff --git a/include/nvgpu/pmuif/gpmuif_pmu.h b/include/nvgpu/pmuif/gpmuif_pmu.h deleted file mode 100644 index 0528bd6..0000000 --- a/include/nvgpu/pmuif/gpmuif_pmu.h +++ /dev/null | |||
@@ -1,193 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | #ifndef NVGPU_PMUIF_GPMUIF_PMU_H | ||
23 | #define NVGPU_PMUIF_GPMUIF_PMU_H | ||
24 | |||
25 | #include <nvgpu/flcnif_cmn.h> | ||
26 | #include "gpmuif_cmn.h" | ||
27 | |||
28 | /* Make sure size of this structure is a multiple of 4 bytes */ | ||
29 | struct pmu_cmdline_args_v3 { | ||
30 | u32 reserved; | ||
31 | u32 cpu_freq_hz; | ||
32 | u32 falc_trace_size; | ||
33 | u32 falc_trace_dma_base; | ||
34 | u32 falc_trace_dma_idx; | ||
35 | u8 secure_mode; | ||
36 | u8 raise_priv_sec; | ||
37 | struct pmu_mem_v1 gc6_ctx; | ||
38 | }; | ||
39 | |||
40 | struct pmu_cmdline_args_v4 { | ||
41 | u32 reserved; | ||
42 | u32 cpu_freq_hz; | ||
43 | u32 falc_trace_size; | ||
44 | struct falc_dma_addr dma_addr; | ||
45 | u32 falc_trace_dma_idx; | ||
46 | u8 secure_mode; | ||
47 | u8 raise_priv_sec; | ||
48 | struct pmu_mem_desc_v0 gc6_ctx; | ||
49 | u8 pad; | ||
50 | }; | ||
51 | |||
52 | struct pmu_cmdline_args_v5 { | ||
53 | u32 cpu_freq_hz; | ||
54 | struct flcn_mem_desc_v0 trace_buf; | ||
55 | u8 secure_mode; | ||
56 | u8 raise_priv_sec; | ||
57 | struct flcn_mem_desc_v0 gc6_ctx; | ||
58 | struct flcn_mem_desc_v0 init_data_dma_info; | ||
59 | u32 dummy; | ||
60 | }; | ||
61 | |||
62 | struct pmu_cmdline_args_v6 { | ||
63 | u32 cpu_freq_hz; | ||
64 | struct flcn_mem_desc_v0 trace_buf; | ||
65 | u8 secure_mode; | ||
66 | u8 raise_priv_sec; | ||
67 | struct flcn_mem_desc_v0 gc6_ctx; | ||
68 | struct flcn_mem_desc_v0 gc6_bsod_ctx; | ||
69 | struct flcn_mem_desc_v0 super_surface; | ||
70 | u32 flags; | ||
71 | }; | ||
72 | |||
73 | /* GPU ID */ | ||
74 | #define PMU_SHA1_GID_SIGNATURE 0xA7C66AD2 | ||
75 | #define PMU_SHA1_GID_SIGNATURE_SIZE 4 | ||
76 | |||
77 | #define PMU_SHA1_GID_SIZE 16 | ||
78 | |||
79 | struct pmu_sha1_gid { | ||
80 | bool valid; | ||
81 | u8 gid[PMU_SHA1_GID_SIZE]; | ||
82 | }; | ||
83 | |||
84 | struct pmu_sha1_gid_data { | ||
85 | u8 signature[PMU_SHA1_GID_SIGNATURE_SIZE]; | ||
86 | u8 gid[PMU_SHA1_GID_SIZE]; | ||
87 | }; | ||
88 | |||
89 | /* PMU INIT MSG */ | ||
90 | enum { | ||
91 | PMU_INIT_MSG_TYPE_PMU_INIT = 0, | ||
92 | }; | ||
93 | |||
94 | struct pmu_init_msg_pmu_v1 { | ||
95 | u8 msg_type; | ||
96 | u8 pad; | ||
97 | u16 os_debug_entry_point; | ||
98 | |||
99 | struct { | ||
100 | u16 size; | ||
101 | u16 offset; | ||
102 | u8 index; | ||
103 | u8 pad; | ||
104 | } queue_info[PMU_QUEUE_COUNT]; | ||
105 | |||
106 | u16 sw_managed_area_offset; | ||
107 | u16 sw_managed_area_size; | ||
108 | }; | ||
109 | |||
110 | #define PMU_QUEUE_COUNT_FOR_V5 4 | ||
111 | #define PMU_QUEUE_COUNT_FOR_V4 5 | ||
112 | #define PMU_QUEUE_COUNT_FOR_V3 3 | ||
113 | #define PMU_QUEUE_HPQ_IDX_FOR_V3 0 | ||
114 | #define PMU_QUEUE_LPQ_IDX_FOR_V3 1 | ||
115 | #define PMU_QUEUE_MSG_IDX_FOR_V3 2 | ||
116 | #define PMU_QUEUE_MSG_IDX_FOR_V5 3 | ||
117 | struct pmu_init_msg_pmu_v3 { | ||
118 | u8 msg_type; | ||
119 | u8 queue_index[PMU_QUEUE_COUNT_FOR_V3]; | ||
120 | u16 queue_size[PMU_QUEUE_COUNT_FOR_V3]; | ||
121 | u16 queue_offset; | ||
122 | |||
123 | u16 sw_managed_area_offset; | ||
124 | u16 sw_managed_area_size; | ||
125 | |||
126 | u16 os_debug_entry_point; | ||
127 | |||
128 | u8 dummy[18]; | ||
129 | }; | ||
130 | |||
131 | struct pmu_init_msg_pmu_v4 { | ||
132 | u8 msg_type; | ||
133 | u8 queue_index[PMU_QUEUE_COUNT_FOR_V4]; | ||
134 | u16 queue_size[PMU_QUEUE_COUNT_FOR_V4]; | ||
135 | u16 queue_offset; | ||
136 | |||
137 | u16 sw_managed_area_offset; | ||
138 | u16 sw_managed_area_size; | ||
139 | |||
140 | u16 os_debug_entry_point; | ||
141 | |||
142 | u8 dummy[18]; | ||
143 | }; | ||
144 | |||
145 | struct pmu_init_msg_pmu_v5 { | ||
146 | u8 msg_type; | ||
147 | u8 flcn_status; | ||
148 | u8 queue_index[PMU_QUEUE_COUNT_FOR_V5]; | ||
149 | u16 queue_size[PMU_QUEUE_COUNT_FOR_V5]; | ||
150 | u16 queue_offset; | ||
151 | |||
152 | u16 sw_managed_area_offset; | ||
153 | u16 sw_managed_area_size; | ||
154 | |||
155 | u16 os_debug_entry_point; | ||
156 | |||
157 | u8 dummy[18]; | ||
158 | u8 pad; | ||
159 | }; | ||
160 | |||
161 | union pmu_init_msg_pmu { | ||
162 | struct pmu_init_msg_pmu_v1 v1; | ||
163 | struct pmu_init_msg_pmu_v3 v3; | ||
164 | struct pmu_init_msg_pmu_v4 v4; | ||
165 | struct pmu_init_msg_pmu_v5 v5; | ||
166 | }; | ||
167 | |||
168 | struct pmu_init_msg { | ||
169 | union { | ||
170 | u8 msg_type; | ||
171 | struct pmu_init_msg_pmu_v1 pmu_init_v1; | ||
172 | struct pmu_init_msg_pmu_v3 pmu_init_v3; | ||
173 | struct pmu_init_msg_pmu_v4 pmu_init_v4; | ||
174 | struct pmu_init_msg_pmu_v5 pmu_init_v5; | ||
175 | }; | ||
176 | }; | ||
177 | |||
178 | /* robust channel (RC) messages */ | ||
179 | enum { | ||
180 | PMU_RC_MSG_TYPE_UNHANDLED_CMD = 0, | ||
181 | }; | ||
182 | |||
183 | struct pmu_rc_msg_unhandled_cmd { | ||
184 | u8 msg_type; | ||
185 | u8 unit_id; | ||
186 | }; | ||
187 | |||
188 | struct pmu_rc_msg { | ||
189 | u8 msg_type; | ||
190 | struct pmu_rc_msg_unhandled_cmd unhandled_cmd; | ||
191 | }; | ||
192 | |||
193 | #endif /* NVGPU_PMUIF_GPMUIF_PMU_H*/ | ||