1 files changed, 0 insertions, 110 deletions
diff --git a/include/nvgpu/pmuif/gpmuif_pg_rppg.h b/include/nvgpu/pmuif/gpmuif_pg_rppg.h
deleted file mode 100644
index 05445f6..0000000
--- a/include/nvgpu/pmuif/gpmuif_pg_rppg.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-#ifndef NVGPU_PMUIF_GPMUIF_PG_RPPG_H
-#define NVGPU_PMUIF_GPMUIF_PG_RPPG_H
-#define NV_PMU_RPPG_CTRL_ID_GR    (0x0000)
-#define NV_PMU_RPPG_CTRL_ID_MS    (0x0001)
-#define NV_PMU_RPPG_CTRL_ID_DI    (0x0002)
-#define NV_PMU_RPPG_CTRL_ID_MAX   (0x0003)
-#define NV_PMU_RPPG_CTRL_MASK_ENABLE_ALL  (BIT(NV_PMU_RPPG_CTRL_ID_GR) |\
-        BIT(NV_PMU_RPPG_CTRL_ID_MS) |\
-        BIT(NV_PMU_RPPG_CTRL_ID_DI))
-#define NV_PMU_RPPG_CTRL_MASK_DISABLE_ALL 0
-enum {
-        NV_PMU_RPPG_DOMAIN_ID_GFX = 0x0,
-        NV_PMU_RPPG_DOMAIN_ID_NON_GFX,
-};
-struct nv_pmu_rppg_ctrl_stats {
-        u32 entry_count;
-        u32 exit_count;
-};
-struct nv_pmu_rppg_cmd_common {
-        u8 cmd_type;
-        u8 cmd_id;
-};
-struct nv_pmu_rppg_cmd_init {
-        u8 cmd_type;
-        u8 cmd_id;
-};
-struct nv_pmu_rppg_cmd_init_ctrl {
-        u8 cmd_type;
-        u8 cmd_id;
-        u8 ctrl_id;
-        u8 domain_id;
-};
-struct nv_pmu_rppg_cmd_stats_reset {
-        u8 cmd_type;
-        u8 cmd_id;
-        u8 ctrl_id;
-};
-struct nv_pmu_rppg_cmd {
-        union {
-                u8 cmd_type;
-                struct nv_pmu_rppg_cmd_common cmn;
-                struct nv_pmu_rppg_cmd_init init;
-                struct nv_pmu_rppg_cmd_init_ctrl init_ctrl;
-                struct nv_pmu_rppg_cmd_stats_reset stats_reset;
-        };
-};
-enum {
-        NV_PMU_RPPG_CMD_ID_INIT = 0x0,
-        NV_PMU_RPPG_CMD_ID_INIT_CTRL,
-        NV_PMU_RPPG_CMD_ID_STATS_RESET,
-};
-struct nv_pmu_rppg_msg_common {
-        u8 msg_type;
-        u8 msg_id;
-};
-struct nv_pmu_rppg_msg_init_ctrl_ack {
-        u8 msg_type;
-        u8 msg_id;
-        u8 ctrl_id;
-        u32 stats_dmem_offset;
-};
-struct nv_pmu_rppg_msg {
-        union {
-                u8 msg_type;
-                struct nv_pmu_rppg_msg_common cmn;
-                struct nv_pmu_rppg_msg_init_ctrl_ack init_ctrl_ack;
-        };
-};
-enum {
-        NV_PMU_RPPG_MSG_ID_INIT_CTRL_ACK = 0x0,
-};
-#endif /* NVGPU_PMUIF_GPMUIF_PG_RPPG_H */

diff --git a/include/nvgpu/pmuif/gpmuif_pg_rppg.h b/include/nvgpu/pmuif/gpmuif_pg_rppg.h deleted file mode 100644 index 05445f6..0000000 --- a/include/nvgpu/pmuif/gpmuif_pg_rppg.h +++ /dev/null
@@ -1,110 +0,0 @@
1	/*
2	* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3	*
4	* Permission is hereby granted, free of charge, to any person obtaining a
5	* copy of this software and associated documentation files (the "Software"),
6	* to deal in the Software without restriction, including without limitation
7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8	* and/or sell copies of the Software, and to permit persons to whom the
9	* Software is furnished to do so, subject to the following conditions:
10	*
11	* The above copyright notice and this permission notice shall be included in
12	* all copies or substantial portions of the Software.
13	*
14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20	* DEALINGS IN THE SOFTWARE.
21	*/
22	#ifndef NVGPU_PMUIF_GPMUIF_PG_RPPG_H
23	#define NVGPU_PMUIF_GPMUIF_PG_RPPG_H
24
25	#define NV_PMU_RPPG_CTRL_ID_GR (0x0000)
26	#define NV_PMU_RPPG_CTRL_ID_MS (0x0001)
27	#define NV_PMU_RPPG_CTRL_ID_DI (0x0002)
28	#define NV_PMU_RPPG_CTRL_ID_MAX (0x0003)
29
30	#define NV_PMU_RPPG_CTRL_MASK_ENABLE_ALL (BIT(NV_PMU_RPPG_CTRL_ID_GR) \|\
31	BIT(NV_PMU_RPPG_CTRL_ID_MS) \|\
32	BIT(NV_PMU_RPPG_CTRL_ID_DI))
33
34	#define NV_PMU_RPPG_CTRL_MASK_DISABLE_ALL 0
35
36	enum {
37	NV_PMU_RPPG_DOMAIN_ID_GFX = 0x0,
38	NV_PMU_RPPG_DOMAIN_ID_NON_GFX,
39	};
40
41	struct nv_pmu_rppg_ctrl_stats {
42	u32 entry_count;
43	u32 exit_count;
44	};
45
46	struct nv_pmu_rppg_cmd_common {
47	u8 cmd_type;
48	u8 cmd_id;
49	};
50
51	struct nv_pmu_rppg_cmd_init {
52	u8 cmd_type;
53	u8 cmd_id;
54	};
55
56	struct nv_pmu_rppg_cmd_init_ctrl {
57	u8 cmd_type;
58	u8 cmd_id;
59	u8 ctrl_id;
60	u8 domain_id;
61	};
62
63	struct nv_pmu_rppg_cmd_stats_reset {
64	u8 cmd_type;
65	u8 cmd_id;
66	u8 ctrl_id;
67	};
68
69	struct nv_pmu_rppg_cmd {
70	union {
71	u8 cmd_type;
72	struct nv_pmu_rppg_cmd_common cmn;
73	struct nv_pmu_rppg_cmd_init init;
74	struct nv_pmu_rppg_cmd_init_ctrl init_ctrl;
75	struct nv_pmu_rppg_cmd_stats_reset stats_reset;
76	};
77	};
78
79	enum {
80	NV_PMU_RPPG_CMD_ID_INIT = 0x0,
81	NV_PMU_RPPG_CMD_ID_INIT_CTRL,
82	NV_PMU_RPPG_CMD_ID_STATS_RESET,
83	};
84
85
86	struct nv_pmu_rppg_msg_common {
87	u8 msg_type;
88	u8 msg_id;
89	};
90
91	struct nv_pmu_rppg_msg_init_ctrl_ack {
92	u8 msg_type;
93	u8 msg_id;
94	u8 ctrl_id;
95	u32 stats_dmem_offset;
96	};
97
98	struct nv_pmu_rppg_msg {
99	union {
100	u8 msg_type;
101	struct nv_pmu_rppg_msg_common cmn;
102	struct nv_pmu_rppg_msg_init_ctrl_ack init_ctrl_ack;
103	};
104	};
105
106	enum {
107	NV_PMU_RPPG_MSG_ID_INIT_CTRL_ACK = 0x0,
108	};
109
110	#endif /* NVGPU_PMUIF_GPMUIF_PG_RPPG_H */