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-rw-r--r--include/nvgpu/pmuif/gpmuif_pg.h424
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diff --git a/include/nvgpu/pmuif/gpmuif_pg.h b/include/nvgpu/pmuif/gpmuif_pg.h
deleted file mode 100644
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--- a/include/nvgpu/pmuif/gpmuif_pg.h
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1/*
2 * Copyright (c) 2017-2022, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22#ifndef NVGPU_PMUIF_GPMUIF_PG_H
23#define NVGPU_PMUIF_GPMUIF_PG_H
24
25#include "gpmuif_ap.h"
26#include "gpmuif_pg_rppg.h"
27
28/*PG defines*/
29
30/* Identifier for each PG */
31#define PMU_PG_ELPG_ENGINE_ID_GRAPHICS (0x00000000U)
32#define PMU_PG_ELPG_ENGINE_ID_MS (0x00000004U)
33#define PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE (0x00000005U)
34#define PMU_PG_ELPG_ENGINE_MAX PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE
35
36/* Async PG message IDs */
37enum {
38 PMU_PG_MSG_ASYNC_CMD_DISALLOW,
39};
40
41/* PG message */
42enum {
43 PMU_PG_ELPG_MSG_INIT_ACK,
44 PMU_PG_ELPG_MSG_DISALLOW_ACK,
45 PMU_PG_ELPG_MSG_ALLOW_ACK,
46 PMU_PG_ELPG_MSG_FREEZE_ACK,
47 PMU_PG_ELPG_MSG_FREEZE_ABORT,
48 PMU_PG_ELPG_MSG_UNFREEZE_ACK,
49};
50
51struct pmu_pg_msg_elpg_msg {
52 u8 msg_type;
53 u8 engine_id;
54 u16 msg;
55};
56
57enum {
58 PMU_PG_STAT_MSG_RESP_DMEM_OFFSET = 0,
59};
60
61struct pmu_pg_msg_stat {
62 u8 msg_type;
63 u8 engine_id;
64 u16 sub_msg_id;
65 u32 data;
66};
67
68enum {
69 PMU_PG_MSG_ENG_BUF_LOADED,
70 PMU_PG_MSG_ENG_BUF_UNLOADED,
71 PMU_PG_MSG_ENG_BUF_FAILED,
72};
73
74struct pmu_pg_msg_eng_buf_stat {
75 u8 msg_type;
76 u8 engine_id;
77 u8 buf_idx;
78 u8 status;
79};
80
81struct pmu_pg_msg_async_cmd_resp {
82 u8 msg_type;
83 u8 ctrl_id;
84 u8 msg_id;
85};
86
87struct pmu_pg_msg {
88 union {
89 u8 msg_type;
90 struct pmu_pg_msg_elpg_msg elpg_msg;
91 struct pmu_pg_msg_stat stat;
92 struct pmu_pg_msg_eng_buf_stat eng_buf_stat;
93 struct pmu_pg_msg_async_cmd_resp async_cmd_resp;
94 /* TBD: other pg messages */
95 union pmu_ap_msg ap_msg;
96 struct nv_pmu_rppg_msg rppg_msg;
97 };
98};
99
100/* PG commands */
101enum {
102 PMU_PG_ELPG_CMD_INIT,
103 PMU_PG_ELPG_CMD_DISALLOW,
104 PMU_PG_ELPG_CMD_ALLOW,
105 PMU_PG_ELPG_CMD_FREEZE,
106 PMU_PG_ELPG_CMD_UNFREEZE,
107};
108
109enum {
110 PMU_PG_CMD_ID_ELPG_CMD = 0,
111 PMU_PG_CMD_ID_ENG_BUF_LOAD,
112 PMU_PG_CMD_ID_ENG_BUF_UNLOAD,
113 PMU_PG_CMD_ID_PG_STAT,
114 PMU_PG_CMD_ID_PG_LOG_INIT,
115 PMU_PG_CMD_ID_PG_LOG_FLUSH,
116 PMU_PG_CMD_ID_PG_PARAM,
117 PMU_PG_CMD_ID_ELPG_INIT,
118 PMU_PG_CMD_ID_ELPG_POLL_CTXSAVE,
119 PMU_PG_CMD_ID_ELPG_ABORT_POLL,
120 PMU_PG_CMD_ID_ELPG_PWR_UP,
121 PMU_PG_CMD_ID_ELPG_DISALLOW,
122 PMU_PG_CMD_ID_ELPG_ALLOW,
123 PMU_PG_CMD_ID_AP,
124 RM_PMU_PG_CMD_ID_PSI,
125 RM_PMU_PG_CMD_ID_CG,
126 PMU_PG_CMD_ID_ZBC_TABLE_UPDATE,
127 PMU_PG_CMD_ID_PWR_RAIL_GATE_DISABLE = 0x20,
128 PMU_PG_CMD_ID_PWR_RAIL_GATE_ENABLE,
129 PMU_PG_CMD_ID_PWR_RAIL_SMU_MSG_DISABLE,
130 PMU_PMU_PG_CMD_ID_RPPG = 0x24,
131};
132
133enum {
134 PMU_PG_STAT_CMD_ALLOC_DMEM = 0,
135};
136
137enum {
138 SLOWDOWN_FACTOR_FPDIV_BY1 = 0,
139 SLOWDOWN_FACTOR_FPDIV_BY1P5,
140 SLOWDOWN_FACTOR_FPDIV_BY2,
141 SLOWDOWN_FACTOR_FPDIV_BY2P5,
142 SLOWDOWN_FACTOR_FPDIV_BY3,
143 SLOWDOWN_FACTOR_FPDIV_BY3P5,
144 SLOWDOWN_FACTOR_FPDIV_BY4,
145 SLOWDOWN_FACTOR_FPDIV_BY4P5,
146 SLOWDOWN_FACTOR_FPDIV_BY5,
147 SLOWDOWN_FACTOR_FPDIV_BY5P5,
148 SLOWDOWN_FACTOR_FPDIV_BY6,
149 SLOWDOWN_FACTOR_FPDIV_BY6P5,
150 SLOWDOWN_FACTOR_FPDIV_BY7,
151 SLOWDOWN_FACTOR_FPDIV_BY7P5,
152 SLOWDOWN_FACTOR_FPDIV_BY8,
153 SLOWDOWN_FACTOR_FPDIV_BY8P5,
154 SLOWDOWN_FACTOR_FPDIV_BY9,
155 SLOWDOWN_FACTOR_FPDIV_BY9P5,
156 SLOWDOWN_FACTOR_FPDIV_BY10,
157 SLOWDOWN_FACTOR_FPDIV_BY10P5,
158 SLOWDOWN_FACTOR_FPDIV_BY11,
159 SLOWDOWN_FACTOR_FPDIV_BY11P5,
160 SLOWDOWN_FACTOR_FPDIV_BY12,
161 SLOWDOWN_FACTOR_FPDIV_BY12P5,
162 SLOWDOWN_FACTOR_FPDIV_BY13,
163 SLOWDOWN_FACTOR_FPDIV_BY13P5,
164 SLOWDOWN_FACTOR_FPDIV_BY14,
165 SLOWDOWN_FACTOR_FPDIV_BY14P5,
166 SLOWDOWN_FACTOR_FPDIV_BY15,
167 SLOWDOWN_FACTOR_FPDIV_BY15P5,
168 SLOWDOWN_FACTOR_FPDIV_BY16,
169 SLOWDOWN_FACTOR_FPDIV_BY16P5,
170 SLOWDOWN_FACTOR_FPDIV_BY17 = 0x20,
171 SLOWDOWN_FACTOR_FPDIV_BY18 = 0x22,
172 SLOWDOWN_FACTOR_FPDIV_BY19 = 0x24,
173 SLOWDOWN_FACTOR_FPDIV_BY20 = 0x26,
174 SLOWDOWN_FACTOR_FPDIV_BY21 = 0x28,
175 SLOWDOWN_FACTOR_FPDIV_BY22 = 0x2a,
176 SLOWDOWN_FACTOR_FPDIV_BY23 = 0x2c,
177 SLOWDOWN_FACTOR_FPDIV_BY24 = 0x2e,
178 SLOWDOWN_FACTOR_FPDIV_BY25 = 0x30,
179 SLOWDOWN_FACTOR_FPDIV_BY26 = 0x32,
180 SLOWDOWN_FACTOR_FPDIV_BY27 = 0x34,
181 SLOWDOWN_FACTOR_FPDIV_BY28 = 0x36,
182 SLOWDOWN_FACTOR_FPDIV_BY29 = 0x38,
183 SLOWDOWN_FACTOR_FPDIV_BY30 = 0x3a,
184 SLOWDOWN_FACTOR_FPDIV_BY31 = 0x3c,
185 SLOWDOWN_FACTOR_FPDIV_BYMAX,
186};
187
188#define PMU_PG_PARAM_CMD_GR_INIT_PARAM 0x0U
189#define PMU_PG_PARAM_CMD_MS_INIT_PARAM 0x01U
190#define PMU_PG_PARAM_CMD_MCLK_CHANGE 0x04U
191#define PMU_PG_PARAM_CMD_POST_INIT 0x06U
192#define PMU_PG_PARAM_CMD_SUB_FEATURE_MASK_UPDATE 0x07U
193
194#define NVGPU_PMU_GR_FEATURE_MASK_SDIV_SLOWDOWN BIT32(0)
195#define NVGPU_PMU_GR_FEATURE_MASK_POWER_GATING BIT32(2)
196#define NVGPU_PMU_GR_FEATURE_MASK_RPPG BIT32(3)
197#define NVGPU_PMU_GR_FEATURE_MASK_PRIV_RING BIT32(5)
198#define NVGPU_PMU_GR_FEATURE_MASK_UNBIND BIT32(6)
199#define NVGPU_PMU_GR_FEATURE_MASK_SAVE_GLOBAL_STATE BIT32(7)
200#define NVGPU_PMU_GR_FEATURE_MASK_RESET_ENTRY BIT32(8)
201#define NVGPU_PMU_GR_FEATURE_MASK_HW_SEQUENCE BIT32(9)
202#define NVGPU_PMU_GR_FEATURE_MASK_ELPG_SRAM BIT32(10)
203#define NVGPU_PMU_GR_FEATURE_MASK_ELPG_LOGIC BIT32(11)
204#define NVGPU_PMU_GR_FEATURE_MASK_ELPG_L2RPPG BIT32(12)
205
206#define NVGPU_PMU_GR_FEATURE_MASK_ALL \
207 ( \
208 NVGPU_PMU_GR_FEATURE_MASK_SDIV_SLOWDOWN |\
209 NVGPU_PMU_GR_FEATURE_MASK_POWER_GATING |\
210 NVGPU_PMU_GR_FEATURE_MASK_RPPG |\
211 NVGPU_PMU_GR_FEATURE_MASK_PRIV_RING |\
212 NVGPU_PMU_GR_FEATURE_MASK_UNBIND |\
213 NVGPU_PMU_GR_FEATURE_MASK_SAVE_GLOBAL_STATE |\
214 NVGPU_PMU_GR_FEATURE_MASK_RESET_ENTRY |\
215 NVGPU_PMU_GR_FEATURE_MASK_HW_SEQUENCE |\
216 NVGPU_PMU_GR_FEATURE_MASK_ELPG_SRAM |\
217 NVGPU_PMU_GR_FEATURE_MASK_ELPG_LOGIC |\
218 NVGPU_PMU_GR_FEATURE_MASK_ELPG_L2RPPG \
219 )
220
221#define NVGPU_PMU_MS_FEATURE_MASK_CLOCK_GATING BIT32(0)
222#define NVGPU_PMU_MS_FEATURE_MASK_SW_ASR BIT32(1)
223#define NVGPU_PMU_MS_FEATURE_MASK_RPPG BIT32(8)
224#define NVGPU_PMU_MS_FEATURE_MASK_FB_TRAINING BIT32(5)
225
226#define NVGPU_PMU_MS_FEATURE_MASK_ALL \
227 ( \
228 NVGPU_PMU_MS_FEATURE_MASK_CLOCK_GATING |\
229 NVGPU_PMU_MS_FEATURE_MASK_SW_ASR |\
230 NVGPU_PMU_MS_FEATURE_MASK_RPPG |\
231 NVGPU_PMU_MS_FEATURE_MASK_FB_TRAINING \
232 )
233
234
235struct pmu_pg_cmd_elpg_cmd {
236 u8 cmd_type;
237 u8 engine_id;
238 u16 cmd;
239};
240
241struct pmu_pg_cmd_eng_buf_load_v0 {
242 u8 cmd_type;
243 u8 engine_id;
244 u8 buf_idx;
245 u8 pad;
246 u16 buf_size;
247 u32 dma_base;
248 u8 dma_offset;
249 u8 dma_idx;
250};
251
252struct pmu_pg_cmd_eng_buf_load_v1 {
253 u8 cmd_type;
254 u8 engine_id;
255 u8 buf_idx;
256 u8 pad;
257 struct flcn_mem_desc {
258 struct falc_u64 dma_addr;
259 u16 dma_size;
260 u8 dma_idx;
261 } dma_desc;
262};
263
264struct pmu_pg_cmd_eng_buf_load_v2 {
265 u8 cmd_type;
266 u8 engine_id;
267 u8 buf_idx;
268 u8 pad;
269 struct flcn_mem_desc_v0 dma_desc;
270};
271
272struct pmu_pg_cmd_gr_init_param {
273 u8 cmd_type;
274 u16 sub_cmd_id;
275 u8 featuremask;
276};
277
278struct pmu_pg_cmd_gr_init_param_v2 {
279 u8 cmd_type;
280 u16 sub_cmd_id;
281 u8 featuremask;
282 u8 ldiv_slowdown_factor;
283};
284
285struct pmu_pg_cmd_gr_init_param_v1 {
286 u8 cmd_type;
287 u16 sub_cmd_id;
288 u32 featuremask;
289};
290
291struct pmu_pg_cmd_sub_feature_mask_update {
292 u8 cmd_type;
293 u16 sub_cmd_id;
294 u8 ctrl_id;
295 u32 enabled_mask;
296};
297
298struct pmu_pg_cmd_ms_init_param {
299 u8 cmd_type;
300 u16 cmd_id;
301 u8 psi;
302 u8 idle_flipped_test_enabled;
303 u16 psiSettleTimeUs;
304 u8 rsvd[2];
305 u32 support_mask;
306 u32 abort_timeout_us;
307};
308
309struct pmu_pg_cmd_mclk_change {
310 u8 cmd_type;
311 u16 cmd_id;
312 u8 rsvd;
313 u32 data;
314};
315
316#define PG_VOLT_RAIL_IDX_MAX 2
317
318struct pmu_pg_volt_rail {
319 u8 volt_rail_idx;
320 u8 sleep_volt_dev_idx;
321 u8 sleep_vfe_idx;
322 u32 sleep_voltage_uv;
323 u32 therm_vid0_cache;
324 u32 therm_vid1_cache;
325};
326
327struct pmu_pg_cmd_post_init_param {
328 u8 cmd_type;
329 u16 cmd_id;
330 struct pmu_pg_volt_rail pg_volt_rail[PG_VOLT_RAIL_IDX_MAX];
331};
332
333struct pmu_pg_cmd_stat {
334 u8 cmd_type;
335 u8 engine_id;
336 u16 sub_cmd_id;
337 u32 data;
338};
339
340struct pmu_pg_cmd {
341 union {
342 u8 cmd_type;
343 struct pmu_pg_cmd_elpg_cmd elpg_cmd;
344 struct pmu_pg_cmd_eng_buf_load_v0 eng_buf_load_v0;
345 struct pmu_pg_cmd_eng_buf_load_v1 eng_buf_load_v1;
346 struct pmu_pg_cmd_eng_buf_load_v2 eng_buf_load_v2;
347 struct pmu_pg_cmd_stat stat;
348 struct pmu_pg_cmd_gr_init_param gr_init_param;
349 struct pmu_pg_cmd_gr_init_param_v1 gr_init_param_v1;
350 struct pmu_pg_cmd_gr_init_param_v2 gr_init_param_v2;
351 struct pmu_pg_cmd_ms_init_param ms_init_param;
352 struct pmu_pg_cmd_mclk_change mclk_change;
353 struct pmu_pg_cmd_post_init_param post_init;
354 /* TBD: other pg commands */
355 union pmu_ap_cmd ap_cmd;
356 struct nv_pmu_rppg_cmd rppg_cmd;
357 struct pmu_pg_cmd_sub_feature_mask_update sf_mask_update;
358 };
359};
360
361/* Statistics structure for PG features */
362struct pmu_pg_stats_v2 {
363 u32 entry_count;
364 u32 exit_count;
365 u32 abort_count;
366 u32 detection_count;
367 u32 prevention_activate_count;
368 u32 prevention_deactivate_count;
369 u32 powered_up_time_us;
370 u32 entry_latency_us;
371 u32 exit_latency_us;
372 u32 resident_time_us;
373 u32 entry_latency_avg_us;
374 u32 exit_latency_avg_us;
375 u32 entry_latency_max_us;
376 u32 exit_latency_max_us;
377 u32 total_sleep_time_us;
378 u32 total_non_sleep_time_us;
379};
380
381struct pmu_pg_stats_v1 {
382 /* Number of time PMU successfully engaged sleep state */
383 u32 entry_count;
384 /* Number of time PMU exit sleep state */
385 u32 exit_count;
386 /* Number of time PMU aborted in entry sequence */
387 u32 abort_count;
388 /*
389 * Time for which GPU was neither in Sleep state not
390 * executing sleep sequence.
391 */
392 u32 poweredup_timeus;
393 /* Entry and exit latency of current sleep cycle */
394 u32 entry_latency_us;
395 u32 exitlatencyus;
396 /* Resident time for current sleep cycle. */
397 u32 resident_timeus;
398 /* Rolling average entry and exit latencies */
399 u32 entrylatency_avgus;
400 u32 exitlatency_avgus;
401 /* Max entry and exit latencies */
402 u32 entrylatency_maxus;
403 u32 exitlatency_maxus;
404 /* Total time spent in sleep and non-sleep state */
405 u32 total_sleep_timeus;
406 u32 total_nonsleep_timeus;
407};
408
409struct pmu_pg_stats {
410 u64 pg_entry_start_timestamp;
411 u64 pg_ingating_start_timestamp;
412 u64 pg_exit_start_timestamp;
413 u64 pg_ungating_start_timestamp;
414 u32 pg_avg_entry_time_us;
415 u32 pg_ingating_cnt;
416 u32 pg_ingating_time_us;
417 u32 pg_avg_exit_time_us;
418 u32 pg_ungating_count;
419 u32 pg_ungating_time_us;
420 u32 pg_gating_cnt;
421 u32 pg_gating_deny_cnt;
422};
423
424#endif /* NVGPU_PMUIF_GPMUIF_PG_H*/
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-30 18:13:35 -0400