1 files changed, 0 insertions, 142 deletions
diff --git a/include/nvgpu/pmuif/gpmuif_cmn.h b/include/nvgpu/pmuif/gpmuif_cmn.h
deleted file mode 100644
index 0989754..0000000
--- a/include/nvgpu/pmuif/gpmuif_cmn.h
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-#ifndef NVGPU_PMUIF_GPMUIF_CMN_H
-#define NVGPU_PMUIF_GPMUIF_CMN_H
-/*
- * Defines the logical queue IDs that must be used when submitting
- * commands to the PMU
- */
-/* write by sw, read by pmu, protected by sw mutex lock */
-#define PMU_COMMAND_QUEUE_HPQ           0U
-/* write by sw, read by pmu, protected by sw mutex lock */
-#define PMU_COMMAND_QUEUE_LPQ           1U
-/* write by pmu, read by sw, accessed by interrupt handler, no lock */
-#define PMU_MESSAGE_QUEUE               4U
-#define PMU_QUEUE_COUNT                 5U
-#define PMU_IS_COMMAND_QUEUE(id)        \
-                ((id)  < PMU_MESSAGE_QUEUE)
-#define PMU_IS_SW_COMMAND_QUEUE(id)     \
-                (((id) == PMU_COMMAND_QUEUE_HPQ) || \
-                 ((id) == PMU_COMMAND_QUEUE_LPQ))
-#define  PMU_IS_MESSAGE_QUEUE(id)       \
-                ((id) == PMU_MESSAGE_QUEUE)
-#define OFLAG_READ      0U
-#define OFLAG_WRITE     1U
-#define QUEUE_SET               (true)
-#define QUEUE_GET               (false)
-#define QUEUE_ALIGNMENT         (4U)
-/* An enumeration containing all valid logical mutex identifiers */
-enum {
-        PMU_MUTEX_ID_RSVD1 = 0,
-        PMU_MUTEX_ID_GPUSER,
-        PMU_MUTEX_ID_QUEUE_BIOS,
-        PMU_MUTEX_ID_QUEUE_SMI,
-        PMU_MUTEX_ID_GPMUTEX,
-        PMU_MUTEX_ID_I2C,
-        PMU_MUTEX_ID_RMLOCK,
-        PMU_MUTEX_ID_MSGBOX,
-        PMU_MUTEX_ID_FIFO,
-        PMU_MUTEX_ID_PG,
-        PMU_MUTEX_ID_GR,
-        PMU_MUTEX_ID_CLK,
-        PMU_MUTEX_ID_RSVD6,
-        PMU_MUTEX_ID_RSVD7,
-        PMU_MUTEX_ID_RSVD8,
-        PMU_MUTEX_ID_RSVD9,
-        PMU_MUTEX_ID_INVALID
-};
-#define PMU_MUTEX_ID_IS_VALID(id)       \
-                ((id) < PMU_MUTEX_ID_INVALID)
-#define PMU_INVALID_MUTEX_OWNER_ID      (0)
-/*
- * The PMU's frame-buffer interface block has several slots/indices
- * which can be bound to support DMA to various surfaces in memory
- */
-enum {
-        PMU_DMAIDX_UCODE         = 0,
-        PMU_DMAIDX_VIRT          = 1,
-        PMU_DMAIDX_PHYS_VID      = 2,
-        PMU_DMAIDX_PHYS_SYS_COH  = 3,
-        PMU_DMAIDX_PHYS_SYS_NCOH = 4,
-        PMU_DMAIDX_RSVD          = 5,
-        PMU_DMAIDX_PELPG         = 6,
-        PMU_DMAIDX_END           = 7
-};
-/*
- * Falcon PMU DMA's minimum size in bytes.
- */
-#define PMU_DMA_MIN_READ_SIZE_BYTES             16
-#define PMU_DMA_MIN_WRITE_SIZE_BYTES    4
-#define PMU_FB_COPY_RW_ALIGNMENT        \
-        ((PMU_DMA_MIN_READ_SIZE_BYTES > PMU_DMA_MIN_WRITE_SIZE_BYTES) ? \
-        PMU_DMA_MIN_READ_SIZE_BYTES : PMU_DMA_MIN_WRITE_SIZE_BYTES)
-/*
- * Macros to make aligned versions of RM_PMU_XXX structures. PMU needs aligned
- * data structures to issue DMA read/write operations.
- */
-#define NV_PMU_MAKE_ALIGNED_STRUCT(name, size)           \
-union name##_aligned {                                   \
-                struct name data;                        \
-                u8 pad[ALIGN_UP(sizeof(struct name),     \
-                (PMU_FB_COPY_RW_ALIGNMENT))];            \
-}
-#define NV_PMU_MAKE_ALIGNED_UNION(name, size)            \
-union name##_aligned {                                   \
-                union name data;                         \
-                u8 pad[ALIGN_UP(sizeof(union name),      \
-                (PMU_FB_COPY_RW_ALIGNMENT))];            \
-}
-/* RPC (Remote Procedure Call) header structure */
-#define NV_PMU_RPC_FLAGS_TYPE_SYNC 0x00000000
-struct nv_pmu_rpc_header {
-        /* Identifies the unit servicing requested RPC*/
-        u8  unit_id;
-        /* Identifies the requested RPC (within the unit)*/
-        u8  function;
-        /* RPC call flags (@see PMU_RPC_FLAGS) */
-        u8  flags;
-        /* Falcon's status code to describe failures*/
-        u8  flcn_status;
-        /* RPC's total exec. time (measured on nvgpu driver side)*/
-        u32  exec_time_nv_ns;
-        /* RPC's actual exec. time (measured on PMU side)*/
-        u32  exec_time_pmu_ns;
-};
-#endif /* NVGPU_PMUIF_GPMUIF_CMN_H*/

diff --git a/include/nvgpu/pmuif/gpmuif_cmn.h b/include/nvgpu/pmuif/gpmuif_cmn.h deleted file mode 100644 index 0989754..0000000 --- a/include/nvgpu/pmuif/gpmuif_cmn.h +++ /dev/null
@@ -1,142 +0,0 @@
1	/*
2	* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
3	*
4	* Permission is hereby granted, free of charge, to any person obtaining a
5	* copy of this software and associated documentation files (the "Software"),
6	* to deal in the Software without restriction, including without limitation
7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8	* and/or sell copies of the Software, and to permit persons to whom the
9	* Software is furnished to do so, subject to the following conditions:
10	*
11	* The above copyright notice and this permission notice shall be included in
12	* all copies or substantial portions of the Software.
13	*
14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20	* DEALINGS IN THE SOFTWARE.
21	*/
22	#ifndef NVGPU_PMUIF_GPMUIF_CMN_H
23	#define NVGPU_PMUIF_GPMUIF_CMN_H
24
25	/*
26	* Defines the logical queue IDs that must be used when submitting
27	* commands to the PMU
28	*/
29	/* write by sw, read by pmu, protected by sw mutex lock */
30	#define PMU_COMMAND_QUEUE_HPQ 0U
31	/* write by sw, read by pmu, protected by sw mutex lock */
32	#define PMU_COMMAND_QUEUE_LPQ 1U
33	/* write by pmu, read by sw, accessed by interrupt handler, no lock */
34	#define PMU_MESSAGE_QUEUE 4U
35	#define PMU_QUEUE_COUNT 5U
36
37	#define PMU_IS_COMMAND_QUEUE(id) \
38	((id) < PMU_MESSAGE_QUEUE)
39
40	#define PMU_IS_SW_COMMAND_QUEUE(id) \
41	(((id) == PMU_COMMAND_QUEUE_HPQ) \|\| \
42	((id) == PMU_COMMAND_QUEUE_LPQ))
43
44	#define PMU_IS_MESSAGE_QUEUE(id) \
45	((id) == PMU_MESSAGE_QUEUE)
46
47	#define OFLAG_READ 0U
48	#define OFLAG_WRITE 1U
49
50	#define QUEUE_SET (true)
51	#define QUEUE_GET (false)
52
53	#define QUEUE_ALIGNMENT (4U)
54
55	/* An enumeration containing all valid logical mutex identifiers */
56	enum {
57	PMU_MUTEX_ID_RSVD1 = 0,
58	PMU_MUTEX_ID_GPUSER,
59	PMU_MUTEX_ID_QUEUE_BIOS,
60	PMU_MUTEX_ID_QUEUE_SMI,
61	PMU_MUTEX_ID_GPMUTEX,
62	PMU_MUTEX_ID_I2C,
63	PMU_MUTEX_ID_RMLOCK,
64	PMU_MUTEX_ID_MSGBOX,
65	PMU_MUTEX_ID_FIFO,
66	PMU_MUTEX_ID_PG,
67	PMU_MUTEX_ID_GR,
68	PMU_MUTEX_ID_CLK,
69	PMU_MUTEX_ID_RSVD6,
70	PMU_MUTEX_ID_RSVD7,
71	PMU_MUTEX_ID_RSVD8,
72	PMU_MUTEX_ID_RSVD9,
73	PMU_MUTEX_ID_INVALID
74	};
75
76	#define PMU_MUTEX_ID_IS_VALID(id) \
77	((id) < PMU_MUTEX_ID_INVALID)
78
79	#define PMU_INVALID_MUTEX_OWNER_ID (0)
80
81	/*
82	* The PMU's frame-buffer interface block has several slots/indices
83	* which can be bound to support DMA to various surfaces in memory
84	*/
85	enum {
86	PMU_DMAIDX_UCODE = 0,
87	PMU_DMAIDX_VIRT = 1,
88	PMU_DMAIDX_PHYS_VID = 2,
89	PMU_DMAIDX_PHYS_SYS_COH = 3,
90	PMU_DMAIDX_PHYS_SYS_NCOH = 4,
91	PMU_DMAIDX_RSVD = 5,
92	PMU_DMAIDX_PELPG = 6,
93	PMU_DMAIDX_END = 7
94	};
95
96	/*
97	* Falcon PMU DMA's minimum size in bytes.
98	*/
99	#define PMU_DMA_MIN_READ_SIZE_BYTES 16
100	#define PMU_DMA_MIN_WRITE_SIZE_BYTES 4
101
102	#define PMU_FB_COPY_RW_ALIGNMENT \
103	((PMU_DMA_MIN_READ_SIZE_BYTES > PMU_DMA_MIN_WRITE_SIZE_BYTES) ? \
104	PMU_DMA_MIN_READ_SIZE_BYTES : PMU_DMA_MIN_WRITE_SIZE_BYTES)
105
106	/*
107	* Macros to make aligned versions of RM_PMU_XXX structures. PMU needs aligned
108	* data structures to issue DMA read/write operations.
109	*/
110	#define NV_PMU_MAKE_ALIGNED_STRUCT(name, size) \
111	union name##_aligned { \
112	struct name data; \
113	u8 pad[ALIGN_UP(sizeof(struct name), \
114	(PMU_FB_COPY_RW_ALIGNMENT))]; \
115	}
116
117	#define NV_PMU_MAKE_ALIGNED_UNION(name, size) \
118	union name##_aligned { \
119	union name data; \
120	u8 pad[ALIGN_UP(sizeof(union name), \
121	(PMU_FB_COPY_RW_ALIGNMENT))]; \
122	}
123
124	/* RPC (Remote Procedure Call) header structure */
125	#define NV_PMU_RPC_FLAGS_TYPE_SYNC 0x00000000
126
127	struct nv_pmu_rpc_header {
128	/* Identifies the unit servicing requested RPC*/
129	u8 unit_id;
130	/* Identifies the requested RPC (within the unit)*/
131	u8 function;
132	/* RPC call flags (@see PMU_RPC_FLAGS) */
133	u8 flags;
134	/* Falcon's status code to describe failures*/
135	u8 flcn_status;
136	/* RPC's total exec. time (measured on nvgpu driver side)*/
137	u32 exec_time_nv_ns;
138	/* RPC's actual exec. time (measured on PMU side)*/
139	u32 exec_time_pmu_ns;
140	};
141
142	#endif /* NVGPU_PMUIF_GPMUIF_CMN_H*/