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diff --git a/include/nvgpu/nvlink.h b/include/nvgpu/nvlink.h
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1/*
2 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef NVGPU_NVLINK_H
24#define NVGPU_NVLINK_H
25
26#include <nvgpu/types.h>
27
28#ifdef __KERNEL__
29#include <nvgpu/linux/nvlink.h>
30#elif defined(__NVGPU_POSIX__)
31#include <nvgpu/posix/nvlink.h>
32#else
33#include <nvgpu_rmos/include/nvlink.h>
34#endif
35
36#define NV_NVLINK_REG_POLL_TIMEOUT_MS 3000
37#define NV_NVLINK_TIMEOUT_DELAY_US 5
38
39#define MINION_REG_RD32(g, off) gk20a_readl(g, g->nvlink.minion_base + (off))
40#define MINION_REG_WR32(g, off, v) gk20a_writel(g, g->nvlink.minion_base + (off), (v))
41#define IOCTRL_REG_RD32(g, off) gk20a_readl(g, g->nvlink.ioctrl_base + (off))
42#define IOCTRL_REG_WR32(g, off, v) gk20a_writel(g, g->nvlink.ioctrl_base + (off), (v))
43#define MIF_REG_RD32(g, id, off) gk20a_readl(g, g->nvlink.links[(id)].mif_base + (off))
44#define MIF_REG_WR32(g, id, off, v) gk20a_writel(g, g->nvlink.links[(id)].mif_base + (off), (v))
45#define IPT_REG_RD32(g, off) gk20a_readl(g, g->nvlink.ipt_base + (off))
46#define IPT_REG_WR32(g, off, v) gk20a_writel(g, g->nvlink.ipt_base + (off), (v))
47#define TLC_REG_RD32(g, id, off) gk20a_readl(g, g->nvlink.links[(id)].tl_base + (off))
48#define TLC_REG_WR32(g, id, off, v) gk20a_writel(g, g->nvlink.links[(id)].tl_base + (off), (v))
49#define DLPL_REG_RD32(g, id, off) gk20a_readl(g, g->nvlink.links[(id)].dlpl_base + (off))
50#define DLPL_REG_WR32(g, id, off, v) gk20a_writel(g, g->nvlink.links[(id)].dlpl_base + (off), (v))
51
52struct gk20a;
53
54struct nvgpu_nvlink_ioctrl_list {
55 bool valid;
56 u32 pri_base_addr;
57 u8 intr_enum;
58 u8 reset_enum;
59};
60
61struct nvgpu_nvlink_device_list {
62 bool valid;
63 u8 device_type;
64 u8 device_id;
65 u8 device_version;
66 u32 pri_base_addr;
67 u8 intr_enum;
68 u8 reset_enum;
69 u8 num_tx;
70 u8 num_rx;
71 u8 pll_master;
72 u8 pll_master_id;
73};
74
75enum nvgpu_nvlink_endp {
76 nvgpu_nvlink_endp_gpu,
77 nvgpu_nvlink_endp_tegra,
78 nvgpu_nvlink_endp__last,
79};
80
81enum nvgpu_nvlink_link_mode {
82 nvgpu_nvlink_link_off,
83 nvgpu_nvlink_link_hs,
84 nvgpu_nvlink_link_safe,
85 nvgpu_nvlink_link_fault,
86 nvgpu_nvlink_link_rcvy_ac,
87 nvgpu_nvlink_link_rcvy_sw,
88 nvgpu_nvlink_link_rcvy_rx,
89 nvgpu_nvlink_link_detect,
90 nvgpu_nvlink_link_reset,
91 nvgpu_nvlink_link_enable_pm,
92 nvgpu_nvlink_link_disable_pm,
93 nvgpu_nvlink_link_disable_err_detect,
94 nvgpu_nvlink_link_lane_disable,
95 nvgpu_nvlink_link_lane_shutdown,
96 nvgpu_nvlink_link__last,
97};
98
99enum nvgpu_nvlink_sublink_mode {
100 nvgpu_nvlink_sublink_tx_hs,
101 nvgpu_nvlink_sublink_tx_enable_pm,
102 nvgpu_nvlink_sublink_tx_disable_pm,
103 nvgpu_nvlink_sublink_tx_single_lane,
104 nvgpu_nvlink_sublink_tx_safe,
105 nvgpu_nvlink_sublink_tx_off,
106 nvgpu_nvlink_sublink_tx_common,
107 nvgpu_nvlink_sublink_tx_common_disable,
108 nvgpu_nvlink_sublink_tx_data_ready,
109 nvgpu_nvlink_sublink_tx_prbs_en,
110 nvgpu_nvlink_sublink_tx__last,
111 /* RX */
112 nvgpu_nvlink_sublink_rx_hs,
113 nvgpu_nvlink_sublink_rx_enable_pm,
114 nvgpu_nvlink_sublink_rx_disable_pm,
115 nvgpu_nvlink_sublink_rx_single_lane,
116 nvgpu_nvlink_sublink_rx_safe,
117 nvgpu_nvlink_sublink_rx_off,
118 nvgpu_nvlink_sublink_rx_rxcal,
119 nvgpu_nvlink_sublink_rx__last,
120};
121
122struct nvgpu_nvlink_conn_info {
123 enum nvgpu_nvlink_endp device_type;
124 u32 link_number;
125 bool is_connected;
126};
127
128struct nvgpu_nvlink_link {
129 bool valid;
130 struct gk20a *g;
131 u8 link_id;
132
133 u32 dlpl_base;
134 u8 dlpl_version;
135
136 u32 tl_base;
137 u8 tl_version;
138
139 u32 mif_base;
140 u8 mif_version;
141
142 u8 intr_enum;
143 u8 reset_enum;
144
145 bool dl_init_done;
146
147 u8 pll_master_link_id;
148 u8 pll_slave_link_id;
149
150 struct nvgpu_nvlink_conn_info remote_info;
151 void *priv;
152};
153
154#define NVLINK_MAX_LINKS_SW 6
155
156enum nvgpu_nvlink_speed {
157 nvgpu_nvlink_speed_25G,
158 nvgpu_nvlink_speed_20G,
159 nvgpu_nvlink_speed__last,
160};
161
162struct nvgpu_nvlink_dev {
163 struct nvgpu_nvlink_ioctrl_list *ioctrl_table;
164 u32 io_num_entries;
165
166 struct nvgpu_nvlink_device_list *device_table;
167 u32 num_devices;
168
169 struct nvgpu_nvlink_link links[NVLINK_MAX_LINKS_SW];
170
171 u8 dlpl_type;
172 u32 dlpl_base[NVLINK_MAX_LINKS_SW];
173
174 u8 tl_type;
175 u32 tl_base[NVLINK_MAX_LINKS_SW];
176
177 u8 mif_type;
178 u32 mif_base[NVLINK_MAX_LINKS_SW];
179
180 u8 ipt_type;
181 u32 ipt_base;
182 u8 ipt_version;
183
184 u8 dlpl_multicast_type;
185 u8 dlpl_multicast_version;
186 u32 dlpl_multicast_base;
187
188 u8 tl_multicast_type;
189 u8 tl_multicast_version;
190 u32 tl_multicast_base;
191
192 u8 mif_multicast_type;
193 u8 mif_multicast_version;
194 u32 mif_multicast_base;
195
196 u8 ioctrl_type;
197 u32 ioctrl_base;
198
199 u8 minion_type;
200 u32 minion_base;
201 u8 minion_version;
202
203 u32 discovered_links;
204
205 /* VBIOS settings */
206 u32 link_disable_mask;
207 u32 link_mode_mask;
208 u32 link_refclk_mask;
209 u8 train_at_boot;
210 u32 ac_coupling_mask;
211
212 u32 connected_links;
213 u32 initialized_links;
214 u32 enabled_links;
215 u32 init_pll_done;
216
217 enum nvgpu_nvlink_speed speed;
218
219 /* tlc cached errors */
220 u32 tlc_rx_err_status_0[NVLINK_MAX_LINKS_SW];
221 u32 tlc_rx_err_status_1[NVLINK_MAX_LINKS_SW];
222 u32 tlc_tx_err_status_0[NVLINK_MAX_LINKS_SW];
223
224 /* priv struct */
225 void *priv;
226};
227
228int nvgpu_nvlink_enumerate(struct gk20a *g);
229int nvgpu_nvlink_train(struct gk20a *g, u32 link_id, bool from_off);
230int nvgpu_nvlink_read_dt_props(struct gk20a *g);
231
232int nvgpu_nvlink_probe(struct gk20a *g);
233int nvgpu_nvlink_remove(struct gk20a *g);
234
235void nvgpu_mss_nvlink_init_credits(struct gk20a *g);
236
237#endif /* NVGPU_NVLINK_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-30 12:16:34 -0400