aboutsummaryrefslogtreecommitdiffstats
path: root/include/nvgpu/hw/gv100/hw_top_gv100.h
diff options
context:
space:
mode:
Diffstat (limited to 'include/nvgpu/hw/gv100/hw_top_gv100.h')
-rw-r--r--include/nvgpu/hw/gv100/hw_top_gv100.h343
1 files changed, 0 insertions, 343 deletions
diff --git a/include/nvgpu/hw/gv100/hw_top_gv100.h b/include/nvgpu/hw/gv100/hw_top_gv100.h
deleted file mode 100644
index 506a818..0000000
--- a/include/nvgpu/hw/gv100/hw_top_gv100.h
+++ /dev/null
@@ -1,343 +0,0 @@
1/*
2 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22/*
23 * Function naming determines intended use:
24 *
25 * <x>_r(void) : Returns the offset for register <x>.
26 *
27 * <x>_o(void) : Returns the offset for element <x>.
28 *
29 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
30 *
31 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
32 *
33 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
34 * and masked to place it at field <y> of register <x>. This value
35 * can be |'d with others to produce a full register value for
36 * register <x>.
37 *
38 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
39 * value can be ~'d and then &'d to clear the value of field <y> for
40 * register <x>.
41 *
42 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
43 * to place it at field <y> of register <x>. This value can be |'d
44 * with others to produce a full register value for <x>.
45 *
46 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
47 * <x> value 'r' after being shifted to place its LSB at bit 0.
48 * This value is suitable for direct comparison with other unshifted
49 * values appropriate for use in field <y> of register <x>.
50 *
51 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
52 * field <y> of register <x>. This value is suitable for direct
53 * comparison with unshifted values appropriate for use in field <y>
54 * of register <x>.
55 */
56#ifndef _hw_top_gv100_h_
57#define _hw_top_gv100_h_
58
59static inline u32 top_num_gpcs_r(void)
60{
61 return 0x00022430U;
62}
63static inline u32 top_num_gpcs_value_v(u32 r)
64{
65 return (r >> 0U) & 0x1fU;
66}
67static inline u32 top_tpc_per_gpc_r(void)
68{
69 return 0x00022434U;
70}
71static inline u32 top_tpc_per_gpc_value_v(u32 r)
72{
73 return (r >> 0U) & 0x1fU;
74}
75static inline u32 top_num_fbps_r(void)
76{
77 return 0x00022438U;
78}
79static inline u32 top_num_fbps_value_v(u32 r)
80{
81 return (r >> 0U) & 0x1fU;
82}
83static inline u32 top_num_fbpas_r(void)
84{
85 return 0x0002243cU;
86}
87static inline u32 top_num_fbpas_value_v(u32 r)
88{
89 return (r >> 0U) & 0x1fU;
90}
91static inline u32 top_ltc_per_fbp_r(void)
92{
93 return 0x00022450U;
94}
95static inline u32 top_ltc_per_fbp_value_v(u32 r)
96{
97 return (r >> 0U) & 0x1fU;
98}
99static inline u32 top_slices_per_ltc_r(void)
100{
101 return 0x0002245cU;
102}
103static inline u32 top_slices_per_ltc_value_v(u32 r)
104{
105 return (r >> 0U) & 0x1fU;
106}
107static inline u32 top_num_ltcs_r(void)
108{
109 return 0x00022454U;
110}
111static inline u32 top_num_ces_r(void)
112{
113 return 0x00022444U;
114}
115static inline u32 top_num_ces_value_v(u32 r)
116{
117 return (r >> 0U) & 0x1fU;
118}
119static inline u32 top_device_info_r(u32 i)
120{
121 return 0x00022700U + i*4U;
122}
123static inline u32 top_device_info__size_1_v(void)
124{
125 return 0x00000040U;
126}
127static inline u32 top_device_info_chain_v(u32 r)
128{
129 return (r >> 31U) & 0x1U;
130}
131static inline u32 top_device_info_chain_enable_v(void)
132{
133 return 0x00000001U;
134}
135static inline u32 top_device_info_engine_enum_v(u32 r)
136{
137 return (r >> 26U) & 0xfU;
138}
139static inline u32 top_device_info_runlist_enum_v(u32 r)
140{
141 return (r >> 21U) & 0xfU;
142}
143static inline u32 top_device_info_intr_enum_v(u32 r)
144{
145 return (r >> 15U) & 0x1fU;
146}
147static inline u32 top_device_info_reset_enum_v(u32 r)
148{
149 return (r >> 9U) & 0x1fU;
150}
151static inline u32 top_device_info_type_enum_v(u32 r)
152{
153 return (r >> 2U) & 0x1fffffffU;
154}
155static inline u32 top_device_info_type_enum_graphics_v(void)
156{
157 return 0x00000000U;
158}
159static inline u32 top_device_info_type_enum_graphics_f(void)
160{
161 return 0x0U;
162}
163static inline u32 top_device_info_type_enum_copy2_v(void)
164{
165 return 0x00000003U;
166}
167static inline u32 top_device_info_type_enum_copy2_f(void)
168{
169 return 0xcU;
170}
171static inline u32 top_device_info_type_enum_lce_v(void)
172{
173 return 0x00000013U;
174}
175static inline u32 top_device_info_type_enum_lce_f(void)
176{
177 return 0x4cU;
178}
179static inline u32 top_device_info_type_enum_ioctrl_v(void)
180{
181 return 0x00000012U;
182}
183static inline u32 top_device_info_type_enum_ioctrl_f(void)
184{
185 return 0x48U;
186}
187static inline u32 top_device_info_engine_v(u32 r)
188{
189 return (r >> 5U) & 0x1U;
190}
191static inline u32 top_device_info_runlist_v(u32 r)
192{
193 return (r >> 4U) & 0x1U;
194}
195static inline u32 top_device_info_intr_v(u32 r)
196{
197 return (r >> 3U) & 0x1U;
198}
199static inline u32 top_device_info_reset_v(u32 r)
200{
201 return (r >> 2U) & 0x1U;
202}
203static inline u32 top_device_info_entry_v(u32 r)
204{
205 return (r >> 0U) & 0x3U;
206}
207static inline u32 top_device_info_entry_not_valid_v(void)
208{
209 return 0x00000000U;
210}
211static inline u32 top_device_info_entry_enum_v(void)
212{
213 return 0x00000002U;
214}
215static inline u32 top_device_info_entry_data_v(void)
216{
217 return 0x00000001U;
218}
219static inline u32 top_device_info_entry_engine_type_v(void)
220{
221 return 0x00000003U;
222}
223static inline u32 top_device_info_data_type_v(u32 r)
224{
225 return (r >> 30U) & 0x1U;
226}
227static inline u32 top_device_info_data_type_enum2_v(void)
228{
229 return 0x00000000U;
230}
231static inline u32 top_device_info_data_inst_id_v(u32 r)
232{
233 return (r >> 26U) & 0xfU;
234}
235static inline u32 top_device_info_data_pri_base_v(u32 r)
236{
237 return (r >> 12U) & 0xfffU;
238}
239static inline u32 top_device_info_data_pri_base_align_v(void)
240{
241 return 0x0000000cU;
242}
243static inline u32 top_device_info_data_fault_id_enum_v(u32 r)
244{
245 return (r >> 3U) & 0x7fU;
246}
247static inline u32 top_device_info_data_fault_id_v(u32 r)
248{
249 return (r >> 2U) & 0x1U;
250}
251static inline u32 top_device_info_data_fault_id_valid_v(void)
252{
253 return 0x00000001U;
254}
255static inline u32 top_nvhsclk_ctrl_r(void)
256{
257 return 0x00022424U;
258}
259static inline u32 top_nvhsclk_ctrl_e_clk_nvl_f(u32 v)
260{
261 return (v & 0x7U) << 0U;
262}
263static inline u32 top_nvhsclk_ctrl_e_clk_nvl_m(void)
264{
265 return 0x7U << 0U;
266}
267static inline u32 top_nvhsclk_ctrl_e_clk_nvl_v(u32 r)
268{
269 return (r >> 0U) & 0x7U;
270}
271static inline u32 top_nvhsclk_ctrl_e_clk_pcie_f(u32 v)
272{
273 return (v & 0x1U) << 3U;
274}
275static inline u32 top_nvhsclk_ctrl_e_clk_pcie_m(void)
276{
277 return 0x1U << 3U;
278}
279static inline u32 top_nvhsclk_ctrl_e_clk_pcie_v(u32 r)
280{
281 return (r >> 3U) & 0x1U;
282}
283static inline u32 top_nvhsclk_ctrl_e_clk_core_f(u32 v)
284{
285 return (v & 0x1U) << 4U;
286}
287static inline u32 top_nvhsclk_ctrl_e_clk_core_m(void)
288{
289 return 0x1U << 4U;
290}
291static inline u32 top_nvhsclk_ctrl_e_clk_core_v(u32 r)
292{
293 return (r >> 4U) & 0x1U;
294}
295static inline u32 top_nvhsclk_ctrl_rfu_f(u32 v)
296{
297 return (v & 0xfU) << 5U;
298}
299static inline u32 top_nvhsclk_ctrl_rfu_m(void)
300{
301 return 0xfU << 5U;
302}
303static inline u32 top_nvhsclk_ctrl_rfu_v(u32 r)
304{
305 return (r >> 5U) & 0xfU;
306}
307static inline u32 top_nvhsclk_ctrl_swap_clk_nvl_f(u32 v)
308{
309 return (v & 0x7U) << 10U;
310}
311static inline u32 top_nvhsclk_ctrl_swap_clk_nvl_m(void)
312{
313 return 0x7U << 10U;
314}
315static inline u32 top_nvhsclk_ctrl_swap_clk_nvl_v(u32 r)
316{
317 return (r >> 10U) & 0x7U;
318}
319static inline u32 top_nvhsclk_ctrl_swap_clk_pcie_f(u32 v)
320{
321 return (v & 0x1U) << 9U;
322}
323static inline u32 top_nvhsclk_ctrl_swap_clk_pcie_m(void)
324{
325 return 0x1U << 9U;
326}
327static inline u32 top_nvhsclk_ctrl_swap_clk_pcie_v(u32 r)
328{
329 return (r >> 9U) & 0x1U;
330}
331static inline u32 top_nvhsclk_ctrl_swap_clk_core_f(u32 v)
332{
333 return (v & 0x1U) << 13U;
334}
335static inline u32 top_nvhsclk_ctrl_swap_clk_core_m(void)
336{
337 return 0x1U << 13U;
338}
339static inline u32 top_nvhsclk_ctrl_swap_clk_core_v(u32 r)
340{
341 return (r >> 13U) & 0x1U;
342}
343#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-30 08:19:15 -0400