aboutsummaryrefslogtreecommitdiffstats
path: root/include/nvgpu/hw/gp106/hw_xve_gp106.h
diff options
context:
space:
mode:
Diffstat (limited to 'include/nvgpu/hw/gp106/hw_xve_gp106.h')
-rw-r--r--include/nvgpu/hw/gp106/hw_xve_gp106.h207
1 files changed, 207 insertions, 0 deletions
diff --git a/include/nvgpu/hw/gp106/hw_xve_gp106.h b/include/nvgpu/hw/gp106/hw_xve_gp106.h
new file mode 100644
index 0000000..e61d13f
--- /dev/null
+++ b/include/nvgpu/hw/gp106/hw_xve_gp106.h
@@ -0,0 +1,207 @@
1/*
2 * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22/*
23 * Function naming determines intended use:
24 *
25 * <x>_r(void) : Returns the offset for register <x>.
26 *
27 * <x>_o(void) : Returns the offset for element <x>.
28 *
29 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
30 *
31 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
32 *
33 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
34 * and masked to place it at field <y> of register <x>. This value
35 * can be |'d with others to produce a full register value for
36 * register <x>.
37 *
38 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
39 * value can be ~'d and then &'d to clear the value of field <y> for
40 * register <x>.
41 *
42 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
43 * to place it at field <y> of register <x>. This value can be |'d
44 * with others to produce a full register value for <x>.
45 *
46 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
47 * <x> value 'r' after being shifted to place its LSB at bit 0.
48 * This value is suitable for direct comparison with other unshifted
49 * values appropriate for use in field <y> of register <x>.
50 *
51 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
52 * field <y> of register <x>. This value is suitable for direct
53 * comparison with unshifted values appropriate for use in field <y>
54 * of register <x>.
55 */
56#ifndef _hw_xve_gp106_h_
57#define _hw_xve_gp106_h_
58
59static inline u32 xve_rom_ctrl_r(void)
60{
61 return 0x00000050U;
62}
63static inline u32 xve_rom_ctrl_rom_shadow_f(u32 v)
64{
65 return (v & 0x1U) << 0U;
66}
67static inline u32 xve_rom_ctrl_rom_shadow_disabled_f(void)
68{
69 return 0x0U;
70}
71static inline u32 xve_rom_ctrl_rom_shadow_enabled_f(void)
72{
73 return 0x1U;
74}
75static inline u32 xve_link_control_status_r(void)
76{
77 return 0x00000088U;
78}
79static inline u32 xve_link_control_status_link_speed_m(void)
80{
81 return 0xfU << 16U;
82}
83static inline u32 xve_link_control_status_link_speed_v(u32 r)
84{
85 return (r >> 16U) & 0xfU;
86}
87static inline u32 xve_link_control_status_link_speed_link_speed_2p5_v(void)
88{
89 return 0x00000001U;
90}
91static inline u32 xve_link_control_status_link_speed_link_speed_5p0_v(void)
92{
93 return 0x00000002U;
94}
95static inline u32 xve_link_control_status_link_speed_link_speed_8p0_v(void)
96{
97 return 0x00000003U;
98}
99static inline u32 xve_link_control_status_link_width_m(void)
100{
101 return 0x3fU << 20U;
102}
103static inline u32 xve_link_control_status_link_width_v(u32 r)
104{
105 return (r >> 20U) & 0x3fU;
106}
107static inline u32 xve_link_control_status_link_width_x1_v(void)
108{
109 return 0x00000001U;
110}
111static inline u32 xve_link_control_status_link_width_x2_v(void)
112{
113 return 0x00000002U;
114}
115static inline u32 xve_link_control_status_link_width_x4_v(void)
116{
117 return 0x00000004U;
118}
119static inline u32 xve_link_control_status_link_width_x8_v(void)
120{
121 return 0x00000008U;
122}
123static inline u32 xve_link_control_status_link_width_x16_v(void)
124{
125 return 0x00000010U;
126}
127static inline u32 xve_priv_xv_r(void)
128{
129 return 0x00000150U;
130}
131static inline u32 xve_priv_xv_cya_l0s_enable_f(u32 v)
132{
133 return (v & 0x1U) << 7U;
134}
135static inline u32 xve_priv_xv_cya_l0s_enable_m(void)
136{
137 return 0x1U << 7U;
138}
139static inline u32 xve_priv_xv_cya_l0s_enable_v(u32 r)
140{
141 return (r >> 7U) & 0x1U;
142}
143static inline u32 xve_priv_xv_cya_l1_enable_f(u32 v)
144{
145 return (v & 0x1U) << 8U;
146}
147static inline u32 xve_priv_xv_cya_l1_enable_m(void)
148{
149 return 0x1U << 8U;
150}
151static inline u32 xve_priv_xv_cya_l1_enable_v(u32 r)
152{
153 return (r >> 8U) & 0x1U;
154}
155static inline u32 xve_cya_2_r(void)
156{
157 return 0x00000704U;
158}
159static inline u32 xve_reset_r(void)
160{
161 return 0x00000718U;
162}
163static inline u32 xve_reset_reset_m(void)
164{
165 return 0x1U << 0U;
166}
167static inline u32 xve_reset_gpu_on_sw_reset_m(void)
168{
169 return 0x1U << 1U;
170}
171static inline u32 xve_reset_counter_en_m(void)
172{
173 return 0x1U << 2U;
174}
175static inline u32 xve_reset_counter_val_f(u32 v)
176{
177 return (v & 0x7ffU) << 4U;
178}
179static inline u32 xve_reset_counter_val_m(void)
180{
181 return 0x7ffU << 4U;
182}
183static inline u32 xve_reset_counter_val_v(u32 r)
184{
185 return (r >> 4U) & 0x7ffU;
186}
187static inline u32 xve_reset_clock_on_sw_reset_m(void)
188{
189 return 0x1U << 15U;
190}
191static inline u32 xve_reset_clock_counter_en_m(void)
192{
193 return 0x1U << 16U;
194}
195static inline u32 xve_reset_clock_counter_val_f(u32 v)
196{
197 return (v & 0x7ffU) << 17U;
198}
199static inline u32 xve_reset_clock_counter_val_m(void)
200{
201 return 0x7ffU << 17U;
202}
203static inline u32 xve_reset_clock_counter_val_v(u32 r)
204{
205 return (r >> 17U) & 0x7ffU;
206}
207#endif