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-rw-r--r--include/nvgpu/hw/gp106/hw_pwr_gp106.h895
1 files changed, 0 insertions, 895 deletions
diff --git a/include/nvgpu/hw/gp106/hw_pwr_gp106.h b/include/nvgpu/hw/gp106/hw_pwr_gp106.h
deleted file mode 100644
index 2e75fa6..0000000
--- a/include/nvgpu/hw/gp106/hw_pwr_gp106.h
+++ /dev/null
@@ -1,895 +0,0 @@
1/*
2 * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22/*
23 * Function naming determines intended use:
24 *
25 * <x>_r(void) : Returns the offset for register <x>.
26 *
27 * <x>_o(void) : Returns the offset for element <x>.
28 *
29 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
30 *
31 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
32 *
33 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
34 * and masked to place it at field <y> of register <x>. This value
35 * can be |'d with others to produce a full register value for
36 * register <x>.
37 *
38 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
39 * value can be ~'d and then &'d to clear the value of field <y> for
40 * register <x>.
41 *
42 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
43 * to place it at field <y> of register <x>. This value can be |'d
44 * with others to produce a full register value for <x>.
45 *
46 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
47 * <x> value 'r' after being shifted to place its LSB at bit 0.
48 * This value is suitable for direct comparison with other unshifted
49 * values appropriate for use in field <y> of register <x>.
50 *
51 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
52 * field <y> of register <x>. This value is suitable for direct
53 * comparison with unshifted values appropriate for use in field <y>
54 * of register <x>.
55 */
56#ifndef _hw_pwr_gp106_h_
57#define _hw_pwr_gp106_h_
58
59static inline u32 pwr_falcon_irqsset_r(void)
60{
61 return 0x0010a000U;
62}
63static inline u32 pwr_falcon_irqsset_swgen0_set_f(void)
64{
65 return 0x40U;
66}
67static inline u32 pwr_falcon_irqsclr_r(void)
68{
69 return 0x0010a004U;
70}
71static inline u32 pwr_falcon_irqstat_r(void)
72{
73 return 0x0010a008U;
74}
75static inline u32 pwr_falcon_irqstat_halt_true_f(void)
76{
77 return 0x10U;
78}
79static inline u32 pwr_falcon_irqstat_exterr_true_f(void)
80{
81 return 0x20U;
82}
83static inline u32 pwr_falcon_irqstat_swgen0_true_f(void)
84{
85 return 0x40U;
86}
87static inline u32 pwr_falcon_irqmode_r(void)
88{
89 return 0x0010a00cU;
90}
91static inline u32 pwr_falcon_irqmset_r(void)
92{
93 return 0x0010a010U;
94}
95static inline u32 pwr_falcon_irqmset_gptmr_f(u32 v)
96{
97 return (v & 0x1U) << 0U;
98}
99static inline u32 pwr_falcon_irqmset_wdtmr_f(u32 v)
100{
101 return (v & 0x1U) << 1U;
102}
103static inline u32 pwr_falcon_irqmset_mthd_f(u32 v)
104{
105 return (v & 0x1U) << 2U;
106}
107static inline u32 pwr_falcon_irqmset_ctxsw_f(u32 v)
108{
109 return (v & 0x1U) << 3U;
110}
111static inline u32 pwr_falcon_irqmset_halt_f(u32 v)
112{
113 return (v & 0x1U) << 4U;
114}
115static inline u32 pwr_falcon_irqmset_exterr_f(u32 v)
116{
117 return (v & 0x1U) << 5U;
118}
119static inline u32 pwr_falcon_irqmset_swgen0_f(u32 v)
120{
121 return (v & 0x1U) << 6U;
122}
123static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v)
124{
125 return (v & 0x1U) << 7U;
126}
127static inline u32 pwr_falcon_irqmclr_r(void)
128{
129 return 0x0010a014U;
130}
131static inline u32 pwr_falcon_irqmclr_gptmr_f(u32 v)
132{
133 return (v & 0x1U) << 0U;
134}
135static inline u32 pwr_falcon_irqmclr_wdtmr_f(u32 v)
136{
137 return (v & 0x1U) << 1U;
138}
139static inline u32 pwr_falcon_irqmclr_mthd_f(u32 v)
140{
141 return (v & 0x1U) << 2U;
142}
143static inline u32 pwr_falcon_irqmclr_ctxsw_f(u32 v)
144{
145 return (v & 0x1U) << 3U;
146}
147static inline u32 pwr_falcon_irqmclr_halt_f(u32 v)
148{
149 return (v & 0x1U) << 4U;
150}
151static inline u32 pwr_falcon_irqmclr_exterr_f(u32 v)
152{
153 return (v & 0x1U) << 5U;
154}
155static inline u32 pwr_falcon_irqmclr_swgen0_f(u32 v)
156{
157 return (v & 0x1U) << 6U;
158}
159static inline u32 pwr_falcon_irqmclr_swgen1_f(u32 v)
160{
161 return (v & 0x1U) << 7U;
162}
163static inline u32 pwr_falcon_irqmclr_ext_f(u32 v)
164{
165 return (v & 0xffU) << 8U;
166}
167static inline u32 pwr_falcon_irqmask_r(void)
168{
169 return 0x0010a018U;
170}
171static inline u32 pwr_falcon_irqdest_r(void)
172{
173 return 0x0010a01cU;
174}
175static inline u32 pwr_falcon_irqdest_host_gptmr_f(u32 v)
176{
177 return (v & 0x1U) << 0U;
178}
179static inline u32 pwr_falcon_irqdest_host_wdtmr_f(u32 v)
180{
181 return (v & 0x1U) << 1U;
182}
183static inline u32 pwr_falcon_irqdest_host_mthd_f(u32 v)
184{
185 return (v & 0x1U) << 2U;
186}
187static inline u32 pwr_falcon_irqdest_host_ctxsw_f(u32 v)
188{
189 return (v & 0x1U) << 3U;
190}
191static inline u32 pwr_falcon_irqdest_host_halt_f(u32 v)
192{
193 return (v & 0x1U) << 4U;
194}
195static inline u32 pwr_falcon_irqdest_host_exterr_f(u32 v)
196{
197 return (v & 0x1U) << 5U;
198}
199static inline u32 pwr_falcon_irqdest_host_swgen0_f(u32 v)
200{
201 return (v & 0x1U) << 6U;
202}
203static inline u32 pwr_falcon_irqdest_host_swgen1_f(u32 v)
204{
205 return (v & 0x1U) << 7U;
206}
207static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v)
208{
209 return (v & 0xffU) << 8U;
210}
211static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v)
212{
213 return (v & 0x1U) << 16U;
214}
215static inline u32 pwr_falcon_irqdest_target_wdtmr_f(u32 v)
216{
217 return (v & 0x1U) << 17U;
218}
219static inline u32 pwr_falcon_irqdest_target_mthd_f(u32 v)
220{
221 return (v & 0x1U) << 18U;
222}
223static inline u32 pwr_falcon_irqdest_target_ctxsw_f(u32 v)
224{
225 return (v & 0x1U) << 19U;
226}
227static inline u32 pwr_falcon_irqdest_target_halt_f(u32 v)
228{
229 return (v & 0x1U) << 20U;
230}
231static inline u32 pwr_falcon_irqdest_target_exterr_f(u32 v)
232{
233 return (v & 0x1U) << 21U;
234}
235static inline u32 pwr_falcon_irqdest_target_swgen0_f(u32 v)
236{
237 return (v & 0x1U) << 22U;
238}
239static inline u32 pwr_falcon_irqdest_target_swgen1_f(u32 v)
240{
241 return (v & 0x1U) << 23U;
242}
243static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v)
244{
245 return (v & 0xffU) << 24U;
246}
247static inline u32 pwr_falcon_curctx_r(void)
248{
249 return 0x0010a050U;
250}
251static inline u32 pwr_falcon_nxtctx_r(void)
252{
253 return 0x0010a054U;
254}
255static inline u32 pwr_falcon_mailbox0_r(void)
256{
257 return 0x0010a040U;
258}
259static inline u32 pwr_falcon_mailbox1_r(void)
260{
261 return 0x0010a044U;
262}
263static inline u32 pwr_falcon_itfen_r(void)
264{
265 return 0x0010a048U;
266}
267static inline u32 pwr_falcon_itfen_ctxen_enable_f(void)
268{
269 return 0x1U;
270}
271static inline u32 pwr_falcon_idlestate_r(void)
272{
273 return 0x0010a04cU;
274}
275static inline u32 pwr_falcon_idlestate_falcon_busy_v(u32 r)
276{
277 return (r >> 0U) & 0x1U;
278}
279static inline u32 pwr_falcon_idlestate_ext_busy_v(u32 r)
280{
281 return (r >> 1U) & 0x7fffU;
282}
283static inline u32 pwr_falcon_os_r(void)
284{
285 return 0x0010a080U;
286}
287static inline u32 pwr_falcon_engctl_r(void)
288{
289 return 0x0010a0a4U;
290}
291static inline u32 pwr_falcon_cpuctl_r(void)
292{
293 return 0x0010a100U;
294}
295static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v)
296{
297 return (v & 0x1U) << 1U;
298}
299static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v)
300{
301 return (v & 0x1U) << 4U;
302}
303static inline u32 pwr_falcon_cpuctl_halt_intr_m(void)
304{
305 return 0x1U << 4U;
306}
307static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r)
308{
309 return (r >> 4U) & 0x1U;
310}
311static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_f(u32 v)
312{
313 return (v & 0x1U) << 6U;
314}
315static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_m(void)
316{
317 return 0x1U << 6U;
318}
319static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_v(u32 r)
320{
321 return (r >> 6U) & 0x1U;
322}
323static inline u32 pwr_falcon_cpuctl_alias_r(void)
324{
325 return 0x0010a130U;
326}
327static inline u32 pwr_falcon_cpuctl_alias_startcpu_f(u32 v)
328{
329 return (v & 0x1U) << 1U;
330}
331static inline u32 pwr_pmu_scpctl_stat_r(void)
332{
333 return 0x0010ac08U;
334}
335static inline u32 pwr_pmu_scpctl_stat_debug_mode_f(u32 v)
336{
337 return (v & 0x1U) << 20U;
338}
339static inline u32 pwr_pmu_scpctl_stat_debug_mode_m(void)
340{
341 return 0x1U << 20U;
342}
343static inline u32 pwr_pmu_scpctl_stat_debug_mode_v(u32 r)
344{
345 return (r >> 20U) & 0x1U;
346}
347static inline u32 pwr_falcon_imemc_r(u32 i)
348{
349 return 0x0010a180U + i*16U;
350}
351static inline u32 pwr_falcon_imemc_offs_f(u32 v)
352{
353 return (v & 0x3fU) << 2U;
354}
355static inline u32 pwr_falcon_imemc_blk_f(u32 v)
356{
357 return (v & 0xffU) << 8U;
358}
359static inline u32 pwr_falcon_imemc_aincw_f(u32 v)
360{
361 return (v & 0x1U) << 24U;
362}
363static inline u32 pwr_falcon_imemd_r(u32 i)
364{
365 return 0x0010a184U + i*16U;
366}
367static inline u32 pwr_falcon_imemt_r(u32 i)
368{
369 return 0x0010a188U + i*16U;
370}
371static inline u32 pwr_falcon_sctl_r(void)
372{
373 return 0x0010a240U;
374}
375static inline u32 pwr_falcon_mmu_phys_sec_r(void)
376{
377 return 0x00100ce4U;
378}
379static inline u32 pwr_falcon_bootvec_r(void)
380{
381 return 0x0010a104U;
382}
383static inline u32 pwr_falcon_bootvec_vec_f(u32 v)
384{
385 return (v & 0xffffffffU) << 0U;
386}
387static inline u32 pwr_falcon_dmactl_r(void)
388{
389 return 0x0010a10cU;
390}
391static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void)
392{
393 return 0x1U << 1U;
394}
395static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void)
396{
397 return 0x1U << 2U;
398}
399static inline u32 pwr_falcon_dmactl_require_ctx_f(u32 v)
400{
401 return (v & 0x1U) << 0U;
402}
403static inline u32 pwr_falcon_hwcfg_r(void)
404{
405 return 0x0010a108U;
406}
407static inline u32 pwr_falcon_hwcfg_imem_size_v(u32 r)
408{
409 return (r >> 0U) & 0x1ffU;
410}
411static inline u32 pwr_falcon_hwcfg_dmem_size_v(u32 r)
412{
413 return (r >> 9U) & 0x1ffU;
414}
415static inline u32 pwr_falcon_dmatrfbase_r(void)
416{
417 return 0x0010a110U;
418}
419static inline u32 pwr_falcon_dmatrfbase1_r(void)
420{
421 return 0x0010a128U;
422}
423static inline u32 pwr_falcon_dmatrfmoffs_r(void)
424{
425 return 0x0010a114U;
426}
427static inline u32 pwr_falcon_dmatrfcmd_r(void)
428{
429 return 0x0010a118U;
430}
431static inline u32 pwr_falcon_dmatrfcmd_imem_f(u32 v)
432{
433 return (v & 0x1U) << 4U;
434}
435static inline u32 pwr_falcon_dmatrfcmd_write_f(u32 v)
436{
437 return (v & 0x1U) << 5U;
438}
439static inline u32 pwr_falcon_dmatrfcmd_size_f(u32 v)
440{
441 return (v & 0x7U) << 8U;
442}
443static inline u32 pwr_falcon_dmatrfcmd_ctxdma_f(u32 v)
444{
445 return (v & 0x7U) << 12U;
446}
447static inline u32 pwr_falcon_dmatrffboffs_r(void)
448{
449 return 0x0010a11cU;
450}
451static inline u32 pwr_falcon_exterraddr_r(void)
452{
453 return 0x0010a168U;
454}
455static inline u32 pwr_falcon_exterrstat_r(void)
456{
457 return 0x0010a16cU;
458}
459static inline u32 pwr_falcon_exterrstat_valid_m(void)
460{
461 return 0x1U << 31U;
462}
463static inline u32 pwr_falcon_exterrstat_valid_v(u32 r)
464{
465 return (r >> 31U) & 0x1U;
466}
467static inline u32 pwr_falcon_exterrstat_valid_true_v(void)
468{
469 return 0x00000001U;
470}
471static inline u32 pwr_pmu_falcon_icd_cmd_r(void)
472{
473 return 0x0010a200U;
474}
475static inline u32 pwr_pmu_falcon_icd_cmd_opc_s(void)
476{
477 return 4U;
478}
479static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v)
480{
481 return (v & 0xfU) << 0U;
482}
483static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void)
484{
485 return 0xfU << 0U;
486}
487static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r)
488{
489 return (r >> 0U) & 0xfU;
490}
491static inline u32 pwr_pmu_falcon_icd_cmd_opc_rreg_f(void)
492{
493 return 0x8U;
494}
495static inline u32 pwr_pmu_falcon_icd_cmd_opc_rstat_f(void)
496{
497 return 0xeU;
498}
499static inline u32 pwr_pmu_falcon_icd_cmd_idx_f(u32 v)
500{
501 return (v & 0x1fU) << 8U;
502}
503static inline u32 pwr_pmu_falcon_icd_rdata_r(void)
504{
505 return 0x0010a20cU;
506}
507static inline u32 pwr_falcon_dmemc_r(u32 i)
508{
509 return 0x0010a1c0U + i*8U;
510}
511static inline u32 pwr_falcon_dmemc_offs_f(u32 v)
512{
513 return (v & 0x3fU) << 2U;
514}
515static inline u32 pwr_falcon_dmemc_offs_m(void)
516{
517 return 0x3fU << 2U;
518}
519static inline u32 pwr_falcon_dmemc_blk_f(u32 v)
520{
521 return (v & 0xffU) << 8U;
522}
523static inline u32 pwr_falcon_dmemc_blk_m(void)
524{
525 return 0xffU << 8U;
526}
527static inline u32 pwr_falcon_dmemc_aincw_f(u32 v)
528{
529 return (v & 0x1U) << 24U;
530}
531static inline u32 pwr_falcon_dmemc_aincr_f(u32 v)
532{
533 return (v & 0x1U) << 25U;
534}
535static inline u32 pwr_falcon_dmemd_r(u32 i)
536{
537 return 0x0010a1c4U + i*8U;
538}
539static inline u32 pwr_pmu_new_instblk_r(void)
540{
541 return 0x0010a480U;
542}
543static inline u32 pwr_pmu_new_instblk_ptr_f(u32 v)
544{
545 return (v & 0xfffffffU) << 0U;
546}
547static inline u32 pwr_pmu_new_instblk_target_fb_f(void)
548{
549 return 0x0U;
550}
551static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void)
552{
553 return 0x20000000U;
554}
555static inline u32 pwr_pmu_new_instblk_target_sys_ncoh_f(void)
556{
557 return 0x30000000U;
558}
559static inline u32 pwr_pmu_new_instblk_valid_f(u32 v)
560{
561 return (v & 0x1U) << 30U;
562}
563static inline u32 pwr_pmu_mutex_id_r(void)
564{
565 return 0x0010a488U;
566}
567static inline u32 pwr_pmu_mutex_id_value_v(u32 r)
568{
569 return (r >> 0U) & 0xffU;
570}
571static inline u32 pwr_pmu_mutex_id_value_init_v(void)
572{
573 return 0x00000000U;
574}
575static inline u32 pwr_pmu_mutex_id_value_not_avail_v(void)
576{
577 return 0x000000ffU;
578}
579static inline u32 pwr_pmu_mutex_id_release_r(void)
580{
581 return 0x0010a48cU;
582}
583static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v)
584{
585 return (v & 0xffU) << 0U;
586}
587static inline u32 pwr_pmu_mutex_id_release_value_m(void)
588{
589 return 0xffU << 0U;
590}
591static inline u32 pwr_pmu_mutex_id_release_value_init_v(void)
592{
593 return 0x00000000U;
594}
595static inline u32 pwr_pmu_mutex_id_release_value_init_f(void)
596{
597 return 0x0U;
598}
599static inline u32 pwr_pmu_mutex_r(u32 i)
600{
601 return 0x0010a580U + i*4U;
602}
603static inline u32 pwr_pmu_mutex__size_1_v(void)
604{
605 return 0x00000010U;
606}
607static inline u32 pwr_pmu_mutex_value_f(u32 v)
608{
609 return (v & 0xffU) << 0U;
610}
611static inline u32 pwr_pmu_mutex_value_v(u32 r)
612{
613 return (r >> 0U) & 0xffU;
614}
615static inline u32 pwr_pmu_mutex_value_initial_lock_f(void)
616{
617 return 0x0U;
618}
619static inline u32 pwr_pmu_queue_head_r(u32 i)
620{
621 return 0x0010a4a0U + i*4U;
622}
623static inline u32 pwr_pmu_queue_head__size_1_v(void)
624{
625 return 0x00000004U;
626}
627static inline u32 pwr_pmu_queue_head_address_f(u32 v)
628{
629 return (v & 0xffffffffU) << 0U;
630}
631static inline u32 pwr_pmu_queue_head_address_v(u32 r)
632{
633 return (r >> 0U) & 0xffffffffU;
634}
635static inline u32 pwr_pmu_queue_tail_r(u32 i)
636{
637 return 0x0010a4b0U + i*4U;
638}
639static inline u32 pwr_pmu_queue_tail__size_1_v(void)
640{
641 return 0x00000004U;
642}
643static inline u32 pwr_pmu_queue_tail_address_f(u32 v)
644{
645 return (v & 0xffffffffU) << 0U;
646}
647static inline u32 pwr_pmu_queue_tail_address_v(u32 r)
648{
649 return (r >> 0U) & 0xffffffffU;
650}
651static inline u32 pwr_pmu_msgq_head_r(void)
652{
653 return 0x0010a4c8U;
654}
655static inline u32 pwr_pmu_msgq_head_val_f(u32 v)
656{
657 return (v & 0xffffffffU) << 0U;
658}
659static inline u32 pwr_pmu_msgq_head_val_v(u32 r)
660{
661 return (r >> 0U) & 0xffffffffU;
662}
663static inline u32 pwr_pmu_msgq_tail_r(void)
664{
665 return 0x0010a4ccU;
666}
667static inline u32 pwr_pmu_msgq_tail_val_f(u32 v)
668{
669 return (v & 0xffffffffU) << 0U;
670}
671static inline u32 pwr_pmu_msgq_tail_val_v(u32 r)
672{
673 return (r >> 0U) & 0xffffffffU;
674}
675static inline u32 pwr_pmu_idle_mask_r(u32 i)
676{
677 return 0x0010a504U + i*16U;
678}
679static inline u32 pwr_pmu_idle_mask_gr_enabled_f(void)
680{
681 return 0x1U;
682}
683static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void)
684{
685 return 0x200000U;
686}
687static inline u32 pwr_pmu_idle_count_r(u32 i)
688{
689 return 0x0010a508U + i*16U;
690}
691static inline u32 pwr_pmu_idle_count_value_f(u32 v)
692{
693 return (v & 0x7fffffffU) << 0U;
694}
695static inline u32 pwr_pmu_idle_count_value_v(u32 r)
696{
697 return (r >> 0U) & 0x7fffffffU;
698}
699static inline u32 pwr_pmu_idle_count_reset_f(u32 v)
700{
701 return (v & 0x1U) << 31U;
702}
703static inline u32 pwr_pmu_idle_ctrl_r(u32 i)
704{
705 return 0x0010a50cU + i*16U;
706}
707static inline u32 pwr_pmu_idle_ctrl_value_m(void)
708{
709 return 0x3U << 0U;
710}
711static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void)
712{
713 return 0x2U;
714}
715static inline u32 pwr_pmu_idle_ctrl_value_always_f(void)
716{
717 return 0x3U;
718}
719static inline u32 pwr_pmu_idle_ctrl_filter_m(void)
720{
721 return 0x1U << 2U;
722}
723static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void)
724{
725 return 0x0U;
726}
727static inline u32 pwr_pmu_idle_threshold_r(u32 i)
728{
729 return 0x0010a8a0U + i*4U;
730}
731static inline u32 pwr_pmu_idle_threshold_value_f(u32 v)
732{
733 return (v & 0x7fffffffU) << 0U;
734}
735static inline u32 pwr_pmu_idle_intr_r(void)
736{
737 return 0x0010a9e8U;
738}
739static inline u32 pwr_pmu_idle_intr_en_f(u32 v)
740{
741 return (v & 0x1U) << 0U;
742}
743static inline u32 pwr_pmu_idle_intr_en_disabled_v(void)
744{
745 return 0x00000000U;
746}
747static inline u32 pwr_pmu_idle_intr_en_enabled_v(void)
748{
749 return 0x00000001U;
750}
751static inline u32 pwr_pmu_idle_intr_status_r(void)
752{
753 return 0x0010a9ecU;
754}
755static inline u32 pwr_pmu_idle_intr_status_intr_f(u32 v)
756{
757 return (v & 0x1U) << 0U;
758}
759static inline u32 pwr_pmu_idle_intr_status_intr_m(void)
760{
761 return U32(0x1U) << 0U;
762}
763static inline u32 pwr_pmu_idle_intr_status_intr_v(u32 r)
764{
765 return (r >> 0U) & 0x1U;
766}
767static inline u32 pwr_pmu_idle_intr_status_intr_pending_v(void)
768{
769 return 0x00000001U;
770}
771static inline u32 pwr_pmu_idle_intr_status_intr_clear_v(void)
772{
773 return 0x00000001U;
774}
775static inline u32 pwr_pmu_idle_mask_supp_r(u32 i)
776{
777 return 0x0010a9f0U + i*8U;
778}
779static inline u32 pwr_pmu_idle_mask_1_supp_r(u32 i)
780{
781 return 0x0010a9f4U + i*8U;
782}
783static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i)
784{
785 return 0x0010aa30U + i*8U;
786}
787static inline u32 pwr_pmu_debug_r(u32 i)
788{
789 return 0x0010a5c0U + i*4U;
790}
791static inline u32 pwr_pmu_debug__size_1_v(void)
792{
793 return 0x00000004U;
794}
795static inline u32 pwr_pmu_mailbox_r(u32 i)
796{
797 return 0x0010a450U + i*4U;
798}
799static inline u32 pwr_pmu_mailbox__size_1_v(void)
800{
801 return 0x0000000cU;
802}
803static inline u32 pwr_pmu_bar0_addr_r(void)
804{
805 return 0x0010a7a0U;
806}
807static inline u32 pwr_pmu_bar0_data_r(void)
808{
809 return 0x0010a7a4U;
810}
811static inline u32 pwr_pmu_bar0_ctl_r(void)
812{
813 return 0x0010a7acU;
814}
815static inline u32 pwr_pmu_bar0_timeout_r(void)
816{
817 return 0x0010a7a8U;
818}
819static inline u32 pwr_pmu_bar0_fecs_error_r(void)
820{
821 return 0x0010a988U;
822}
823static inline u32 pwr_pmu_bar0_error_status_r(void)
824{
825 return 0x0010a7b0U;
826}
827static inline u32 pwr_pmu_pg_idlefilth_r(u32 i)
828{
829 return 0x0010a6c0U + i*4U;
830}
831static inline u32 pwr_pmu_pg_ppuidlefilth_r(u32 i)
832{
833 return 0x0010a6e8U + i*4U;
834}
835static inline u32 pwr_pmu_pg_idle_cnt_r(u32 i)
836{
837 return 0x0010a710U + i*4U;
838}
839static inline u32 pwr_pmu_pg_intren_r(u32 i)
840{
841 return 0x0010a760U + i*4U;
842}
843static inline u32 pwr_fbif_transcfg_r(u32 i)
844{
845 return 0x0010ae00U + i*4U;
846}
847static inline u32 pwr_fbif_transcfg_target_local_fb_f(void)
848{
849 return 0x0U;
850}
851static inline u32 pwr_fbif_transcfg_target_coherent_sysmem_f(void)
852{
853 return 0x1U;
854}
855static inline u32 pwr_fbif_transcfg_target_noncoherent_sysmem_f(void)
856{
857 return 0x2U;
858}
859static inline u32 pwr_fbif_transcfg_mem_type_s(void)
860{
861 return 1U;
862}
863static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v)
864{
865 return (v & 0x1U) << 2U;
866}
867static inline u32 pwr_fbif_transcfg_mem_type_m(void)
868{
869 return 0x1U << 2U;
870}
871static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r)
872{
873 return (r >> 2U) & 0x1U;
874}
875static inline u32 pwr_fbif_transcfg_mem_type_virtual_f(void)
876{
877 return 0x0U;
878}
879static inline u32 pwr_fbif_transcfg_mem_type_physical_f(void)
880{
881 return 0x4U;
882}
883static inline u32 pwr_falcon_engine_r(void)
884{
885 return 0x0010a3c0U;
886}
887static inline u32 pwr_falcon_engine_reset_true_f(void)
888{
889 return 0x1U;
890}
891static inline u32 pwr_falcon_engine_reset_false_f(void)
892{
893 return 0x0U;
894}
895#endif
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