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-rw-r--r--include/nvgpu/hw/gm20b/hw_trim_gm20b.h503
1 files changed, 0 insertions, 503 deletions
diff --git a/include/nvgpu/hw/gm20b/hw_trim_gm20b.h b/include/nvgpu/hw/gm20b/hw_trim_gm20b.h
deleted file mode 100644
index 8f0a77a..0000000
--- a/include/nvgpu/hw/gm20b/hw_trim_gm20b.h
+++ /dev/null
@@ -1,503 +0,0 @@
1/*
2 * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22/*
23 * Function naming determines intended use:
24 *
25 * <x>_r(void) : Returns the offset for register <x>.
26 *
27 * <x>_o(void) : Returns the offset for element <x>.
28 *
29 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
30 *
31 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
32 *
33 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
34 * and masked to place it at field <y> of register <x>. This value
35 * can be |'d with others to produce a full register value for
36 * register <x>.
37 *
38 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
39 * value can be ~'d and then &'d to clear the value of field <y> for
40 * register <x>.
41 *
42 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
43 * to place it at field <y> of register <x>. This value can be |'d
44 * with others to produce a full register value for <x>.
45 *
46 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
47 * <x> value 'r' after being shifted to place its LSB at bit 0.
48 * This value is suitable for direct comparison with other unshifted
49 * values appropriate for use in field <y> of register <x>.
50 *
51 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
52 * field <y> of register <x>. This value is suitable for direct
53 * comparison with unshifted values appropriate for use in field <y>
54 * of register <x>.
55 */
56#ifndef _hw_trim_gm20b_h_
57#define _hw_trim_gm20b_h_
58
59static inline u32 trim_sys_gpcpll_cfg_r(void)
60{
61 return 0x00137000U;
62}
63static inline u32 trim_sys_gpcpll_cfg_enable_m(void)
64{
65 return 0x1U << 0U;
66}
67static inline u32 trim_sys_gpcpll_cfg_enable_v(u32 r)
68{
69 return (r >> 0U) & 0x1U;
70}
71static inline u32 trim_sys_gpcpll_cfg_enable_no_f(void)
72{
73 return 0x0U;
74}
75static inline u32 trim_sys_gpcpll_cfg_enable_yes_f(void)
76{
77 return 0x1U;
78}
79static inline u32 trim_sys_gpcpll_cfg_iddq_m(void)
80{
81 return 0x1U << 1U;
82}
83static inline u32 trim_sys_gpcpll_cfg_iddq_v(u32 r)
84{
85 return (r >> 1U) & 0x1U;
86}
87static inline u32 trim_sys_gpcpll_cfg_iddq_power_on_v(void)
88{
89 return 0x00000000U;
90}
91static inline u32 trim_sys_gpcpll_cfg_sync_mode_m(void)
92{
93 return 0x1U << 2U;
94}
95static inline u32 trim_sys_gpcpll_cfg_sync_mode_v(u32 r)
96{
97 return (r >> 2U) & 0x1U;
98}
99static inline u32 trim_sys_gpcpll_cfg_sync_mode_enable_f(void)
100{
101 return 0x4U;
102}
103static inline u32 trim_sys_gpcpll_cfg_sync_mode_disable_f(void)
104{
105 return 0x0U;
106}
107static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_m(void)
108{
109 return 0x1U << 4U;
110}
111static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_power_on_f(void)
112{
113 return 0x0U;
114}
115static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_power_off_f(void)
116{
117 return 0x10U;
118}
119static inline u32 trim_sys_gpcpll_cfg_pll_lock_v(u32 r)
120{
121 return (r >> 17U) & 0x1U;
122}
123static inline u32 trim_sys_gpcpll_cfg_pll_lock_true_f(void)
124{
125 return 0x20000U;
126}
127static inline u32 trim_sys_gpcpll_coeff_r(void)
128{
129 return 0x00137004U;
130}
131static inline u32 trim_sys_gpcpll_coeff_mdiv_f(u32 v)
132{
133 return (v & 0xffU) << 0U;
134}
135static inline u32 trim_sys_gpcpll_coeff_mdiv_m(void)
136{
137 return 0xffU << 0U;
138}
139static inline u32 trim_sys_gpcpll_coeff_mdiv_v(u32 r)
140{
141 return (r >> 0U) & 0xffU;
142}
143static inline u32 trim_sys_gpcpll_coeff_ndiv_f(u32 v)
144{
145 return (v & 0xffU) << 8U;
146}
147static inline u32 trim_sys_gpcpll_coeff_ndiv_m(void)
148{
149 return 0xffU << 8U;
150}
151static inline u32 trim_sys_gpcpll_coeff_ndiv_v(u32 r)
152{
153 return (r >> 8U) & 0xffU;
154}
155static inline u32 trim_sys_gpcpll_coeff_pldiv_f(u32 v)
156{
157 return (v & 0x3fU) << 16U;
158}
159static inline u32 trim_sys_gpcpll_coeff_pldiv_m(void)
160{
161 return 0x3fU << 16U;
162}
163static inline u32 trim_sys_gpcpll_coeff_pldiv_v(u32 r)
164{
165 return (r >> 16U) & 0x3fU;
166}
167static inline u32 trim_sys_sel_vco_r(void)
168{
169 return 0x00137100U;
170}
171static inline u32 trim_sys_sel_vco_gpc2clk_out_m(void)
172{
173 return 0x1U << 0U;
174}
175static inline u32 trim_sys_sel_vco_gpc2clk_out_init_v(void)
176{
177 return 0x00000000U;
178}
179static inline u32 trim_sys_sel_vco_gpc2clk_out_init_f(void)
180{
181 return 0x0U;
182}
183static inline u32 trim_sys_sel_vco_gpc2clk_out_bypass_f(void)
184{
185 return 0x0U;
186}
187static inline u32 trim_sys_sel_vco_gpc2clk_out_vco_f(void)
188{
189 return 0x1U;
190}
191static inline u32 trim_sys_gpc2clk_out_r(void)
192{
193 return 0x00137250U;
194}
195static inline u32 trim_sys_gpc2clk_out_bypdiv_s(void)
196{
197 return 6U;
198}
199static inline u32 trim_sys_gpc2clk_out_bypdiv_f(u32 v)
200{
201 return (v & 0x3fU) << 0U;
202}
203static inline u32 trim_sys_gpc2clk_out_bypdiv_m(void)
204{
205 return 0x3fU << 0U;
206}
207static inline u32 trim_sys_gpc2clk_out_bypdiv_v(u32 r)
208{
209 return (r >> 0U) & 0x3fU;
210}
211static inline u32 trim_sys_gpc2clk_out_bypdiv_by31_f(void)
212{
213 return 0x3cU;
214}
215static inline u32 trim_sys_gpc2clk_out_vcodiv_s(void)
216{
217 return 6U;
218}
219static inline u32 trim_sys_gpc2clk_out_vcodiv_f(u32 v)
220{
221 return (v & 0x3fU) << 8U;
222}
223static inline u32 trim_sys_gpc2clk_out_vcodiv_m(void)
224{
225 return 0x3fU << 8U;
226}
227static inline u32 trim_sys_gpc2clk_out_vcodiv_v(u32 r)
228{
229 return (r >> 8U) & 0x3fU;
230}
231static inline u32 trim_sys_gpc2clk_out_vcodiv_by1_f(void)
232{
233 return 0x0U;
234}
235static inline u32 trim_sys_gpc2clk_out_sdiv14_m(void)
236{
237 return 0x1U << 31U;
238}
239static inline u32 trim_sys_gpc2clk_out_sdiv14_indiv4_mode_f(void)
240{
241 return 0x80000000U;
242}
243static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_r(u32 i)
244{
245 return 0x00134124U + i*512U;
246}
247static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_noofipclks_f(u32 v)
248{
249 return (v & 0x3fffU) << 0U;
250}
251static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_write_en_asserted_f(void)
252{
253 return 0x10000U;
254}
255static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_enable_asserted_f(void)
256{
257 return 0x100000U;
258}
259static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_reset_asserted_f(void)
260{
261 return 0x1000000U;
262}
263static inline u32 trim_gpc_clk_cntr_ncgpcclk_cnt_r(u32 i)
264{
265 return 0x00134128U + i*512U;
266}
267static inline u32 trim_gpc_clk_cntr_ncgpcclk_cnt_value_v(u32 r)
268{
269 return (r >> 0U) & 0xfffffU;
270}
271static inline u32 trim_sys_gpcpll_cfg2_r(void)
272{
273 return 0x0013700cU;
274}
275static inline u32 trim_sys_gpcpll_cfg2_sdm_din_f(u32 v)
276{
277 return (v & 0xffU) << 0U;
278}
279static inline u32 trim_sys_gpcpll_cfg2_sdm_din_m(void)
280{
281 return 0xffU << 0U;
282}
283static inline u32 trim_sys_gpcpll_cfg2_sdm_din_v(u32 r)
284{
285 return (r >> 0U) & 0xffU;
286}
287static inline u32 trim_sys_gpcpll_cfg2_sdm_din_new_f(u32 v)
288{
289 return (v & 0xffU) << 8U;
290}
291static inline u32 trim_sys_gpcpll_cfg2_sdm_din_new_m(void)
292{
293 return 0xffU << 8U;
294}
295static inline u32 trim_sys_gpcpll_cfg2_sdm_din_new_v(u32 r)
296{
297 return (r >> 8U) & 0xffU;
298}
299static inline u32 trim_sys_gpcpll_cfg2_pll_stepa_f(u32 v)
300{
301 return (v & 0xffU) << 24U;
302}
303static inline u32 trim_sys_gpcpll_cfg2_pll_stepa_m(void)
304{
305 return 0xffU << 24U;
306}
307static inline u32 trim_sys_gpcpll_cfg3_r(void)
308{
309 return 0x00137018U;
310}
311static inline u32 trim_sys_gpcpll_cfg3_vco_ctrl_f(u32 v)
312{
313 return (v & 0x1ffU) << 0U;
314}
315static inline u32 trim_sys_gpcpll_cfg3_vco_ctrl_m(void)
316{
317 return 0x1ffU << 0U;
318}
319static inline u32 trim_sys_gpcpll_cfg3_pll_stepb_f(u32 v)
320{
321 return (v & 0xffU) << 16U;
322}
323static inline u32 trim_sys_gpcpll_cfg3_pll_stepb_m(void)
324{
325 return 0xffU << 16U;
326}
327static inline u32 trim_sys_gpcpll_cfg3_dfs_testout_v(u32 r)
328{
329 return (r >> 24U) & 0x7fU;
330}
331static inline u32 trim_sys_gpcpll_dvfs0_r(void)
332{
333 return 0x00137010U;
334}
335static inline u32 trim_sys_gpcpll_dvfs0_dfs_coeff_f(u32 v)
336{
337 return (v & 0x7fU) << 0U;
338}
339static inline u32 trim_sys_gpcpll_dvfs0_dfs_coeff_m(void)
340{
341 return 0x7fU << 0U;
342}
343static inline u32 trim_sys_gpcpll_dvfs0_dfs_coeff_v(u32 r)
344{
345 return (r >> 0U) & 0x7fU;
346}
347static inline u32 trim_sys_gpcpll_dvfs0_dfs_det_max_f(u32 v)
348{
349 return (v & 0x7fU) << 8U;
350}
351static inline u32 trim_sys_gpcpll_dvfs0_dfs_det_max_m(void)
352{
353 return 0x7fU << 8U;
354}
355static inline u32 trim_sys_gpcpll_dvfs0_dfs_det_max_v(u32 r)
356{
357 return (r >> 8U) & 0x7fU;
358}
359static inline u32 trim_sys_gpcpll_dvfs0_dfs_dc_offset_f(u32 v)
360{
361 return (v & 0x3fU) << 16U;
362}
363static inline u32 trim_sys_gpcpll_dvfs0_dfs_dc_offset_m(void)
364{
365 return 0x3fU << 16U;
366}
367static inline u32 trim_sys_gpcpll_dvfs0_dfs_dc_offset_v(u32 r)
368{
369 return (r >> 16U) & 0x3fU;
370}
371static inline u32 trim_sys_gpcpll_dvfs0_mode_m(void)
372{
373 return 0x1U << 28U;
374}
375static inline u32 trim_sys_gpcpll_dvfs0_mode_dvfspll_f(void)
376{
377 return 0x0U;
378}
379static inline u32 trim_sys_gpcpll_dvfs1_r(void)
380{
381 return 0x00137014U;
382}
383static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_det_f(u32 v)
384{
385 return (v & 0x7fU) << 0U;
386}
387static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_det_m(void)
388{
389 return 0x7fU << 0U;
390}
391static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_det_v(u32 r)
392{
393 return (r >> 0U) & 0x7fU;
394}
395static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_strb_m(void)
396{
397 return 0x1U << 7U;
398}
399static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_cal_f(u32 v)
400{
401 return (v & 0x7fU) << 8U;
402}
403static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_cal_m(void)
404{
405 return 0x7fU << 8U;
406}
407static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_cal_v(u32 r)
408{
409 return (r >> 8U) & 0x7fU;
410}
411static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_sel_m(void)
412{
413 return 0x1U << 15U;
414}
415static inline u32 trim_sys_gpcpll_dvfs1_dfs_ctrl_f(u32 v)
416{
417 return (v & 0xfffU) << 16U;
418}
419static inline u32 trim_sys_gpcpll_dvfs1_dfs_ctrl_m(void)
420{
421 return 0xfffU << 16U;
422}
423static inline u32 trim_sys_gpcpll_dvfs1_dfs_ctrl_v(u32 r)
424{
425 return (r >> 16U) & 0xfffU;
426}
427static inline u32 trim_sys_gpcpll_dvfs1_en_sdm_m(void)
428{
429 return 0x1U << 28U;
430}
431static inline u32 trim_sys_gpcpll_dvfs1_en_dfs_m(void)
432{
433 return 0x1U << 29U;
434}
435static inline u32 trim_sys_gpcpll_dvfs1_en_dfs_cal_m(void)
436{
437 return 0x1U << 30U;
438}
439static inline u32 trim_sys_gpcpll_dvfs1_dfs_cal_done_v(u32 r)
440{
441 return (r >> 31U) & 0x1U;
442}
443static inline u32 trim_sys_gpcpll_dvfs2_r(void)
444{
445 return 0x00137020U;
446}
447static inline u32 trim_sys_gpcpll_ndiv_slowdown_r(void)
448{
449 return 0x0013701cU;
450}
451static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_m(void)
452{
453 return 0x1U << 22U;
454}
455static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_yes_f(void)
456{
457 return 0x400000U;
458}
459static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_no_f(void)
460{
461 return 0x0U;
462}
463static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_m(void)
464{
465 return 0x1U << 31U;
466}
467static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_yes_f(void)
468{
469 return 0x80000000U;
470}
471static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_no_f(void)
472{
473 return 0x0U;
474}
475static inline u32 trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_r(void)
476{
477 return 0x001328a0U;
478}
479static inline u32 trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_pll_dynramp_done_synced_v(u32 r)
480{
481 return (r >> 24U) & 0x1U;
482}
483static inline u32 trim_gpc_bcast_gpcpll_dvfs2_r(void)
484{
485 return 0x00132820U;
486}
487static inline u32 trim_sys_bypassctrl_r(void)
488{
489 return 0x00137340U;
490}
491static inline u32 trim_sys_bypassctrl_gpcpll_m(void)
492{
493 return 0x1U << 0U;
494}
495static inline u32 trim_sys_bypassctrl_gpcpll_bypassclk_f(void)
496{
497 return 0x1U;
498}
499static inline u32 trim_sys_bypassctrl_gpcpll_vco_f(void)
500{
501 return 0x0U;
502}
503#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-30 14:24:21 -0400