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-rw-r--r--include/nvgpu/hw/gm20b/hw_mc_gm20b.h287
1 files changed, 0 insertions, 287 deletions
diff --git a/include/nvgpu/hw/gm20b/hw_mc_gm20b.h b/include/nvgpu/hw/gm20b/hw_mc_gm20b.h
deleted file mode 100644
index 0264803..0000000
--- a/include/nvgpu/hw/gm20b/hw_mc_gm20b.h
+++ /dev/null
@@ -1,287 +0,0 @@
1/*
2 * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22/*
23 * Function naming determines intended use:
24 *
25 * <x>_r(void) : Returns the offset for register <x>.
26 *
27 * <x>_o(void) : Returns the offset for element <x>.
28 *
29 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
30 *
31 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
32 *
33 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
34 * and masked to place it at field <y> of register <x>. This value
35 * can be |'d with others to produce a full register value for
36 * register <x>.
37 *
38 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
39 * value can be ~'d and then &'d to clear the value of field <y> for
40 * register <x>.
41 *
42 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
43 * to place it at field <y> of register <x>. This value can be |'d
44 * with others to produce a full register value for <x>.
45 *
46 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
47 * <x> value 'r' after being shifted to place its LSB at bit 0.
48 * This value is suitable for direct comparison with other unshifted
49 * values appropriate for use in field <y> of register <x>.
50 *
51 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
52 * field <y> of register <x>. This value is suitable for direct
53 * comparison with unshifted values appropriate for use in field <y>
54 * of register <x>.
55 */
56#ifndef _hw_mc_gm20b_h_
57#define _hw_mc_gm20b_h_
58
59static inline u32 mc_boot_0_r(void)
60{
61 return 0x00000000U;
62}
63static inline u32 mc_boot_0_architecture_v(u32 r)
64{
65 return (r >> 24U) & 0x1fU;
66}
67static inline u32 mc_boot_0_implementation_v(u32 r)
68{
69 return (r >> 20U) & 0xfU;
70}
71static inline u32 mc_boot_0_major_revision_v(u32 r)
72{
73 return (r >> 4U) & 0xfU;
74}
75static inline u32 mc_boot_0_minor_revision_v(u32 r)
76{
77 return (r >> 0U) & 0xfU;
78}
79static inline u32 mc_intr_r(u32 i)
80{
81 return 0x00000100U + i*4U;
82}
83static inline u32 mc_intr_pfifo_pending_f(void)
84{
85 return 0x100U;
86}
87static inline u32 mc_intr_pmu_pending_f(void)
88{
89 return 0x1000000U;
90}
91static inline u32 mc_intr_ltc_pending_f(void)
92{
93 return 0x2000000U;
94}
95static inline u32 mc_intr_priv_ring_pending_f(void)
96{
97 return 0x40000000U;
98}
99static inline u32 mc_intr_pbus_pending_f(void)
100{
101 return 0x10000000U;
102}
103static inline u32 mc_intr_mask_0_r(void)
104{
105 return 0x00000640U;
106}
107static inline u32 mc_intr_mask_0_pmu_enabled_f(void)
108{
109 return 0x1000000U;
110}
111static inline u32 mc_intr_en_0_r(void)
112{
113 return 0x00000140U;
114}
115static inline u32 mc_intr_en_0_inta_disabled_f(void)
116{
117 return 0x0U;
118}
119static inline u32 mc_intr_en_0_inta_hardware_f(void)
120{
121 return 0x1U;
122}
123static inline u32 mc_intr_mask_1_r(void)
124{
125 return 0x00000644U;
126}
127static inline u32 mc_intr_mask_1_pmu_s(void)
128{
129 return 1U;
130}
131static inline u32 mc_intr_mask_1_pmu_f(u32 v)
132{
133 return (v & 0x1U) << 24U;
134}
135static inline u32 mc_intr_mask_1_pmu_m(void)
136{
137 return 0x1U << 24U;
138}
139static inline u32 mc_intr_mask_1_pmu_v(u32 r)
140{
141 return (r >> 24U) & 0x1U;
142}
143static inline u32 mc_intr_mask_1_pmu_enabled_f(void)
144{
145 return 0x1000000U;
146}
147static inline u32 mc_intr_en_1_r(void)
148{
149 return 0x00000144U;
150}
151static inline u32 mc_intr_en_1_inta_disabled_f(void)
152{
153 return 0x0U;
154}
155static inline u32 mc_intr_en_1_inta_hardware_f(void)
156{
157 return 0x1U;
158}
159static inline u32 mc_enable_r(void)
160{
161 return 0x00000200U;
162}
163static inline u32 mc_enable_xbar_enabled_f(void)
164{
165 return 0x4U;
166}
167static inline u32 mc_enable_l2_enabled_f(void)
168{
169 return 0x8U;
170}
171static inline u32 mc_enable_pmedia_s(void)
172{
173 return 1U;
174}
175static inline u32 mc_enable_pmedia_f(u32 v)
176{
177 return (v & 0x1U) << 4U;
178}
179static inline u32 mc_enable_pmedia_m(void)
180{
181 return 0x1U << 4U;
182}
183static inline u32 mc_enable_pmedia_v(u32 r)
184{
185 return (r >> 4U) & 0x1U;
186}
187static inline u32 mc_enable_priv_ring_enabled_f(void)
188{
189 return 0x20U;
190}
191static inline u32 mc_enable_ce0_m(void)
192{
193 return 0x1U << 6U;
194}
195static inline u32 mc_enable_pfifo_enabled_f(void)
196{
197 return 0x100U;
198}
199static inline u32 mc_enable_pgraph_enabled_f(void)
200{
201 return 0x1000U;
202}
203static inline u32 mc_enable_pwr_v(u32 r)
204{
205 return (r >> 13U) & 0x1U;
206}
207static inline u32 mc_enable_pwr_disabled_v(void)
208{
209 return 0x00000000U;
210}
211static inline u32 mc_enable_pwr_enabled_f(void)
212{
213 return 0x2000U;
214}
215static inline u32 mc_enable_pfb_enabled_f(void)
216{
217 return 0x100000U;
218}
219static inline u32 mc_enable_ce2_m(void)
220{
221 return 0x1U << 21U;
222}
223static inline u32 mc_enable_ce2_enabled_f(void)
224{
225 return 0x200000U;
226}
227static inline u32 mc_enable_blg_enabled_f(void)
228{
229 return 0x8000000U;
230}
231static inline u32 mc_enable_perfmon_enabled_f(void)
232{
233 return 0x10000000U;
234}
235static inline u32 mc_enable_hub_enabled_f(void)
236{
237 return 0x20000000U;
238}
239static inline u32 mc_intr_ltc_r(void)
240{
241 return 0x0000017cU;
242}
243static inline u32 mc_enable_pb_r(void)
244{
245 return 0x00000204U;
246}
247static inline u32 mc_enable_pb_0_s(void)
248{
249 return 1U;
250}
251static inline u32 mc_enable_pb_0_f(u32 v)
252{
253 return (v & 0x1U) << 0U;
254}
255static inline u32 mc_enable_pb_0_m(void)
256{
257 return 0x1U << 0U;
258}
259static inline u32 mc_enable_pb_0_v(u32 r)
260{
261 return (r >> 0U) & 0x1U;
262}
263static inline u32 mc_enable_pb_0_enabled_v(void)
264{
265 return 0x00000001U;
266}
267static inline u32 mc_enable_pb_sel_f(u32 v, u32 i)
268{
269 return (v & 0x1U) << (0U + i*1U);
270}
271static inline u32 mc_elpg_enable_r(void)
272{
273 return 0x0000020cU;
274}
275static inline u32 mc_elpg_enable_xbar_enabled_f(void)
276{
277 return 0x4U;
278}
279static inline u32 mc_elpg_enable_pfb_enabled_f(void)
280{
281 return 0x100000U;
282}
283static inline u32 mc_elpg_enable_hub_enabled_f(void)
284{
285 return 0x20000000U;
286}
287#endif
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