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-rw-r--r--include/nvgpu/hw/gm20b/hw_ccsr_gm20b.h163
1 files changed, 163 insertions, 0 deletions
diff --git a/include/nvgpu/hw/gm20b/hw_ccsr_gm20b.h b/include/nvgpu/hw/gm20b/hw_ccsr_gm20b.h
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index 0000000..adfce72
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+++ b/include/nvgpu/hw/gm20b/hw_ccsr_gm20b.h
@@ -0,0 +1,163 @@
1/*
2 * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22/*
23 * Function naming determines intended use:
24 *
25 * <x>_r(void) : Returns the offset for register <x>.
26 *
27 * <x>_o(void) : Returns the offset for element <x>.
28 *
29 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
30 *
31 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
32 *
33 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
34 * and masked to place it at field <y> of register <x>. This value
35 * can be |'d with others to produce a full register value for
36 * register <x>.
37 *
38 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
39 * value can be ~'d and then &'d to clear the value of field <y> for
40 * register <x>.
41 *
42 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
43 * to place it at field <y> of register <x>. This value can be |'d
44 * with others to produce a full register value for <x>.
45 *
46 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
47 * <x> value 'r' after being shifted to place its LSB at bit 0.
48 * This value is suitable for direct comparison with other unshifted
49 * values appropriate for use in field <y> of register <x>.
50 *
51 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
52 * field <y> of register <x>. This value is suitable for direct
53 * comparison with unshifted values appropriate for use in field <y>
54 * of register <x>.
55 */
56#ifndef _hw_ccsr_gm20b_h_
57#define _hw_ccsr_gm20b_h_
58
59static inline u32 ccsr_channel_inst_r(u32 i)
60{
61 return 0x00800000U + i*8U;
62}
63static inline u32 ccsr_channel_inst__size_1_v(void)
64{
65 return 0x00000200U;
66}
67static inline u32 ccsr_channel_inst_ptr_f(u32 v)
68{
69 return (v & 0xfffffffU) << 0U;
70}
71static inline u32 ccsr_channel_inst_target_vid_mem_f(void)
72{
73 return 0x0U;
74}
75static inline u32 ccsr_channel_inst_target_sys_mem_coh_f(void)
76{
77 return 0x20000000U;
78}
79static inline u32 ccsr_channel_inst_target_sys_mem_ncoh_f(void)
80{
81 return 0x30000000U;
82}
83static inline u32 ccsr_channel_inst_bind_false_f(void)
84{
85 return 0x0U;
86}
87static inline u32 ccsr_channel_inst_bind_true_f(void)
88{
89 return 0x80000000U;
90}
91static inline u32 ccsr_channel_r(u32 i)
92{
93 return 0x00800004U + i*8U;
94}
95static inline u32 ccsr_channel__size_1_v(void)
96{
97 return 0x00000200U;
98}
99static inline u32 ccsr_channel_enable_v(u32 r)
100{
101 return (r >> 0U) & 0x1U;
102}
103static inline u32 ccsr_channel_enable_set_f(u32 v)
104{
105 return (v & 0x1U) << 10U;
106}
107static inline u32 ccsr_channel_enable_set_true_f(void)
108{
109 return 0x400U;
110}
111static inline u32 ccsr_channel_enable_clr_true_f(void)
112{
113 return 0x800U;
114}
115static inline u32 ccsr_channel_status_v(u32 r)
116{
117 return (r >> 24U) & 0xfU;
118}
119static inline u32 ccsr_channel_status_pending_ctx_reload_v(void)
120{
121 return 0x00000002U;
122}
123static inline u32 ccsr_channel_status_pending_acq_ctx_reload_v(void)
124{
125 return 0x00000004U;
126}
127static inline u32 ccsr_channel_status_on_pbdma_ctx_reload_v(void)
128{
129 return 0x0000000aU;
130}
131static inline u32 ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v(void)
132{
133 return 0x0000000bU;
134}
135static inline u32 ccsr_channel_status_on_eng_ctx_reload_v(void)
136{
137 return 0x0000000cU;
138}
139static inline u32 ccsr_channel_status_on_eng_pending_ctx_reload_v(void)
140{
141 return 0x0000000dU;
142}
143static inline u32 ccsr_channel_status_on_eng_pending_acq_ctx_reload_v(void)
144{
145 return 0x0000000eU;
146}
147static inline u32 ccsr_channel_next_v(u32 r)
148{
149 return (r >> 1U) & 0x1U;
150}
151static inline u32 ccsr_channel_next_true_v(void)
152{
153 return 0x00000001U;
154}
155static inline u32 ccsr_channel_force_ctx_reload_true_f(void)
156{
157 return 0x100U;
158}
159static inline u32 ccsr_channel_busy_v(u32 r)
160{
161 return (r >> 28U) & 0x1U;
162}
163#endif