aboutsummaryrefslogtreecommitdiffstats
path: root/include/nvgpu/hw/gk20a/hw_gr_gk20a.h
diff options
context:
space:
mode:
Diffstat (limited to 'include/nvgpu/hw/gk20a/hw_gr_gk20a.h')
-rw-r--r--include/nvgpu/hw/gk20a/hw_gr_gk20a.h3868
1 files changed, 0 insertions, 3868 deletions
diff --git a/include/nvgpu/hw/gk20a/hw_gr_gk20a.h b/include/nvgpu/hw/gk20a/hw_gr_gk20a.h
deleted file mode 100644
index 376cc8f..0000000
--- a/include/nvgpu/hw/gk20a/hw_gr_gk20a.h
+++ /dev/null
@@ -1,3868 +0,0 @@
1/*
2 * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22/*
23 * Function naming determines intended use:
24 *
25 * <x>_r(void) : Returns the offset for register <x>.
26 *
27 * <x>_o(void) : Returns the offset for element <x>.
28 *
29 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
30 *
31 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
32 *
33 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
34 * and masked to place it at field <y> of register <x>. This value
35 * can be |'d with others to produce a full register value for
36 * register <x>.
37 *
38 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
39 * value can be ~'d and then &'d to clear the value of field <y> for
40 * register <x>.
41 *
42 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
43 * to place it at field <y> of register <x>. This value can be |'d
44 * with others to produce a full register value for <x>.
45 *
46 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
47 * <x> value 'r' after being shifted to place its LSB at bit 0.
48 * This value is suitable for direct comparison with other unshifted
49 * values appropriate for use in field <y> of register <x>.
50 *
51 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
52 * field <y> of register <x>. This value is suitable for direct
53 * comparison with unshifted values appropriate for use in field <y>
54 * of register <x>.
55 */
56#ifndef _hw_gr_gk20a_h_
57#define _hw_gr_gk20a_h_
58
59static inline u32 gr_intr_r(void)
60{
61 return 0x00400100U;
62}
63static inline u32 gr_intr_notify_pending_f(void)
64{
65 return 0x1U;
66}
67static inline u32 gr_intr_notify_reset_f(void)
68{
69 return 0x1U;
70}
71static inline u32 gr_intr_semaphore_pending_f(void)
72{
73 return 0x2U;
74}
75static inline u32 gr_intr_semaphore_reset_f(void)
76{
77 return 0x2U;
78}
79static inline u32 gr_intr_semaphore_timeout_not_pending_f(void)
80{
81 return 0x0U;
82}
83static inline u32 gr_intr_semaphore_timeout_pending_f(void)
84{
85 return 0x4U;
86}
87static inline u32 gr_intr_semaphore_timeout_reset_f(void)
88{
89 return 0x4U;
90}
91static inline u32 gr_intr_illegal_method_pending_f(void)
92{
93 return 0x10U;
94}
95static inline u32 gr_intr_illegal_method_reset_f(void)
96{
97 return 0x10U;
98}
99static inline u32 gr_intr_illegal_notify_pending_f(void)
100{
101 return 0x40U;
102}
103static inline u32 gr_intr_illegal_notify_reset_f(void)
104{
105 return 0x40U;
106}
107static inline u32 gr_intr_firmware_method_f(u32 v)
108{
109 return (v & 0x1U) << 8U;
110}
111static inline u32 gr_intr_firmware_method_pending_f(void)
112{
113 return 0x100U;
114}
115static inline u32 gr_intr_firmware_method_reset_f(void)
116{
117 return 0x100U;
118}
119static inline u32 gr_intr_illegal_class_pending_f(void)
120{
121 return 0x20U;
122}
123static inline u32 gr_intr_illegal_class_reset_f(void)
124{
125 return 0x20U;
126}
127static inline u32 gr_intr_fecs_error_pending_f(void)
128{
129 return 0x80000U;
130}
131static inline u32 gr_intr_fecs_error_reset_f(void)
132{
133 return 0x80000U;
134}
135static inline u32 gr_intr_class_error_pending_f(void)
136{
137 return 0x100000U;
138}
139static inline u32 gr_intr_class_error_reset_f(void)
140{
141 return 0x100000U;
142}
143static inline u32 gr_intr_exception_pending_f(void)
144{
145 return 0x200000U;
146}
147static inline u32 gr_intr_exception_reset_f(void)
148{
149 return 0x200000U;
150}
151static inline u32 gr_fecs_intr_r(void)
152{
153 return 0x00400144U;
154}
155static inline u32 gr_class_error_r(void)
156{
157 return 0x00400110U;
158}
159static inline u32 gr_class_error_code_v(u32 r)
160{
161 return (r >> 0U) & 0xffffU;
162}
163static inline u32 gr_intr_nonstall_r(void)
164{
165 return 0x00400120U;
166}
167static inline u32 gr_intr_nonstall_trap_pending_f(void)
168{
169 return 0x2U;
170}
171static inline u32 gr_intr_en_r(void)
172{
173 return 0x0040013cU;
174}
175static inline u32 gr_exception_r(void)
176{
177 return 0x00400108U;
178}
179static inline u32 gr_exception_fe_m(void)
180{
181 return 0x1U << 0U;
182}
183static inline u32 gr_exception_gpc_m(void)
184{
185 return 0x1U << 24U;
186}
187static inline u32 gr_exception_memfmt_m(void)
188{
189 return 0x1U << 1U;
190}
191static inline u32 gr_exception_ds_m(void)
192{
193 return 0x1U << 4U;
194}
195static inline u32 gr_exception_sked_m(void)
196{
197 return 0x1U << 8U;
198}
199static inline u32 gr_exception_pd_m(void)
200{
201 return 0x1U << 2U;
202}
203static inline u32 gr_exception_scc_m(void)
204{
205 return 0x1U << 3U;
206}
207static inline u32 gr_exception_ssync_m(void)
208{
209 return 0x1U << 5U;
210}
211static inline u32 gr_exception_mme_m(void)
212{
213 return 0x1U << 7U;
214}
215static inline u32 gr_exception1_r(void)
216{
217 return 0x00400118U;
218}
219static inline u32 gr_exception1_gpc_0_pending_f(void)
220{
221 return 0x1U;
222}
223static inline u32 gr_exception2_r(void)
224{
225 return 0x0040011cU;
226}
227static inline u32 gr_exception_en_r(void)
228{
229 return 0x00400138U;
230}
231static inline u32 gr_exception_en_fe_m(void)
232{
233 return 0x1U << 0U;
234}
235static inline u32 gr_exception1_en_r(void)
236{
237 return 0x00400130U;
238}
239static inline u32 gr_exception2_en_r(void)
240{
241 return 0x00400134U;
242}
243static inline u32 gr_gpfifo_ctl_r(void)
244{
245 return 0x00400500U;
246}
247static inline u32 gr_gpfifo_ctl_access_f(u32 v)
248{
249 return (v & 0x1U) << 0U;
250}
251static inline u32 gr_gpfifo_ctl_access_disabled_f(void)
252{
253 return 0x0U;
254}
255static inline u32 gr_gpfifo_ctl_access_enabled_f(void)
256{
257 return 0x1U;
258}
259static inline u32 gr_gpfifo_ctl_semaphore_access_f(u32 v)
260{
261 return (v & 0x1U) << 16U;
262}
263static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_v(void)
264{
265 return 0x00000001U;
266}
267static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_f(void)
268{
269 return 0x10000U;
270}
271static inline u32 gr_gpfifo_status_r(void)
272{
273 return 0x00400504U;
274}
275static inline u32 gr_trapped_addr_r(void)
276{
277 return 0x00400704U;
278}
279static inline u32 gr_trapped_addr_mthd_v(u32 r)
280{
281 return (r >> 2U) & 0xfffU;
282}
283static inline u32 gr_trapped_addr_subch_v(u32 r)
284{
285 return (r >> 16U) & 0x7U;
286}
287static inline u32 gr_trapped_addr_mme_generated_v(u32 r)
288{
289 return (r >> 20U) & 0x1U;
290}
291static inline u32 gr_trapped_addr_datahigh_v(u32 r)
292{
293 return (r >> 24U) & 0x1U;
294}
295static inline u32 gr_trapped_addr_priv_v(u32 r)
296{
297 return (r >> 28U) & 0x1U;
298}
299static inline u32 gr_trapped_addr_status_v(u32 r)
300{
301 return (r >> 31U) & 0x1U;
302}
303static inline u32 gr_trapped_data_lo_r(void)
304{
305 return 0x00400708U;
306}
307static inline u32 gr_trapped_data_hi_r(void)
308{
309 return 0x0040070cU;
310}
311static inline u32 gr_trapped_data_mme_r(void)
312{
313 return 0x00400710U;
314}
315static inline u32 gr_trapped_data_mme_pc_v(u32 r)
316{
317 return (r >> 0U) & 0x7ffU;
318}
319static inline u32 gr_status_r(void)
320{
321 return 0x00400700U;
322}
323static inline u32 gr_status_fe_method_upper_v(u32 r)
324{
325 return (r >> 1U) & 0x1U;
326}
327static inline u32 gr_status_fe_method_lower_v(u32 r)
328{
329 return (r >> 2U) & 0x1U;
330}
331static inline u32 gr_status_fe_method_lower_idle_v(void)
332{
333 return 0x00000000U;
334}
335static inline u32 gr_status_fe_gi_v(u32 r)
336{
337 return (r >> 21U) & 0x1U;
338}
339static inline u32 gr_status_mask_r(void)
340{
341 return 0x00400610U;
342}
343static inline u32 gr_status_1_r(void)
344{
345 return 0x00400604U;
346}
347static inline u32 gr_status_2_r(void)
348{
349 return 0x00400608U;
350}
351static inline u32 gr_engine_status_r(void)
352{
353 return 0x0040060cU;
354}
355static inline u32 gr_engine_status_value_busy_f(void)
356{
357 return 0x1U;
358}
359static inline u32 gr_pri_be0_becs_be_exception_r(void)
360{
361 return 0x00410204U;
362}
363static inline u32 gr_pri_be0_becs_be_exception_en_r(void)
364{
365 return 0x00410208U;
366}
367static inline u32 gr_pri_gpc0_gpccs_gpc_exception_r(void)
368{
369 return 0x00502c90U;
370}
371static inline u32 gr_pri_gpc0_gpccs_gpc_exception_en_r(void)
372{
373 return 0x00502c94U;
374}
375static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_r(void)
376{
377 return 0x00504508U;
378}
379static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r(void)
380{
381 return 0x0050450cU;
382}
383static inline u32 gr_activity_0_r(void)
384{
385 return 0x00400380U;
386}
387static inline u32 gr_activity_1_r(void)
388{
389 return 0x00400384U;
390}
391static inline u32 gr_activity_2_r(void)
392{
393 return 0x00400388U;
394}
395static inline u32 gr_activity_4_r(void)
396{
397 return 0x00400390U;
398}
399static inline u32 gr_pri_gpc0_gcc_dbg_r(void)
400{
401 return 0x00501000U;
402}
403static inline u32 gr_pri_gpcs_gcc_dbg_r(void)
404{
405 return 0x00419000U;
406}
407static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void)
408{
409 return 0x1U << 1U;
410}
411static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void)
412{
413 return 0x005046a4U;
414}
415static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void)
416{
417 return 0x00419ea4U;
418}
419static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void)
420{
421 return 0x1U << 0U;
422}
423static inline u32 gr_pri_sked_activity_r(void)
424{
425 return 0x00407054U;
426}
427static inline u32 gr_pri_gpc0_gpccs_gpc_activity0_r(void)
428{
429 return 0x00502c80U;
430}
431static inline u32 gr_pri_gpc0_gpccs_gpc_activity1_r(void)
432{
433 return 0x00502c84U;
434}
435static inline u32 gr_pri_gpc0_gpccs_gpc_activity2_r(void)
436{
437 return 0x00502c88U;
438}
439static inline u32 gr_pri_gpc0_gpccs_gpc_activity3_r(void)
440{
441 return 0x00502c8cU;
442}
443static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r(void)
444{
445 return 0x00504500U;
446}
447static inline u32 gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r(void)
448{
449 return 0x00501d00U;
450}
451static inline u32 gr_pri_gpcs_gpccs_gpc_activity_0_r(void)
452{
453 return 0x0041ac80U;
454}
455static inline u32 gr_pri_gpcs_gpccs_gpc_activity_1_r(void)
456{
457 return 0x0041ac84U;
458}
459static inline u32 gr_pri_gpcs_gpccs_gpc_activity_2_r(void)
460{
461 return 0x0041ac88U;
462}
463static inline u32 gr_pri_gpcs_gpccs_gpc_activity_3_r(void)
464{
465 return 0x0041ac8cU;
466}
467static inline u32 gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r(void)
468{
469 return 0x0041c500U;
470}
471static inline u32 gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r(void)
472{
473 return 0x00419d00U;
474}
475static inline u32 gr_pri_be0_becs_be_activity0_r(void)
476{
477 return 0x00410200U;
478}
479static inline u32 gr_pri_bes_becs_be_activity0_r(void)
480{
481 return 0x00408a00U;
482}
483static inline u32 gr_pri_ds_mpipe_status_r(void)
484{
485 return 0x00405858U;
486}
487static inline u32 gr_pri_fe_go_idle_on_status_r(void)
488{
489 return 0x00404150U;
490}
491static inline u32 gr_pri_fe_go_idle_check_r(void)
492{
493 return 0x00404158U;
494}
495static inline u32 gr_pri_fe_go_idle_info_r(void)
496{
497 return 0x00404194U;
498}
499static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void)
500{
501 return 0x00504238U;
502}
503static inline u32 gr_pri_be0_crop_status1_r(void)
504{
505 return 0x00410134U;
506}
507static inline u32 gr_pri_bes_crop_status1_r(void)
508{
509 return 0x00408934U;
510}
511static inline u32 gr_pri_be0_zrop_status_r(void)
512{
513 return 0x00410048U;
514}
515static inline u32 gr_pri_be0_zrop_status2_r(void)
516{
517 return 0x0041004cU;
518}
519static inline u32 gr_pri_bes_zrop_status_r(void)
520{
521 return 0x00408848U;
522}
523static inline u32 gr_pri_bes_zrop_status2_r(void)
524{
525 return 0x0040884cU;
526}
527static inline u32 gr_pipe_bundle_address_r(void)
528{
529 return 0x00400200U;
530}
531static inline u32 gr_pipe_bundle_address_value_v(u32 r)
532{
533 return (r >> 0U) & 0xffffU;
534}
535static inline u32 gr_pipe_bundle_data_r(void)
536{
537 return 0x00400204U;
538}
539static inline u32 gr_pipe_bundle_config_r(void)
540{
541 return 0x00400208U;
542}
543static inline u32 gr_pipe_bundle_config_override_pipe_mode_disabled_f(void)
544{
545 return 0x0U;
546}
547static inline u32 gr_pipe_bundle_config_override_pipe_mode_enabled_f(void)
548{
549 return 0x80000000U;
550}
551static inline u32 gr_fe_hww_esr_r(void)
552{
553 return 0x00404000U;
554}
555static inline u32 gr_fe_hww_esr_reset_active_f(void)
556{
557 return 0x40000000U;
558}
559static inline u32 gr_fe_hww_esr_en_enable_f(void)
560{
561 return 0x80000000U;
562}
563static inline u32 gr_fe_hww_esr_info_r(void)
564{
565 return 0x004041b0U;
566}
567static inline u32 gr_fe_go_idle_timeout_r(void)
568{
569 return 0x00404154U;
570}
571static inline u32 gr_fe_go_idle_timeout_count_f(u32 v)
572{
573 return (v & 0xffffffffU) << 0U;
574}
575static inline u32 gr_fe_go_idle_timeout_count_disabled_f(void)
576{
577 return 0x0U;
578}
579static inline u32 gr_fe_go_idle_timeout_count_prod_f(void)
580{
581 return 0x800U;
582}
583static inline u32 gr_fe_object_table_r(u32 i)
584{
585 return 0x00404200U + i*4U;
586}
587static inline u32 gr_fe_object_table_nvclass_v(u32 r)
588{
589 return (r >> 0U) & 0xffffU;
590}
591static inline u32 gr_pri_mme_shadow_raw_index_r(void)
592{
593 return 0x00404488U;
594}
595static inline u32 gr_pri_mme_shadow_raw_index_write_trigger_f(void)
596{
597 return 0x80000000U;
598}
599static inline u32 gr_pri_mme_shadow_raw_data_r(void)
600{
601 return 0x0040448cU;
602}
603static inline u32 gr_mme_hww_esr_r(void)
604{
605 return 0x00404490U;
606}
607static inline u32 gr_mme_hww_esr_reset_active_f(void)
608{
609 return 0x40000000U;
610}
611static inline u32 gr_mme_hww_esr_en_enable_f(void)
612{
613 return 0x80000000U;
614}
615static inline u32 gr_mme_hww_esr_info_r(void)
616{
617 return 0x00404494U;
618}
619static inline u32 gr_memfmt_hww_esr_r(void)
620{
621 return 0x00404600U;
622}
623static inline u32 gr_memfmt_hww_esr_reset_active_f(void)
624{
625 return 0x40000000U;
626}
627static inline u32 gr_memfmt_hww_esr_en_enable_f(void)
628{
629 return 0x80000000U;
630}
631static inline u32 gr_fecs_cpuctl_r(void)
632{
633 return 0x00409100U;
634}
635static inline u32 gr_fecs_cpuctl_startcpu_f(u32 v)
636{
637 return (v & 0x1U) << 1U;
638}
639static inline u32 gr_fecs_dmactl_r(void)
640{
641 return 0x0040910cU;
642}
643static inline u32 gr_fecs_dmactl_require_ctx_f(u32 v)
644{
645 return (v & 0x1U) << 0U;
646}
647static inline u32 gr_fecs_dmactl_dmem_scrubbing_m(void)
648{
649 return 0x1U << 1U;
650}
651static inline u32 gr_fecs_dmactl_imem_scrubbing_m(void)
652{
653 return 0x1U << 2U;
654}
655static inline u32 gr_fecs_os_r(void)
656{
657 return 0x00409080U;
658}
659static inline u32 gr_fecs_idlestate_r(void)
660{
661 return 0x0040904cU;
662}
663static inline u32 gr_fecs_mailbox0_r(void)
664{
665 return 0x00409040U;
666}
667static inline u32 gr_fecs_mailbox1_r(void)
668{
669 return 0x00409044U;
670}
671static inline u32 gr_fecs_irqstat_r(void)
672{
673 return 0x00409008U;
674}
675static inline u32 gr_fecs_irqmode_r(void)
676{
677 return 0x0040900cU;
678}
679static inline u32 gr_fecs_irqmask_r(void)
680{
681 return 0x00409018U;
682}
683static inline u32 gr_fecs_irqdest_r(void)
684{
685 return 0x0040901cU;
686}
687static inline u32 gr_fecs_curctx_r(void)
688{
689 return 0x00409050U;
690}
691static inline u32 gr_fecs_nxtctx_r(void)
692{
693 return 0x00409054U;
694}
695static inline u32 gr_fecs_engctl_r(void)
696{
697 return 0x004090a4U;
698}
699static inline u32 gr_fecs_debug1_r(void)
700{
701 return 0x00409090U;
702}
703static inline u32 gr_fecs_debuginfo_r(void)
704{
705 return 0x00409094U;
706}
707static inline u32 gr_fecs_icd_cmd_r(void)
708{
709 return 0x00409200U;
710}
711static inline u32 gr_fecs_icd_cmd_opc_s(void)
712{
713 return 4U;
714}
715static inline u32 gr_fecs_icd_cmd_opc_f(u32 v)
716{
717 return (v & 0xfU) << 0U;
718}
719static inline u32 gr_fecs_icd_cmd_opc_m(void)
720{
721 return 0xfU << 0U;
722}
723static inline u32 gr_fecs_icd_cmd_opc_v(u32 r)
724{
725 return (r >> 0U) & 0xfU;
726}
727static inline u32 gr_fecs_icd_cmd_opc_rreg_f(void)
728{
729 return 0x8U;
730}
731static inline u32 gr_fecs_icd_cmd_opc_rstat_f(void)
732{
733 return 0xeU;
734}
735static inline u32 gr_fecs_icd_cmd_idx_f(u32 v)
736{
737 return (v & 0x1fU) << 8U;
738}
739static inline u32 gr_fecs_icd_rdata_r(void)
740{
741 return 0x0040920cU;
742}
743static inline u32 gr_fecs_imemc_r(u32 i)
744{
745 return 0x00409180U + i*16U;
746}
747static inline u32 gr_fecs_imemc_offs_f(u32 v)
748{
749 return (v & 0x3fU) << 2U;
750}
751static inline u32 gr_fecs_imemc_blk_f(u32 v)
752{
753 return (v & 0xffU) << 8U;
754}
755static inline u32 gr_fecs_imemc_aincw_f(u32 v)
756{
757 return (v & 0x1U) << 24U;
758}
759static inline u32 gr_fecs_imemd_r(u32 i)
760{
761 return 0x00409184U + i*16U;
762}
763static inline u32 gr_fecs_imemt_r(u32 i)
764{
765 return 0x00409188U + i*16U;
766}
767static inline u32 gr_fecs_imemt_tag_f(u32 v)
768{
769 return (v & 0xffffU) << 0U;
770}
771static inline u32 gr_fecs_dmemc_r(u32 i)
772{
773 return 0x004091c0U + i*8U;
774}
775static inline u32 gr_fecs_dmemc_offs_s(void)
776{
777 return 6U;
778}
779static inline u32 gr_fecs_dmemc_offs_f(u32 v)
780{
781 return (v & 0x3fU) << 2U;
782}
783static inline u32 gr_fecs_dmemc_offs_m(void)
784{
785 return 0x3fU << 2U;
786}
787static inline u32 gr_fecs_dmemc_offs_v(u32 r)
788{
789 return (r >> 2U) & 0x3fU;
790}
791static inline u32 gr_fecs_dmemc_blk_f(u32 v)
792{
793 return (v & 0xffU) << 8U;
794}
795static inline u32 gr_fecs_dmemc_aincw_f(u32 v)
796{
797 return (v & 0x1U) << 24U;
798}
799static inline u32 gr_fecs_dmemd_r(u32 i)
800{
801 return 0x004091c4U + i*8U;
802}
803static inline u32 gr_fecs_dmatrfbase_r(void)
804{
805 return 0x00409110U;
806}
807static inline u32 gr_fecs_dmatrfmoffs_r(void)
808{
809 return 0x00409114U;
810}
811static inline u32 gr_fecs_dmatrffboffs_r(void)
812{
813 return 0x0040911cU;
814}
815static inline u32 gr_fecs_dmatrfcmd_r(void)
816{
817 return 0x00409118U;
818}
819static inline u32 gr_fecs_dmatrfcmd_imem_f(u32 v)
820{
821 return (v & 0x1U) << 4U;
822}
823static inline u32 gr_fecs_dmatrfcmd_write_f(u32 v)
824{
825 return (v & 0x1U) << 5U;
826}
827static inline u32 gr_fecs_dmatrfcmd_size_f(u32 v)
828{
829 return (v & 0x7U) << 8U;
830}
831static inline u32 gr_fecs_dmatrfcmd_ctxdma_f(u32 v)
832{
833 return (v & 0x7U) << 12U;
834}
835static inline u32 gr_fecs_bootvec_r(void)
836{
837 return 0x00409104U;
838}
839static inline u32 gr_fecs_bootvec_vec_f(u32 v)
840{
841 return (v & 0xffffffffU) << 0U;
842}
843static inline u32 gr_fecs_falcon_hwcfg_r(void)
844{
845 return 0x00409108U;
846}
847static inline u32 gr_gpcs_gpccs_falcon_hwcfg_r(void)
848{
849 return 0x0041a108U;
850}
851static inline u32 gr_fecs_falcon_rm_r(void)
852{
853 return 0x00409084U;
854}
855static inline u32 gr_fecs_current_ctx_r(void)
856{
857 return 0x00409b00U;
858}
859static inline u32 gr_fecs_current_ctx_ptr_f(u32 v)
860{
861 return (v & 0xfffffffU) << 0U;
862}
863static inline u32 gr_fecs_current_ctx_ptr_v(u32 r)
864{
865 return (r >> 0U) & 0xfffffffU;
866}
867static inline u32 gr_fecs_current_ctx_target_s(void)
868{
869 return 2U;
870}
871static inline u32 gr_fecs_current_ctx_target_f(u32 v)
872{
873 return (v & 0x3U) << 28U;
874}
875static inline u32 gr_fecs_current_ctx_target_m(void)
876{
877 return 0x3U << 28U;
878}
879static inline u32 gr_fecs_current_ctx_target_v(u32 r)
880{
881 return (r >> 28U) & 0x3U;
882}
883static inline u32 gr_fecs_current_ctx_target_vid_mem_f(void)
884{
885 return 0x0U;
886}
887static inline u32 gr_fecs_current_ctx_target_sys_mem_coh_f(void)
888{
889 return 0x20000000U;
890}
891static inline u32 gr_fecs_current_ctx_target_sys_mem_ncoh_f(void)
892{
893 return 0x30000000U;
894}
895static inline u32 gr_fecs_current_ctx_valid_s(void)
896{
897 return 1U;
898}
899static inline u32 gr_fecs_current_ctx_valid_f(u32 v)
900{
901 return (v & 0x1U) << 31U;
902}
903static inline u32 gr_fecs_current_ctx_valid_m(void)
904{
905 return 0x1U << 31U;
906}
907static inline u32 gr_fecs_current_ctx_valid_v(u32 r)
908{
909 return (r >> 31U) & 0x1U;
910}
911static inline u32 gr_fecs_current_ctx_valid_false_f(void)
912{
913 return 0x0U;
914}
915static inline u32 gr_fecs_method_data_r(void)
916{
917 return 0x00409500U;
918}
919static inline u32 gr_fecs_method_push_r(void)
920{
921 return 0x00409504U;
922}
923static inline u32 gr_fecs_method_push_adr_f(u32 v)
924{
925 return (v & 0xfffU) << 0U;
926}
927static inline u32 gr_fecs_method_push_adr_bind_pointer_v(void)
928{
929 return 0x00000003U;
930}
931static inline u32 gr_fecs_method_push_adr_bind_pointer_f(void)
932{
933 return 0x3U;
934}
935static inline u32 gr_fecs_method_push_adr_discover_image_size_v(void)
936{
937 return 0x00000010U;
938}
939static inline u32 gr_fecs_method_push_adr_wfi_golden_save_v(void)
940{
941 return 0x00000009U;
942}
943static inline u32 gr_fecs_method_push_adr_restore_golden_v(void)
944{
945 return 0x00000015U;
946}
947static inline u32 gr_fecs_method_push_adr_discover_zcull_image_size_v(void)
948{
949 return 0x00000016U;
950}
951static inline u32 gr_fecs_method_push_adr_discover_pm_image_size_v(void)
952{
953 return 0x00000025U;
954}
955static inline u32 gr_fecs_method_push_adr_discover_reglist_image_size_v(void)
956{
957 return 0x00000030U;
958}
959static inline u32 gr_fecs_method_push_adr_set_reglist_bind_instance_v(void)
960{
961 return 0x00000031U;
962}
963static inline u32 gr_fecs_method_push_adr_set_reglist_virtual_address_v(void)
964{
965 return 0x00000032U;
966}
967static inline u32 gr_fecs_method_push_adr_stop_ctxsw_v(void)
968{
969 return 0x00000038U;
970}
971static inline u32 gr_fecs_method_push_adr_start_ctxsw_v(void)
972{
973 return 0x00000039U;
974}
975static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void)
976{
977 return 0x21U;
978}
979static inline u32 gr_fecs_method_push_adr_halt_pipeline_v(void)
980{
981 return 0x00000004U;
982}
983static inline u32 gr_fecs_host_int_status_r(void)
984{
985 return 0x00409c18U;
986}
987static inline u32 gr_fecs_host_int_status_fault_during_ctxsw_f(u32 v)
988{
989 return (v & 0x1U) << 16U;
990}
991static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v)
992{
993 return (v & 0x1U) << 17U;
994}
995static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v)
996{
997 return (v & 0x1U) << 18U;
998}
999static inline u32 gr_fecs_host_int_status_watchdog_active_f(void)
1000{
1001 return 0x80000U;
1002}
1003static inline u32 gr_fecs_host_int_status_ctxsw_intr_f(u32 v)
1004{
1005 return (v & 0xffffU) << 0U;
1006}
1007static inline u32 gr_fecs_host_int_clear_r(void)
1008{
1009 return 0x00409c20U;
1010}
1011static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_f(u32 v)
1012{
1013 return (v & 0x1U) << 1U;
1014}
1015static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_clear_f(void)
1016{
1017 return 0x2U;
1018}
1019static inline u32 gr_fecs_host_int_enable_r(void)
1020{
1021 return 0x00409c24U;
1022}
1023static inline u32 gr_fecs_host_int_enable_ctxsw_intr1_enable_f(void)
1024{
1025 return 0x2U;
1026}
1027static inline u32 gr_fecs_host_int_enable_fault_during_ctxsw_enable_f(void)
1028{
1029 return 0x10000U;
1030}
1031static inline u32 gr_fecs_host_int_enable_umimp_firmware_method_enable_f(void)
1032{
1033 return 0x20000U;
1034}
1035static inline u32 gr_fecs_host_int_enable_umimp_illegal_method_enable_f(void)
1036{
1037 return 0x40000U;
1038}
1039static inline u32 gr_fecs_host_int_enable_watchdog_enable_f(void)
1040{
1041 return 0x80000U;
1042}
1043static inline u32 gr_fecs_ctxsw_reset_ctl_r(void)
1044{
1045 return 0x00409614U;
1046}
1047static inline u32 gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f(void)
1048{
1049 return 0x0U;
1050}
1051static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f(void)
1052{
1053 return 0x0U;
1054}
1055static inline u32 gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f(void)
1056{
1057 return 0x0U;
1058}
1059static inline u32 gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f(void)
1060{
1061 return 0x10U;
1062}
1063static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f(void)
1064{
1065 return 0x20U;
1066}
1067static inline u32 gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f(void)
1068{
1069 return 0x40U;
1070}
1071static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f(void)
1072{
1073 return 0x0U;
1074}
1075static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f(void)
1076{
1077 return 0x100U;
1078}
1079static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f(void)
1080{
1081 return 0x0U;
1082}
1083static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f(void)
1084{
1085 return 0x200U;
1086}
1087static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_s(void)
1088{
1089 return 1U;
1090}
1091static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_f(u32 v)
1092{
1093 return (v & 0x1U) << 10U;
1094}
1095static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_m(void)
1096{
1097 return 0x1U << 10U;
1098}
1099static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_v(u32 r)
1100{
1101 return (r >> 10U) & 0x1U;
1102}
1103static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f(void)
1104{
1105 return 0x0U;
1106}
1107static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f(void)
1108{
1109 return 0x400U;
1110}
1111static inline u32 gr_fecs_ctx_state_store_major_rev_id_r(void)
1112{
1113 return 0x0040960cU;
1114}
1115static inline u32 gr_fecs_ctxsw_mailbox_r(u32 i)
1116{
1117 return 0x00409800U + i*4U;
1118}
1119static inline u32 gr_fecs_ctxsw_mailbox__size_1_v(void)
1120{
1121 return 0x00000008U;
1122}
1123static inline u32 gr_fecs_ctxsw_mailbox_value_f(u32 v)
1124{
1125 return (v & 0xffffffffU) << 0U;
1126}
1127static inline u32 gr_fecs_ctxsw_mailbox_value_pass_v(void)
1128{
1129 return 0x00000001U;
1130}
1131static inline u32 gr_fecs_ctxsw_mailbox_value_fail_v(void)
1132{
1133 return 0x00000002U;
1134}
1135static inline u32 gr_fecs_ctxsw_mailbox_set_r(u32 i)
1136{
1137 return 0x00409820U + i*4U;
1138}
1139static inline u32 gr_fecs_ctxsw_mailbox_set_value_f(u32 v)
1140{
1141 return (v & 0xffffffffU) << 0U;
1142}
1143static inline u32 gr_fecs_ctxsw_mailbox_clear_r(u32 i)
1144{
1145 return 0x00409840U + i*4U;
1146}
1147static inline u32 gr_fecs_ctxsw_mailbox_clear_value_f(u32 v)
1148{
1149 return (v & 0xffffffffU) << 0U;
1150}
1151static inline u32 gr_fecs_fs_r(void)
1152{
1153 return 0x00409604U;
1154}
1155static inline u32 gr_fecs_fs_num_available_gpcs_s(void)
1156{
1157 return 5U;
1158}
1159static inline u32 gr_fecs_fs_num_available_gpcs_f(u32 v)
1160{
1161 return (v & 0x1fU) << 0U;
1162}
1163static inline u32 gr_fecs_fs_num_available_gpcs_m(void)
1164{
1165 return 0x1fU << 0U;
1166}
1167static inline u32 gr_fecs_fs_num_available_gpcs_v(u32 r)
1168{
1169 return (r >> 0U) & 0x1fU;
1170}
1171static inline u32 gr_fecs_fs_num_available_fbps_s(void)
1172{
1173 return 5U;
1174}
1175static inline u32 gr_fecs_fs_num_available_fbps_f(u32 v)
1176{
1177 return (v & 0x1fU) << 16U;
1178}
1179static inline u32 gr_fecs_fs_num_available_fbps_m(void)
1180{
1181 return 0x1fU << 16U;
1182}
1183static inline u32 gr_fecs_fs_num_available_fbps_v(u32 r)
1184{
1185 return (r >> 16U) & 0x1fU;
1186}
1187static inline u32 gr_fecs_cfg_r(void)
1188{
1189 return 0x00409620U;
1190}
1191static inline u32 gr_fecs_cfg_imem_sz_v(u32 r)
1192{
1193 return (r >> 0U) & 0xffU;
1194}
1195static inline u32 gr_fecs_rc_lanes_r(void)
1196{
1197 return 0x00409880U;
1198}
1199static inline u32 gr_fecs_rc_lanes_num_chains_s(void)
1200{
1201 return 6U;
1202}
1203static inline u32 gr_fecs_rc_lanes_num_chains_f(u32 v)
1204{
1205 return (v & 0x3fU) << 0U;
1206}
1207static inline u32 gr_fecs_rc_lanes_num_chains_m(void)
1208{
1209 return 0x3fU << 0U;
1210}
1211static inline u32 gr_fecs_rc_lanes_num_chains_v(u32 r)
1212{
1213 return (r >> 0U) & 0x3fU;
1214}
1215static inline u32 gr_fecs_ctxsw_status_1_r(void)
1216{
1217 return 0x00409400U;
1218}
1219static inline u32 gr_fecs_ctxsw_status_1_arb_busy_s(void)
1220{
1221 return 1U;
1222}
1223static inline u32 gr_fecs_ctxsw_status_1_arb_busy_f(u32 v)
1224{
1225 return (v & 0x1U) << 12U;
1226}
1227static inline u32 gr_fecs_ctxsw_status_1_arb_busy_m(void)
1228{
1229 return 0x1U << 12U;
1230}
1231static inline u32 gr_fecs_ctxsw_status_1_arb_busy_v(u32 r)
1232{
1233 return (r >> 12U) & 0x1U;
1234}
1235static inline u32 gr_fecs_arb_ctx_adr_r(void)
1236{
1237 return 0x00409a24U;
1238}
1239static inline u32 gr_fecs_new_ctx_r(void)
1240{
1241 return 0x00409b04U;
1242}
1243static inline u32 gr_fecs_new_ctx_ptr_s(void)
1244{
1245 return 28U;
1246}
1247static inline u32 gr_fecs_new_ctx_ptr_f(u32 v)
1248{
1249 return (v & 0xfffffffU) << 0U;
1250}
1251static inline u32 gr_fecs_new_ctx_ptr_m(void)
1252{
1253 return 0xfffffffU << 0U;
1254}
1255static inline u32 gr_fecs_new_ctx_ptr_v(u32 r)
1256{
1257 return (r >> 0U) & 0xfffffffU;
1258}
1259static inline u32 gr_fecs_new_ctx_target_s(void)
1260{
1261 return 2U;
1262}
1263static inline u32 gr_fecs_new_ctx_target_f(u32 v)
1264{
1265 return (v & 0x3U) << 28U;
1266}
1267static inline u32 gr_fecs_new_ctx_target_m(void)
1268{
1269 return 0x3U << 28U;
1270}
1271static inline u32 gr_fecs_new_ctx_target_v(u32 r)
1272{
1273 return (r >> 28U) & 0x3U;
1274}
1275static inline u32 gr_fecs_new_ctx_target_vid_mem_f(void)
1276{
1277 return 0x0U;
1278}
1279static inline u32 gr_fecs_new_ctx_target_sys_mem_ncoh_f(void)
1280{
1281 return 0x30000000U;
1282}
1283static inline u32 gr_fecs_new_ctx_target_sys_mem_coh_f(void)
1284{
1285 return 0x20000000U;
1286}
1287static inline u32 gr_fecs_new_ctx_valid_s(void)
1288{
1289 return 1U;
1290}
1291static inline u32 gr_fecs_new_ctx_valid_f(u32 v)
1292{
1293 return (v & 0x1U) << 31U;
1294}
1295static inline u32 gr_fecs_new_ctx_valid_m(void)
1296{
1297 return 0x1U << 31U;
1298}
1299static inline u32 gr_fecs_new_ctx_valid_v(u32 r)
1300{
1301 return (r >> 31U) & 0x1U;
1302}
1303static inline u32 gr_fecs_arb_ctx_ptr_r(void)
1304{
1305 return 0x00409a0cU;
1306}
1307static inline u32 gr_fecs_arb_ctx_ptr_ptr_s(void)
1308{
1309 return 28U;
1310}
1311static inline u32 gr_fecs_arb_ctx_ptr_ptr_f(u32 v)
1312{
1313 return (v & 0xfffffffU) << 0U;
1314}
1315static inline u32 gr_fecs_arb_ctx_ptr_ptr_m(void)
1316{
1317 return 0xfffffffU << 0U;
1318}
1319static inline u32 gr_fecs_arb_ctx_ptr_ptr_v(u32 r)
1320{
1321 return (r >> 0U) & 0xfffffffU;
1322}
1323static inline u32 gr_fecs_arb_ctx_ptr_target_s(void)
1324{
1325 return 2U;
1326}
1327static inline u32 gr_fecs_arb_ctx_ptr_target_f(u32 v)
1328{
1329 return (v & 0x3U) << 28U;
1330}
1331static inline u32 gr_fecs_arb_ctx_ptr_target_m(void)
1332{
1333 return 0x3U << 28U;
1334}
1335static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r)
1336{
1337 return (r >> 28U) & 0x3U;
1338}
1339static inline u32 gr_fecs_arb_ctx_ptr_target_vid_mem_f(void)
1340{
1341 return 0x0U;
1342}
1343static inline u32 gr_fecs_arb_ctx_ptr_target_sys_mem_ncoh_f(void)
1344{
1345 return 0x30000000U;
1346}
1347static inline u32 gr_fecs_arb_ctx_ptr_target_sys_mem_coh_f(void)
1348{
1349 return 0x20000000U;
1350}
1351static inline u32 gr_fecs_arb_ctx_cmd_r(void)
1352{
1353 return 0x00409a10U;
1354}
1355static inline u32 gr_fecs_arb_ctx_cmd_cmd_s(void)
1356{
1357 return 5U;
1358}
1359static inline u32 gr_fecs_arb_ctx_cmd_cmd_f(u32 v)
1360{
1361 return (v & 0x1fU) << 0U;
1362}
1363static inline u32 gr_fecs_arb_ctx_cmd_cmd_m(void)
1364{
1365 return 0x1fU << 0U;
1366}
1367static inline u32 gr_fecs_arb_ctx_cmd_cmd_v(u32 r)
1368{
1369 return (r >> 0U) & 0x1fU;
1370}
1371static inline u32 gr_fecs_ctxsw_status_fe_0_r(void)
1372{
1373 return 0x00409c00U;
1374}
1375static inline u32 gr_gpc0_gpccs_ctxsw_status_gpc_0_r(void)
1376{
1377 return 0x00502c04U;
1378}
1379static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void)
1380{
1381 return 0x00502400U;
1382}
1383static inline u32 gr_gpc0_gpccs_ctxsw_mailbox__size_1_v(void)
1384{
1385 return 0x00000010U;
1386}
1387static inline u32 gr_fecs_ctxsw_idlestate_r(void)
1388{
1389 return 0x00409420U;
1390}
1391static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void)
1392{
1393 return 0x00502420U;
1394}
1395static inline u32 gr_rstr2d_gpc_map0_r(void)
1396{
1397 return 0x0040780cU;
1398}
1399static inline u32 gr_rstr2d_gpc_map1_r(void)
1400{
1401 return 0x00407810U;
1402}
1403static inline u32 gr_rstr2d_gpc_map2_r(void)
1404{
1405 return 0x00407814U;
1406}
1407static inline u32 gr_rstr2d_gpc_map3_r(void)
1408{
1409 return 0x00407818U;
1410}
1411static inline u32 gr_rstr2d_gpc_map4_r(void)
1412{
1413 return 0x0040781cU;
1414}
1415static inline u32 gr_rstr2d_gpc_map5_r(void)
1416{
1417 return 0x00407820U;
1418}
1419static inline u32 gr_rstr2d_map_table_cfg_r(void)
1420{
1421 return 0x004078bcU;
1422}
1423static inline u32 gr_rstr2d_map_table_cfg_row_offset_f(u32 v)
1424{
1425 return (v & 0xffU) << 0U;
1426}
1427static inline u32 gr_rstr2d_map_table_cfg_num_entries_f(u32 v)
1428{
1429 return (v & 0xffU) << 8U;
1430}
1431static inline u32 gr_pd_hww_esr_r(void)
1432{
1433 return 0x00406018U;
1434}
1435static inline u32 gr_pd_hww_esr_reset_active_f(void)
1436{
1437 return 0x40000000U;
1438}
1439static inline u32 gr_pd_hww_esr_en_enable_f(void)
1440{
1441 return 0x80000000U;
1442}
1443static inline u32 gr_pd_num_tpc_per_gpc_r(u32 i)
1444{
1445 return 0x00406028U + i*4U;
1446}
1447static inline u32 gr_pd_num_tpc_per_gpc__size_1_v(void)
1448{
1449 return 0x00000004U;
1450}
1451static inline u32 gr_pd_num_tpc_per_gpc_count0_f(u32 v)
1452{
1453 return (v & 0xfU) << 0U;
1454}
1455static inline u32 gr_pd_num_tpc_per_gpc_count1_f(u32 v)
1456{
1457 return (v & 0xfU) << 4U;
1458}
1459static inline u32 gr_pd_num_tpc_per_gpc_count2_f(u32 v)
1460{
1461 return (v & 0xfU) << 8U;
1462}
1463static inline u32 gr_pd_num_tpc_per_gpc_count3_f(u32 v)
1464{
1465 return (v & 0xfU) << 12U;
1466}
1467static inline u32 gr_pd_num_tpc_per_gpc_count4_f(u32 v)
1468{
1469 return (v & 0xfU) << 16U;
1470}
1471static inline u32 gr_pd_num_tpc_per_gpc_count5_f(u32 v)
1472{
1473 return (v & 0xfU) << 20U;
1474}
1475static inline u32 gr_pd_num_tpc_per_gpc_count6_f(u32 v)
1476{
1477 return (v & 0xfU) << 24U;
1478}
1479static inline u32 gr_pd_num_tpc_per_gpc_count7_f(u32 v)
1480{
1481 return (v & 0xfU) << 28U;
1482}
1483static inline u32 gr_pd_ab_dist_cfg0_r(void)
1484{
1485 return 0x004064c0U;
1486}
1487static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_en_f(void)
1488{
1489 return 0x80000000U;
1490}
1491static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_dis_f(void)
1492{
1493 return 0x0U;
1494}
1495static inline u32 gr_pd_ab_dist_cfg1_r(void)
1496{
1497 return 0x004064c4U;
1498}
1499static inline u32 gr_pd_ab_dist_cfg1_max_batches_init_f(void)
1500{
1501 return 0xffffU;
1502}
1503static inline u32 gr_pd_ab_dist_cfg1_max_output_f(u32 v)
1504{
1505 return (v & 0x7ffU) << 16U;
1506}
1507static inline u32 gr_pd_ab_dist_cfg1_max_output_granularity_v(void)
1508{
1509 return 0x00000080U;
1510}
1511static inline u32 gr_pd_ab_dist_cfg2_r(void)
1512{
1513 return 0x004064c8U;
1514}
1515static inline u32 gr_pd_ab_dist_cfg2_token_limit_f(u32 v)
1516{
1517 return (v & 0xfffU) << 0U;
1518}
1519static inline u32 gr_pd_ab_dist_cfg2_token_limit_init_v(void)
1520{
1521 return 0x00000100U;
1522}
1523static inline u32 gr_pd_ab_dist_cfg2_state_limit_f(u32 v)
1524{
1525 return (v & 0xfffU) << 16U;
1526}
1527static inline u32 gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(void)
1528{
1529 return 0x00000020U;
1530}
1531static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void)
1532{
1533 return 0x00000062U;
1534}
1535static inline u32 gr_pd_pagepool_r(void)
1536{
1537 return 0x004064ccU;
1538}
1539static inline u32 gr_pd_pagepool_total_pages_f(u32 v)
1540{
1541 return (v & 0xffU) << 0U;
1542}
1543static inline u32 gr_pd_pagepool_valid_true_f(void)
1544{
1545 return 0x80000000U;
1546}
1547static inline u32 gr_pd_dist_skip_table_r(u32 i)
1548{
1549 return 0x004064d0U + i*4U;
1550}
1551static inline u32 gr_pd_dist_skip_table__size_1_v(void)
1552{
1553 return 0x00000008U;
1554}
1555static inline u32 gr_pd_dist_skip_table_gpc_4n0_mask_f(u32 v)
1556{
1557 return (v & 0xffU) << 0U;
1558}
1559static inline u32 gr_pd_dist_skip_table_gpc_4n1_mask_f(u32 v)
1560{
1561 return (v & 0xffU) << 8U;
1562}
1563static inline u32 gr_pd_dist_skip_table_gpc_4n2_mask_f(u32 v)
1564{
1565 return (v & 0xffU) << 16U;
1566}
1567static inline u32 gr_pd_dist_skip_table_gpc_4n3_mask_f(u32 v)
1568{
1569 return (v & 0xffU) << 24U;
1570}
1571static inline u32 gr_pd_alpha_ratio_table_r(u32 i)
1572{
1573 return 0x00406800U + i*4U;
1574}
1575static inline u32 gr_pd_alpha_ratio_table__size_1_v(void)
1576{
1577 return 0x00000100U;
1578}
1579static inline u32 gr_pd_alpha_ratio_table_gpc_4n0_mask_f(u32 v)
1580{
1581 return (v & 0xffU) << 0U;
1582}
1583static inline u32 gr_pd_alpha_ratio_table_gpc_4n1_mask_f(u32 v)
1584{
1585 return (v & 0xffU) << 8U;
1586}
1587static inline u32 gr_pd_alpha_ratio_table_gpc_4n2_mask_f(u32 v)
1588{
1589 return (v & 0xffU) << 16U;
1590}
1591static inline u32 gr_pd_alpha_ratio_table_gpc_4n3_mask_f(u32 v)
1592{
1593 return (v & 0xffU) << 24U;
1594}
1595static inline u32 gr_pd_beta_ratio_table_r(u32 i)
1596{
1597 return 0x00406c00U + i*4U;
1598}
1599static inline u32 gr_pd_beta_ratio_table__size_1_v(void)
1600{
1601 return 0x00000100U;
1602}
1603static inline u32 gr_pd_beta_ratio_table_gpc_4n0_mask_f(u32 v)
1604{
1605 return (v & 0xffU) << 0U;
1606}
1607static inline u32 gr_pd_beta_ratio_table_gpc_4n1_mask_f(u32 v)
1608{
1609 return (v & 0xffU) << 8U;
1610}
1611static inline u32 gr_pd_beta_ratio_table_gpc_4n2_mask_f(u32 v)
1612{
1613 return (v & 0xffU) << 16U;
1614}
1615static inline u32 gr_pd_beta_ratio_table_gpc_4n3_mask_f(u32 v)
1616{
1617 return (v & 0xffU) << 24U;
1618}
1619static inline u32 gr_ds_debug_r(void)
1620{
1621 return 0x00405800U;
1622}
1623static inline u32 gr_ds_debug_timeslice_mode_disable_f(void)
1624{
1625 return 0x0U;
1626}
1627static inline u32 gr_ds_debug_timeslice_mode_enable_f(void)
1628{
1629 return 0x8000000U;
1630}
1631static inline u32 gr_ds_zbc_color_r_r(void)
1632{
1633 return 0x00405804U;
1634}
1635static inline u32 gr_ds_zbc_color_r_val_f(u32 v)
1636{
1637 return (v & 0xffffffffU) << 0U;
1638}
1639static inline u32 gr_ds_zbc_color_g_r(void)
1640{
1641 return 0x00405808U;
1642}
1643static inline u32 gr_ds_zbc_color_g_val_f(u32 v)
1644{
1645 return (v & 0xffffffffU) << 0U;
1646}
1647static inline u32 gr_ds_zbc_color_b_r(void)
1648{
1649 return 0x0040580cU;
1650}
1651static inline u32 gr_ds_zbc_color_b_val_f(u32 v)
1652{
1653 return (v & 0xffffffffU) << 0U;
1654}
1655static inline u32 gr_ds_zbc_color_a_r(void)
1656{
1657 return 0x00405810U;
1658}
1659static inline u32 gr_ds_zbc_color_a_val_f(u32 v)
1660{
1661 return (v & 0xffffffffU) << 0U;
1662}
1663static inline u32 gr_ds_zbc_color_fmt_r(void)
1664{
1665 return 0x00405814U;
1666}
1667static inline u32 gr_ds_zbc_color_fmt_val_f(u32 v)
1668{
1669 return (v & 0x7fU) << 0U;
1670}
1671static inline u32 gr_ds_zbc_color_fmt_val_invalid_f(void)
1672{
1673 return 0x0U;
1674}
1675static inline u32 gr_ds_zbc_color_fmt_val_zero_v(void)
1676{
1677 return 0x00000001U;
1678}
1679static inline u32 gr_ds_zbc_color_fmt_val_unorm_one_v(void)
1680{
1681 return 0x00000002U;
1682}
1683static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void)
1684{
1685 return 0x00000004U;
1686}
1687static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void)
1688{
1689 return 0x00000028U;
1690}
1691static inline u32 gr_ds_zbc_z_r(void)
1692{
1693 return 0x00405818U;
1694}
1695static inline u32 gr_ds_zbc_z_val_s(void)
1696{
1697 return 32U;
1698}
1699static inline u32 gr_ds_zbc_z_val_f(u32 v)
1700{
1701 return (v & 0xffffffffU) << 0U;
1702}
1703static inline u32 gr_ds_zbc_z_val_m(void)
1704{
1705 return 0xffffffffU << 0U;
1706}
1707static inline u32 gr_ds_zbc_z_val_v(u32 r)
1708{
1709 return (r >> 0U) & 0xffffffffU;
1710}
1711static inline u32 gr_ds_zbc_z_val__init_v(void)
1712{
1713 return 0x00000000U;
1714}
1715static inline u32 gr_ds_zbc_z_val__init_f(void)
1716{
1717 return 0x0U;
1718}
1719static inline u32 gr_ds_zbc_z_fmt_r(void)
1720{
1721 return 0x0040581cU;
1722}
1723static inline u32 gr_ds_zbc_z_fmt_val_f(u32 v)
1724{
1725 return (v & 0x1U) << 0U;
1726}
1727static inline u32 gr_ds_zbc_z_fmt_val_invalid_f(void)
1728{
1729 return 0x0U;
1730}
1731static inline u32 gr_ds_zbc_z_fmt_val_fp32_v(void)
1732{
1733 return 0x00000001U;
1734}
1735static inline u32 gr_ds_zbc_tbl_index_r(void)
1736{
1737 return 0x00405820U;
1738}
1739static inline u32 gr_ds_zbc_tbl_index_val_f(u32 v)
1740{
1741 return (v & 0xfU) << 0U;
1742}
1743static inline u32 gr_ds_zbc_tbl_ld_r(void)
1744{
1745 return 0x00405824U;
1746}
1747static inline u32 gr_ds_zbc_tbl_ld_select_c_f(void)
1748{
1749 return 0x0U;
1750}
1751static inline u32 gr_ds_zbc_tbl_ld_select_z_f(void)
1752{
1753 return 0x1U;
1754}
1755static inline u32 gr_ds_zbc_tbl_ld_action_write_f(void)
1756{
1757 return 0x0U;
1758}
1759static inline u32 gr_ds_zbc_tbl_ld_trigger_active_f(void)
1760{
1761 return 0x4U;
1762}
1763static inline u32 gr_ds_tga_constraintlogic_r(void)
1764{
1765 return 0x00405830U;
1766}
1767static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v)
1768{
1769 return (v & 0xfffU) << 16U;
1770}
1771static inline u32 gr_ds_tga_constraintlogic_alpha_cbsize_f(u32 v)
1772{
1773 return (v & 0xfffU) << 0U;
1774}
1775static inline u32 gr_ds_hww_esr_r(void)
1776{
1777 return 0x00405840U;
1778}
1779static inline u32 gr_ds_hww_esr_reset_s(void)
1780{
1781 return 1U;
1782}
1783static inline u32 gr_ds_hww_esr_reset_f(u32 v)
1784{
1785 return (v & 0x1U) << 30U;
1786}
1787static inline u32 gr_ds_hww_esr_reset_m(void)
1788{
1789 return 0x1U << 30U;
1790}
1791static inline u32 gr_ds_hww_esr_reset_v(u32 r)
1792{
1793 return (r >> 30U) & 0x1U;
1794}
1795static inline u32 gr_ds_hww_esr_reset_task_v(void)
1796{
1797 return 0x00000001U;
1798}
1799static inline u32 gr_ds_hww_esr_reset_task_f(void)
1800{
1801 return 0x40000000U;
1802}
1803static inline u32 gr_ds_hww_esr_en_enabled_f(void)
1804{
1805 return 0x80000000U;
1806}
1807static inline u32 gr_ds_hww_report_mask_r(void)
1808{
1809 return 0x00405844U;
1810}
1811static inline u32 gr_ds_hww_report_mask_sph0_err_report_f(void)
1812{
1813 return 0x1U;
1814}
1815static inline u32 gr_ds_hww_report_mask_sph1_err_report_f(void)
1816{
1817 return 0x2U;
1818}
1819static inline u32 gr_ds_hww_report_mask_sph2_err_report_f(void)
1820{
1821 return 0x4U;
1822}
1823static inline u32 gr_ds_hww_report_mask_sph3_err_report_f(void)
1824{
1825 return 0x8U;
1826}
1827static inline u32 gr_ds_hww_report_mask_sph4_err_report_f(void)
1828{
1829 return 0x10U;
1830}
1831static inline u32 gr_ds_hww_report_mask_sph5_err_report_f(void)
1832{
1833 return 0x20U;
1834}
1835static inline u32 gr_ds_hww_report_mask_sph6_err_report_f(void)
1836{
1837 return 0x40U;
1838}
1839static inline u32 gr_ds_hww_report_mask_sph7_err_report_f(void)
1840{
1841 return 0x80U;
1842}
1843static inline u32 gr_ds_hww_report_mask_sph8_err_report_f(void)
1844{
1845 return 0x100U;
1846}
1847static inline u32 gr_ds_hww_report_mask_sph9_err_report_f(void)
1848{
1849 return 0x200U;
1850}
1851static inline u32 gr_ds_hww_report_mask_sph10_err_report_f(void)
1852{
1853 return 0x400U;
1854}
1855static inline u32 gr_ds_hww_report_mask_sph11_err_report_f(void)
1856{
1857 return 0x800U;
1858}
1859static inline u32 gr_ds_hww_report_mask_sph12_err_report_f(void)
1860{
1861 return 0x1000U;
1862}
1863static inline u32 gr_ds_hww_report_mask_sph13_err_report_f(void)
1864{
1865 return 0x2000U;
1866}
1867static inline u32 gr_ds_hww_report_mask_sph14_err_report_f(void)
1868{
1869 return 0x4000U;
1870}
1871static inline u32 gr_ds_hww_report_mask_sph15_err_report_f(void)
1872{
1873 return 0x8000U;
1874}
1875static inline u32 gr_ds_hww_report_mask_sph16_err_report_f(void)
1876{
1877 return 0x10000U;
1878}
1879static inline u32 gr_ds_hww_report_mask_sph17_err_report_f(void)
1880{
1881 return 0x20000U;
1882}
1883static inline u32 gr_ds_hww_report_mask_sph18_err_report_f(void)
1884{
1885 return 0x40000U;
1886}
1887static inline u32 gr_ds_hww_report_mask_sph19_err_report_f(void)
1888{
1889 return 0x80000U;
1890}
1891static inline u32 gr_ds_hww_report_mask_sph20_err_report_f(void)
1892{
1893 return 0x100000U;
1894}
1895static inline u32 gr_ds_hww_report_mask_sph21_err_report_f(void)
1896{
1897 return 0x200000U;
1898}
1899static inline u32 gr_ds_hww_report_mask_sph22_err_report_f(void)
1900{
1901 return 0x400000U;
1902}
1903static inline u32 gr_ds_hww_report_mask_sph23_err_report_f(void)
1904{
1905 return 0x800000U;
1906}
1907static inline u32 gr_ds_num_tpc_per_gpc_r(u32 i)
1908{
1909 return 0x00405870U + i*4U;
1910}
1911static inline u32 gr_scc_bundle_cb_base_r(void)
1912{
1913 return 0x00408004U;
1914}
1915static inline u32 gr_scc_bundle_cb_base_addr_39_8_f(u32 v)
1916{
1917 return (v & 0xffffffffU) << 0U;
1918}
1919static inline u32 gr_scc_bundle_cb_base_addr_39_8_align_bits_v(void)
1920{
1921 return 0x00000008U;
1922}
1923static inline u32 gr_scc_bundle_cb_size_r(void)
1924{
1925 return 0x00408008U;
1926}
1927static inline u32 gr_scc_bundle_cb_size_div_256b_f(u32 v)
1928{
1929 return (v & 0x7ffU) << 0U;
1930}
1931static inline u32 gr_scc_bundle_cb_size_div_256b__prod_v(void)
1932{
1933 return 0x00000018U;
1934}
1935static inline u32 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(void)
1936{
1937 return 0x00000100U;
1938}
1939static inline u32 gr_scc_bundle_cb_size_valid_false_v(void)
1940{
1941 return 0x00000000U;
1942}
1943static inline u32 gr_scc_bundle_cb_size_valid_false_f(void)
1944{
1945 return 0x0U;
1946}
1947static inline u32 gr_scc_bundle_cb_size_valid_true_f(void)
1948{
1949 return 0x80000000U;
1950}
1951static inline u32 gr_scc_pagepool_base_r(void)
1952{
1953 return 0x0040800cU;
1954}
1955static inline u32 gr_scc_pagepool_base_addr_39_8_f(u32 v)
1956{
1957 return (v & 0xffffffffU) << 0U;
1958}
1959static inline u32 gr_scc_pagepool_base_addr_39_8_align_bits_v(void)
1960{
1961 return 0x00000008U;
1962}
1963static inline u32 gr_scc_pagepool_r(void)
1964{
1965 return 0x00408010U;
1966}
1967static inline u32 gr_scc_pagepool_total_pages_f(u32 v)
1968{
1969 return (v & 0xffU) << 0U;
1970}
1971static inline u32 gr_scc_pagepool_total_pages_hwmax_v(void)
1972{
1973 return 0x00000000U;
1974}
1975static inline u32 gr_scc_pagepool_total_pages_hwmax_value_v(void)
1976{
1977 return 0x00000080U;
1978}
1979static inline u32 gr_scc_pagepool_total_pages_byte_granularity_v(void)
1980{
1981 return 0x00000100U;
1982}
1983static inline u32 gr_scc_pagepool_max_valid_pages_s(void)
1984{
1985 return 8U;
1986}
1987static inline u32 gr_scc_pagepool_max_valid_pages_f(u32 v)
1988{
1989 return (v & 0xffU) << 8U;
1990}
1991static inline u32 gr_scc_pagepool_max_valid_pages_m(void)
1992{
1993 return 0xffU << 8U;
1994}
1995static inline u32 gr_scc_pagepool_max_valid_pages_v(u32 r)
1996{
1997 return (r >> 8U) & 0xffU;
1998}
1999static inline u32 gr_scc_pagepool_valid_true_f(void)
2000{
2001 return 0x80000000U;
2002}
2003static inline u32 gr_scc_init_r(void)
2004{
2005 return 0x0040802cU;
2006}
2007static inline u32 gr_scc_init_ram_trigger_f(void)
2008{
2009 return 0x1U;
2010}
2011static inline u32 gr_scc_hww_esr_r(void)
2012{
2013 return 0x00408030U;
2014}
2015static inline u32 gr_scc_hww_esr_reset_active_f(void)
2016{
2017 return 0x40000000U;
2018}
2019static inline u32 gr_scc_hww_esr_en_enable_f(void)
2020{
2021 return 0x80000000U;
2022}
2023static inline u32 gr_sked_hww_esr_r(void)
2024{
2025 return 0x00407020U;
2026}
2027static inline u32 gr_sked_hww_esr_reset_active_f(void)
2028{
2029 return 0x40000000U;
2030}
2031static inline u32 gr_cwd_fs_r(void)
2032{
2033 return 0x00405b00U;
2034}
2035static inline u32 gr_cwd_fs_num_gpcs_f(u32 v)
2036{
2037 return (v & 0xffU) << 0U;
2038}
2039static inline u32 gr_cwd_fs_num_tpcs_f(u32 v)
2040{
2041 return (v & 0xffU) << 8U;
2042}
2043static inline u32 gr_gpc0_fs_gpc_r(void)
2044{
2045 return 0x00502608U;
2046}
2047static inline u32 gr_gpc0_fs_gpc_num_available_tpcs_v(u32 r)
2048{
2049 return (r >> 0U) & 0x1fU;
2050}
2051static inline u32 gr_gpc0_fs_gpc_num_available_zculls_v(u32 r)
2052{
2053 return (r >> 16U) & 0x1fU;
2054}
2055static inline u32 gr_gpc0_cfg_r(void)
2056{
2057 return 0x00502620U;
2058}
2059static inline u32 gr_gpc0_cfg_imem_sz_v(u32 r)
2060{
2061 return (r >> 0U) & 0xffU;
2062}
2063static inline u32 gr_gpccs_rc_lanes_r(void)
2064{
2065 return 0x00502880U;
2066}
2067static inline u32 gr_gpccs_rc_lanes_num_chains_s(void)
2068{
2069 return 6U;
2070}
2071static inline u32 gr_gpccs_rc_lanes_num_chains_f(u32 v)
2072{
2073 return (v & 0x3fU) << 0U;
2074}
2075static inline u32 gr_gpccs_rc_lanes_num_chains_m(void)
2076{
2077 return 0x3fU << 0U;
2078}
2079static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r)
2080{
2081 return (r >> 0U) & 0x3fU;
2082}
2083static inline u32 gr_gpccs_rc_lane_size_r(u32 i)
2084{
2085 return 0x00502910U + i*0U;
2086}
2087static inline u32 gr_gpccs_rc_lane_size__size_1_v(void)
2088{
2089 return 0x00000010U;
2090}
2091static inline u32 gr_gpccs_rc_lane_size_v_s(void)
2092{
2093 return 24U;
2094}
2095static inline u32 gr_gpccs_rc_lane_size_v_f(u32 v)
2096{
2097 return (v & 0xffffffU) << 0U;
2098}
2099static inline u32 gr_gpccs_rc_lane_size_v_m(void)
2100{
2101 return 0xffffffU << 0U;
2102}
2103static inline u32 gr_gpccs_rc_lane_size_v_v(u32 r)
2104{
2105 return (r >> 0U) & 0xffffffU;
2106}
2107static inline u32 gr_gpccs_rc_lane_size_v_0_v(void)
2108{
2109 return 0x00000000U;
2110}
2111static inline u32 gr_gpccs_rc_lane_size_v_0_f(void)
2112{
2113 return 0x0U;
2114}
2115static inline u32 gr_gpc0_zcull_fs_r(void)
2116{
2117 return 0x00500910U;
2118}
2119static inline u32 gr_gpc0_zcull_fs_num_sms_f(u32 v)
2120{
2121 return (v & 0x1ffU) << 0U;
2122}
2123static inline u32 gr_gpc0_zcull_fs_num_active_banks_f(u32 v)
2124{
2125 return (v & 0xfU) << 16U;
2126}
2127static inline u32 gr_gpc0_zcull_ram_addr_r(void)
2128{
2129 return 0x00500914U;
2130}
2131static inline u32 gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(u32 v)
2132{
2133 return (v & 0xfU) << 0U;
2134}
2135static inline u32 gr_gpc0_zcull_ram_addr_row_offset_f(u32 v)
2136{
2137 return (v & 0xfU) << 8U;
2138}
2139static inline u32 gr_gpc0_zcull_sm_num_rcp_r(void)
2140{
2141 return 0x00500918U;
2142}
2143static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative_f(u32 v)
2144{
2145 return (v & 0xffffffU) << 0U;
2146}
2147static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative__max_v(void)
2148{
2149 return 0x00800000U;
2150}
2151static inline u32 gr_gpc0_zcull_total_ram_size_r(void)
2152{
2153 return 0x00500920U;
2154}
2155static inline u32 gr_gpc0_zcull_total_ram_size_num_aliquots_f(u32 v)
2156{
2157 return (v & 0xffffU) << 0U;
2158}
2159static inline u32 gr_gpc0_zcull_zcsize_r(u32 i)
2160{
2161 return 0x00500a04U + i*32U;
2162}
2163static inline u32 gr_gpc0_zcull_zcsize_height_subregion__multiple_v(void)
2164{
2165 return 0x00000040U;
2166}
2167static inline u32 gr_gpc0_zcull_zcsize_width_subregion__multiple_v(void)
2168{
2169 return 0x00000010U;
2170}
2171static inline u32 gr_gpc0_gpm_pd_active_tpcs_r(void)
2172{
2173 return 0x00500c08U;
2174}
2175static inline u32 gr_gpc0_gpm_pd_active_tpcs_num_f(u32 v)
2176{
2177 return (v & 0x7U) << 0U;
2178}
2179static inline u32 gr_gpc0_gpm_pd_sm_id_r(u32 i)
2180{
2181 return 0x00500c10U + i*4U;
2182}
2183static inline u32 gr_gpc0_gpm_pd_sm_id_id_f(u32 v)
2184{
2185 return (v & 0xffU) << 0U;
2186}
2187static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_r(u32 i)
2188{
2189 return 0x00500c30U + i*4U;
2190}
2191static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(u32 r)
2192{
2193 return (r >> 0U) & 0xffU;
2194}
2195static inline u32 gr_gpc0_gpm_sd_active_tpcs_r(void)
2196{
2197 return 0x00500c8cU;
2198}
2199static inline u32 gr_gpc0_gpm_sd_active_tpcs_num_f(u32 v)
2200{
2201 return (v & 0x7U) << 0U;
2202}
2203static inline u32 gr_gpc0_tpc0_pe_cfg_smid_r(void)
2204{
2205 return 0x00504088U;
2206}
2207static inline u32 gr_gpc0_tpc0_pe_cfg_smid_value_f(u32 v)
2208{
2209 return (v & 0xffffU) << 0U;
2210}
2211static inline u32 gr_gpc0_tpc0_l1c_cfg_smid_r(void)
2212{
2213 return 0x005044e8U;
2214}
2215static inline u32 gr_gpc0_tpc0_l1c_cfg_smid_value_f(u32 v)
2216{
2217 return (v & 0xffffU) << 0U;
2218}
2219static inline u32 gr_gpc0_tpc0_sm_cfg_r(void)
2220{
2221 return 0x00504698U;
2222}
2223static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_f(u32 v)
2224{
2225 return (v & 0xffffU) << 0U;
2226}
2227static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_v(u32 r)
2228{
2229 return (r >> 0U) & 0xffffU;
2230}
2231static inline u32 gr_gpc0_tpc0_sm_arch_r(void)
2232{
2233 return 0x0050469cU;
2234}
2235static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r)
2236{
2237 return (r >> 0U) & 0xffU;
2238}
2239static inline u32 gr_gpc0_tpc0_sm_arch_spa_version_v(u32 r)
2240{
2241 return (r >> 8U) & 0xfU;
2242}
2243static inline u32 gr_gpc0_tpc0_sm_arch_spa_version_smkepler_lp_v(void)
2244{
2245 return 0x0000000cU;
2246}
2247static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void)
2248{
2249 return 0x00503018U;
2250}
2251static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_m(void)
2252{
2253 return 0x1U << 0U;
2254}
2255static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f(void)
2256{
2257 return 0x1U;
2258}
2259static inline u32 gr_gpc0_ppc0_cbm_cfg_r(void)
2260{
2261 return 0x005030c0U;
2262}
2263static inline u32 gr_gpc0_ppc0_cbm_cfg_start_offset_f(u32 v)
2264{
2265 return (v & 0xffffU) << 0U;
2266}
2267static inline u32 gr_gpc0_ppc0_cbm_cfg_start_offset_m(void)
2268{
2269 return 0xffffU << 0U;
2270}
2271static inline u32 gr_gpc0_ppc0_cbm_cfg_start_offset_v(u32 r)
2272{
2273 return (r >> 0U) & 0xffffU;
2274}
2275static inline u32 gr_gpc0_ppc0_cbm_cfg_size_f(u32 v)
2276{
2277 return (v & 0xfffU) << 16U;
2278}
2279static inline u32 gr_gpc0_ppc0_cbm_cfg_size_m(void)
2280{
2281 return 0xfffU << 16U;
2282}
2283static inline u32 gr_gpc0_ppc0_cbm_cfg_size_v(u32 r)
2284{
2285 return (r >> 16U) & 0xfffU;
2286}
2287static inline u32 gr_gpc0_ppc0_cbm_cfg_size_default_v(void)
2288{
2289 return 0x00000240U;
2290}
2291static inline u32 gr_gpc0_ppc0_cbm_cfg_size_granularity_v(void)
2292{
2293 return 0x00000020U;
2294}
2295static inline u32 gr_gpc0_ppc0_cbm_cfg_timeslice_mode_f(u32 v)
2296{
2297 return (v & 0x1U) << 28U;
2298}
2299static inline u32 gr_gpc0_ppc0_cbm_cfg2_r(void)
2300{
2301 return 0x005030e4U;
2302}
2303static inline u32 gr_gpc0_ppc0_cbm_cfg2_start_offset_f(u32 v)
2304{
2305 return (v & 0xffffU) << 0U;
2306}
2307static inline u32 gr_gpc0_ppc0_cbm_cfg2_size_f(u32 v)
2308{
2309 return (v & 0xfffU) << 16U;
2310}
2311static inline u32 gr_gpc0_ppc0_cbm_cfg2_size_m(void)
2312{
2313 return 0xfffU << 16U;
2314}
2315static inline u32 gr_gpc0_ppc0_cbm_cfg2_size_v(u32 r)
2316{
2317 return (r >> 16U) & 0xfffU;
2318}
2319static inline u32 gr_gpc0_ppc0_cbm_cfg2_size_default_v(void)
2320{
2321 return 0x00000648U;
2322}
2323static inline u32 gr_gpc0_ppc0_cbm_cfg2_size_granularity_v(void)
2324{
2325 return 0x00000020U;
2326}
2327static inline u32 gr_gpccs_falcon_addr_r(void)
2328{
2329 return 0x0041a0acU;
2330}
2331static inline u32 gr_gpccs_falcon_addr_lsb_s(void)
2332{
2333 return 6U;
2334}
2335static inline u32 gr_gpccs_falcon_addr_lsb_f(u32 v)
2336{
2337 return (v & 0x3fU) << 0U;
2338}
2339static inline u32 gr_gpccs_falcon_addr_lsb_m(void)
2340{
2341 return 0x3fU << 0U;
2342}
2343static inline u32 gr_gpccs_falcon_addr_lsb_v(u32 r)
2344{
2345 return (r >> 0U) & 0x3fU;
2346}
2347static inline u32 gr_gpccs_falcon_addr_lsb_init_v(void)
2348{
2349 return 0x00000000U;
2350}
2351static inline u32 gr_gpccs_falcon_addr_lsb_init_f(void)
2352{
2353 return 0x0U;
2354}
2355static inline u32 gr_gpccs_falcon_addr_msb_s(void)
2356{
2357 return 6U;
2358}
2359static inline u32 gr_gpccs_falcon_addr_msb_f(u32 v)
2360{
2361 return (v & 0x3fU) << 6U;
2362}
2363static inline u32 gr_gpccs_falcon_addr_msb_m(void)
2364{
2365 return 0x3fU << 6U;
2366}
2367static inline u32 gr_gpccs_falcon_addr_msb_v(u32 r)
2368{
2369 return (r >> 6U) & 0x3fU;
2370}
2371static inline u32 gr_gpccs_falcon_addr_msb_init_v(void)
2372{
2373 return 0x00000000U;
2374}
2375static inline u32 gr_gpccs_falcon_addr_msb_init_f(void)
2376{
2377 return 0x0U;
2378}
2379static inline u32 gr_gpccs_falcon_addr_ext_s(void)
2380{
2381 return 12U;
2382}
2383static inline u32 gr_gpccs_falcon_addr_ext_f(u32 v)
2384{
2385 return (v & 0xfffU) << 0U;
2386}
2387static inline u32 gr_gpccs_falcon_addr_ext_m(void)
2388{
2389 return 0xfffU << 0U;
2390}
2391static inline u32 gr_gpccs_falcon_addr_ext_v(u32 r)
2392{
2393 return (r >> 0U) & 0xfffU;
2394}
2395static inline u32 gr_gpccs_cpuctl_r(void)
2396{
2397 return 0x0041a100U;
2398}
2399static inline u32 gr_gpccs_cpuctl_startcpu_f(u32 v)
2400{
2401 return (v & 0x1U) << 1U;
2402}
2403static inline u32 gr_gpccs_dmactl_r(void)
2404{
2405 return 0x0041a10cU;
2406}
2407static inline u32 gr_gpccs_dmactl_require_ctx_f(u32 v)
2408{
2409 return (v & 0x1U) << 0U;
2410}
2411static inline u32 gr_gpccs_dmactl_dmem_scrubbing_m(void)
2412{
2413 return 0x1U << 1U;
2414}
2415static inline u32 gr_gpccs_dmactl_imem_scrubbing_m(void)
2416{
2417 return 0x1U << 2U;
2418}
2419static inline u32 gr_gpccs_imemc_r(u32 i)
2420{
2421 return 0x0041a180U + i*16U;
2422}
2423static inline u32 gr_gpccs_imemc_offs_f(u32 v)
2424{
2425 return (v & 0x3fU) << 2U;
2426}
2427static inline u32 gr_gpccs_imemc_blk_f(u32 v)
2428{
2429 return (v & 0xffU) << 8U;
2430}
2431static inline u32 gr_gpccs_imemc_aincw_f(u32 v)
2432{
2433 return (v & 0x1U) << 24U;
2434}
2435static inline u32 gr_gpccs_imemd_r(u32 i)
2436{
2437 return 0x0041a184U + i*16U;
2438}
2439static inline u32 gr_gpccs_imemt_r(u32 i)
2440{
2441 return 0x0041a188U + i*16U;
2442}
2443static inline u32 gr_gpccs_imemt__size_1_v(void)
2444{
2445 return 0x00000004U;
2446}
2447static inline u32 gr_gpccs_imemt_tag_f(u32 v)
2448{
2449 return (v & 0xffffU) << 0U;
2450}
2451static inline u32 gr_gpccs_dmemc_r(u32 i)
2452{
2453 return 0x0041a1c0U + i*8U;
2454}
2455static inline u32 gr_gpccs_dmemc_offs_f(u32 v)
2456{
2457 return (v & 0x3fU) << 2U;
2458}
2459static inline u32 gr_gpccs_dmemc_blk_f(u32 v)
2460{
2461 return (v & 0xffU) << 8U;
2462}
2463static inline u32 gr_gpccs_dmemc_aincw_f(u32 v)
2464{
2465 return (v & 0x1U) << 24U;
2466}
2467static inline u32 gr_gpccs_dmemd_r(u32 i)
2468{
2469 return 0x0041a1c4U + i*8U;
2470}
2471static inline u32 gr_gpccs_ctxsw_mailbox_r(u32 i)
2472{
2473 return 0x0041a800U + i*4U;
2474}
2475static inline u32 gr_gpccs_ctxsw_mailbox_value_f(u32 v)
2476{
2477 return (v & 0xffffffffU) << 0U;
2478}
2479static inline u32 gr_gpcs_setup_bundle_cb_base_r(void)
2480{
2481 return 0x00418808U;
2482}
2483static inline u32 gr_gpcs_setup_bundle_cb_base_addr_39_8_s(void)
2484{
2485 return 32U;
2486}
2487static inline u32 gr_gpcs_setup_bundle_cb_base_addr_39_8_f(u32 v)
2488{
2489 return (v & 0xffffffffU) << 0U;
2490}
2491static inline u32 gr_gpcs_setup_bundle_cb_base_addr_39_8_m(void)
2492{
2493 return 0xffffffffU << 0U;
2494}
2495static inline u32 gr_gpcs_setup_bundle_cb_base_addr_39_8_v(u32 r)
2496{
2497 return (r >> 0U) & 0xffffffffU;
2498}
2499static inline u32 gr_gpcs_setup_bundle_cb_base_addr_39_8_init_v(void)
2500{
2501 return 0x00000000U;
2502}
2503static inline u32 gr_gpcs_setup_bundle_cb_base_addr_39_8_init_f(void)
2504{
2505 return 0x0U;
2506}
2507static inline u32 gr_gpcs_setup_bundle_cb_size_r(void)
2508{
2509 return 0x0041880cU;
2510}
2511static inline u32 gr_gpcs_setup_bundle_cb_size_div_256b_s(void)
2512{
2513 return 11U;
2514}
2515static inline u32 gr_gpcs_setup_bundle_cb_size_div_256b_f(u32 v)
2516{
2517 return (v & 0x7ffU) << 0U;
2518}
2519static inline u32 gr_gpcs_setup_bundle_cb_size_div_256b_m(void)
2520{
2521 return 0x7ffU << 0U;
2522}
2523static inline u32 gr_gpcs_setup_bundle_cb_size_div_256b_v(u32 r)
2524{
2525 return (r >> 0U) & 0x7ffU;
2526}
2527static inline u32 gr_gpcs_setup_bundle_cb_size_div_256b_init_v(void)
2528{
2529 return 0x00000000U;
2530}
2531static inline u32 gr_gpcs_setup_bundle_cb_size_div_256b_init_f(void)
2532{
2533 return 0x0U;
2534}
2535static inline u32 gr_gpcs_setup_bundle_cb_size_div_256b__prod_v(void)
2536{
2537 return 0x00000018U;
2538}
2539static inline u32 gr_gpcs_setup_bundle_cb_size_div_256b__prod_f(void)
2540{
2541 return 0x18U;
2542}
2543static inline u32 gr_gpcs_setup_bundle_cb_size_valid_s(void)
2544{
2545 return 1U;
2546}
2547static inline u32 gr_gpcs_setup_bundle_cb_size_valid_f(u32 v)
2548{
2549 return (v & 0x1U) << 31U;
2550}
2551static inline u32 gr_gpcs_setup_bundle_cb_size_valid_m(void)
2552{
2553 return 0x1U << 31U;
2554}
2555static inline u32 gr_gpcs_setup_bundle_cb_size_valid_v(u32 r)
2556{
2557 return (r >> 31U) & 0x1U;
2558}
2559static inline u32 gr_gpcs_setup_bundle_cb_size_valid_false_v(void)
2560{
2561 return 0x00000000U;
2562}
2563static inline u32 gr_gpcs_setup_bundle_cb_size_valid_false_f(void)
2564{
2565 return 0x0U;
2566}
2567static inline u32 gr_gpcs_setup_bundle_cb_size_valid_true_v(void)
2568{
2569 return 0x00000001U;
2570}
2571static inline u32 gr_gpcs_setup_bundle_cb_size_valid_true_f(void)
2572{
2573 return 0x80000000U;
2574}
2575static inline u32 gr_gpcs_setup_attrib_cb_base_r(void)
2576{
2577 return 0x00418810U;
2578}
2579static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_f(u32 v)
2580{
2581 return (v & 0xfffffffU) << 0U;
2582}
2583static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v(void)
2584{
2585 return 0x0000000cU;
2586}
2587static inline u32 gr_gpcs_setup_attrib_cb_base_valid_true_f(void)
2588{
2589 return 0x80000000U;
2590}
2591static inline u32 gr_crstr_gpc_map0_r(void)
2592{
2593 return 0x00418b08U;
2594}
2595static inline u32 gr_crstr_gpc_map0_tile0_f(u32 v)
2596{
2597 return (v & 0x7U) << 0U;
2598}
2599static inline u32 gr_crstr_gpc_map0_tile1_f(u32 v)
2600{
2601 return (v & 0x7U) << 5U;
2602}
2603static inline u32 gr_crstr_gpc_map0_tile2_f(u32 v)
2604{
2605 return (v & 0x7U) << 10U;
2606}
2607static inline u32 gr_crstr_gpc_map0_tile3_f(u32 v)
2608{
2609 return (v & 0x7U) << 15U;
2610}
2611static inline u32 gr_crstr_gpc_map0_tile4_f(u32 v)
2612{
2613 return (v & 0x7U) << 20U;
2614}
2615static inline u32 gr_crstr_gpc_map0_tile5_f(u32 v)
2616{
2617 return (v & 0x7U) << 25U;
2618}
2619static inline u32 gr_crstr_gpc_map1_r(void)
2620{
2621 return 0x00418b0cU;
2622}
2623static inline u32 gr_crstr_gpc_map1_tile6_f(u32 v)
2624{
2625 return (v & 0x7U) << 0U;
2626}
2627static inline u32 gr_crstr_gpc_map1_tile7_f(u32 v)
2628{
2629 return (v & 0x7U) << 5U;
2630}
2631static inline u32 gr_crstr_gpc_map1_tile8_f(u32 v)
2632{
2633 return (v & 0x7U) << 10U;
2634}
2635static inline u32 gr_crstr_gpc_map1_tile9_f(u32 v)
2636{
2637 return (v & 0x7U) << 15U;
2638}
2639static inline u32 gr_crstr_gpc_map1_tile10_f(u32 v)
2640{
2641 return (v & 0x7U) << 20U;
2642}
2643static inline u32 gr_crstr_gpc_map1_tile11_f(u32 v)
2644{
2645 return (v & 0x7U) << 25U;
2646}
2647static inline u32 gr_crstr_gpc_map2_r(void)
2648{
2649 return 0x00418b10U;
2650}
2651static inline u32 gr_crstr_gpc_map2_tile12_f(u32 v)
2652{
2653 return (v & 0x7U) << 0U;
2654}
2655static inline u32 gr_crstr_gpc_map2_tile13_f(u32 v)
2656{
2657 return (v & 0x7U) << 5U;
2658}
2659static inline u32 gr_crstr_gpc_map2_tile14_f(u32 v)
2660{
2661 return (v & 0x7U) << 10U;
2662}
2663static inline u32 gr_crstr_gpc_map2_tile15_f(u32 v)
2664{
2665 return (v & 0x7U) << 15U;
2666}
2667static inline u32 gr_crstr_gpc_map2_tile16_f(u32 v)
2668{
2669 return (v & 0x7U) << 20U;
2670}
2671static inline u32 gr_crstr_gpc_map2_tile17_f(u32 v)
2672{
2673 return (v & 0x7U) << 25U;
2674}
2675static inline u32 gr_crstr_gpc_map3_r(void)
2676{
2677 return 0x00418b14U;
2678}
2679static inline u32 gr_crstr_gpc_map3_tile18_f(u32 v)
2680{
2681 return (v & 0x7U) << 0U;
2682}
2683static inline u32 gr_crstr_gpc_map3_tile19_f(u32 v)
2684{
2685 return (v & 0x7U) << 5U;
2686}
2687static inline u32 gr_crstr_gpc_map3_tile20_f(u32 v)
2688{
2689 return (v & 0x7U) << 10U;
2690}
2691static inline u32 gr_crstr_gpc_map3_tile21_f(u32 v)
2692{
2693 return (v & 0x7U) << 15U;
2694}
2695static inline u32 gr_crstr_gpc_map3_tile22_f(u32 v)
2696{
2697 return (v & 0x7U) << 20U;
2698}
2699static inline u32 gr_crstr_gpc_map3_tile23_f(u32 v)
2700{
2701 return (v & 0x7U) << 25U;
2702}
2703static inline u32 gr_crstr_gpc_map4_r(void)
2704{
2705 return 0x00418b18U;
2706}
2707static inline u32 gr_crstr_gpc_map4_tile24_f(u32 v)
2708{
2709 return (v & 0x7U) << 0U;
2710}
2711static inline u32 gr_crstr_gpc_map4_tile25_f(u32 v)
2712{
2713 return (v & 0x7U) << 5U;
2714}
2715static inline u32 gr_crstr_gpc_map4_tile26_f(u32 v)
2716{
2717 return (v & 0x7U) << 10U;
2718}
2719static inline u32 gr_crstr_gpc_map4_tile27_f(u32 v)
2720{
2721 return (v & 0x7U) << 15U;
2722}
2723static inline u32 gr_crstr_gpc_map4_tile28_f(u32 v)
2724{
2725 return (v & 0x7U) << 20U;
2726}
2727static inline u32 gr_crstr_gpc_map4_tile29_f(u32 v)
2728{
2729 return (v & 0x7U) << 25U;
2730}
2731static inline u32 gr_crstr_gpc_map5_r(void)
2732{
2733 return 0x00418b1cU;
2734}
2735static inline u32 gr_crstr_gpc_map5_tile30_f(u32 v)
2736{
2737 return (v & 0x7U) << 0U;
2738}
2739static inline u32 gr_crstr_gpc_map5_tile31_f(u32 v)
2740{
2741 return (v & 0x7U) << 5U;
2742}
2743static inline u32 gr_crstr_gpc_map5_tile32_f(u32 v)
2744{
2745 return (v & 0x7U) << 10U;
2746}
2747static inline u32 gr_crstr_gpc_map5_tile33_f(u32 v)
2748{
2749 return (v & 0x7U) << 15U;
2750}
2751static inline u32 gr_crstr_gpc_map5_tile34_f(u32 v)
2752{
2753 return (v & 0x7U) << 20U;
2754}
2755static inline u32 gr_crstr_gpc_map5_tile35_f(u32 v)
2756{
2757 return (v & 0x7U) << 25U;
2758}
2759static inline u32 gr_crstr_map_table_cfg_r(void)
2760{
2761 return 0x00418bb8U;
2762}
2763static inline u32 gr_crstr_map_table_cfg_row_offset_f(u32 v)
2764{
2765 return (v & 0xffU) << 0U;
2766}
2767static inline u32 gr_crstr_map_table_cfg_num_entries_f(u32 v)
2768{
2769 return (v & 0xffU) << 8U;
2770}
2771static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_r(void)
2772{
2773 return 0x00418980U;
2774}
2775static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_0_f(u32 v)
2776{
2777 return (v & 0x7U) << 0U;
2778}
2779static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_1_f(u32 v)
2780{
2781 return (v & 0x7U) << 4U;
2782}
2783static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_2_f(u32 v)
2784{
2785 return (v & 0x7U) << 8U;
2786}
2787static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_3_f(u32 v)
2788{
2789 return (v & 0x7U) << 12U;
2790}
2791static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_4_f(u32 v)
2792{
2793 return (v & 0x7U) << 16U;
2794}
2795static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_5_f(u32 v)
2796{
2797 return (v & 0x7U) << 20U;
2798}
2799static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_6_f(u32 v)
2800{
2801 return (v & 0x7U) << 24U;
2802}
2803static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_7_f(u32 v)
2804{
2805 return (v & 0x7U) << 28U;
2806}
2807static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_r(void)
2808{
2809 return 0x00418984U;
2810}
2811static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_8_f(u32 v)
2812{
2813 return (v & 0x7U) << 0U;
2814}
2815static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_9_f(u32 v)
2816{
2817 return (v & 0x7U) << 4U;
2818}
2819static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_10_f(u32 v)
2820{
2821 return (v & 0x7U) << 8U;
2822}
2823static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_11_f(u32 v)
2824{
2825 return (v & 0x7U) << 12U;
2826}
2827static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_12_f(u32 v)
2828{
2829 return (v & 0x7U) << 16U;
2830}
2831static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_13_f(u32 v)
2832{
2833 return (v & 0x7U) << 20U;
2834}
2835static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_14_f(u32 v)
2836{
2837 return (v & 0x7U) << 24U;
2838}
2839static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_15_f(u32 v)
2840{
2841 return (v & 0x7U) << 28U;
2842}
2843static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_r(void)
2844{
2845 return 0x00418988U;
2846}
2847static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_16_f(u32 v)
2848{
2849 return (v & 0x7U) << 0U;
2850}
2851static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_17_f(u32 v)
2852{
2853 return (v & 0x7U) << 4U;
2854}
2855static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_18_f(u32 v)
2856{
2857 return (v & 0x7U) << 8U;
2858}
2859static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_19_f(u32 v)
2860{
2861 return (v & 0x7U) << 12U;
2862}
2863static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_20_f(u32 v)
2864{
2865 return (v & 0x7U) << 16U;
2866}
2867static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_21_f(u32 v)
2868{
2869 return (v & 0x7U) << 20U;
2870}
2871static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_22_f(u32 v)
2872{
2873 return (v & 0x7U) << 24U;
2874}
2875static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_s(void)
2876{
2877 return 3U;
2878}
2879static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_f(u32 v)
2880{
2881 return (v & 0x7U) << 28U;
2882}
2883static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_m(void)
2884{
2885 return 0x7U << 28U;
2886}
2887static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_v(u32 r)
2888{
2889 return (r >> 28U) & 0x7U;
2890}
2891static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_r(void)
2892{
2893 return 0x0041898cU;
2894}
2895static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_24_f(u32 v)
2896{
2897 return (v & 0x7U) << 0U;
2898}
2899static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_25_f(u32 v)
2900{
2901 return (v & 0x7U) << 4U;
2902}
2903static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_26_f(u32 v)
2904{
2905 return (v & 0x7U) << 8U;
2906}
2907static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_27_f(u32 v)
2908{
2909 return (v & 0x7U) << 12U;
2910}
2911static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_28_f(u32 v)
2912{
2913 return (v & 0x7U) << 16U;
2914}
2915static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_29_f(u32 v)
2916{
2917 return (v & 0x7U) << 20U;
2918}
2919static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_30_f(u32 v)
2920{
2921 return (v & 0x7U) << 24U;
2922}
2923static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_31_f(u32 v)
2924{
2925 return (v & 0x7U) << 28U;
2926}
2927static inline u32 gr_gpcs_gpm_pd_cfg_r(void)
2928{
2929 return 0x00418c6cU;
2930}
2931static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_disable_f(void)
2932{
2933 return 0x0U;
2934}
2935static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_enable_f(void)
2936{
2937 return 0x1U;
2938}
2939static inline u32 gr_gpcs_gcc_pagepool_base_r(void)
2940{
2941 return 0x00419004U;
2942}
2943static inline u32 gr_gpcs_gcc_pagepool_base_addr_39_8_f(u32 v)
2944{
2945 return (v & 0xffffffffU) << 0U;
2946}
2947static inline u32 gr_gpcs_gcc_pagepool_r(void)
2948{
2949 return 0x00419008U;
2950}
2951static inline u32 gr_gpcs_gcc_pagepool_total_pages_f(u32 v)
2952{
2953 return (v & 0xffU) << 0U;
2954}
2955static inline u32 gr_gpcs_tpcs_pe_vaf_r(void)
2956{
2957 return 0x0041980cU;
2958}
2959static inline u32 gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f(void)
2960{
2961 return 0x10U;
2962}
2963static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r(void)
2964{
2965 return 0x00419848U;
2966}
2967static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(u32 v)
2968{
2969 return (v & 0xfffffffU) << 0U;
2970}
2971static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(u32 v)
2972{
2973 return (v & 0x1U) << 28U;
2974}
2975static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f(void)
2976{
2977 return 0x10000000U;
2978}
2979static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_r(void)
2980{
2981 return 0x00419c00U;
2982}
2983static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f(void)
2984{
2985 return 0x0U;
2986}
2987static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f(void)
2988{
2989 return 0x8U;
2990}
2991static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r(void)
2992{
2993 return 0x00419e44U;
2994}
2995static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_error_report_f(void)
2996{
2997 return 0x2U;
2998}
2999static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_api_stack_error_report_f(void)
3000{
3001 return 0x4U;
3002}
3003static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_ret_empty_stack_error_report_f(void)
3004{
3005 return 0x8U;
3006}
3007static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_wrap_report_f(void)
3008{
3009 return 0x10U;
3010}
3011static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_pc_report_f(void)
3012{
3013 return 0x20U;
3014}
3015static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_overflow_report_f(void)
3016{
3017 return 0x40U;
3018}
3019static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_immc_addr_report_f(void)
3020{
3021 return 0x80U;
3022}
3023static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_reg_report_f(void)
3024{
3025 return 0x100U;
3026}
3027static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void)
3028{
3029 return 0x200U;
3030}
3031static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_sph_instr_combo_report_f(void)
3032{
3033 return 0x400U;
3034}
3035static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param_report_f(void)
3036{
3037 return 0x800U;
3038}
3039static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_report_f(void)
3040{
3041 return 0x1000U;
3042}
3043static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_reg_report_f(void)
3044{
3045 return 0x2000U;
3046}
3047static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_addr_report_f(void)
3048{
3049 return 0x4000U;
3050}
3051static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_addr_report_f(void)
3052{
3053 return 0x8000U;
3054}
3055static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_addr_space_report_f(void)
3056{
3057 return 0x10000U;
3058}
3059static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param2_report_f(void)
3060{
3061 return 0x20000U;
3062}
3063static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void)
3064{
3065 return 0x40000U;
3066}
3067static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_geometry_sm_error_report_f(void)
3068{
3069 return 0x80000U;
3070}
3071static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_divergent_report_f(void)
3072{
3073 return 0x100000U;
3074}
3075static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_r(void)
3076{
3077 return 0x00419e4cU;
3078}
3079static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_sm_to_sm_fault_report_f(void)
3080{
3081 return 0x1U;
3082}
3083static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_l1_error_report_f(void)
3084{
3085 return 0x2U;
3086}
3087static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_multiple_warp_errors_report_f(void)
3088{
3089 return 0x4U;
3090}
3091static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_physical_stack_overflow_error_report_f(void)
3092{
3093 return 0x8U;
3094}
3095static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_int_report_f(void)
3096{
3097 return 0x10U;
3098}
3099static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_pause_report_f(void)
3100{
3101 return 0x20U;
3102}
3103static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_single_step_complete_report_f(void)
3104{
3105 return 0x40U;
3106}
3107static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void)
3108{
3109 return 0x00419d0cU;
3110}
3111static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f(void)
3112{
3113 return 0x2U;
3114}
3115static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f(void)
3116{
3117 return 0x1U;
3118}
3119static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void)
3120{
3121 return 0x0050450cU;
3122}
3123static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(u32 r)
3124{
3125 return (r >> 1U) & 0x1U;
3126}
3127static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void)
3128{
3129 return 0x2U;
3130}
3131static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void)
3132{
3133 return 0x0041ac94U;
3134}
3135static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v)
3136{
3137 return (v & 0xffU) << 16U;
3138}
3139static inline u32 gr_gpc0_gpccs_gpc_exception_r(void)
3140{
3141 return 0x00502c90U;
3142}
3143static inline u32 gr_gpc0_gpccs_gpc_exception_gcc_v(u32 r)
3144{
3145 return (r >> 2U) & 0x1U;
3146}
3147static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r)
3148{
3149 return (r >> 16U) & 0xffU;
3150}
3151static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v(void)
3152{
3153 return 0x00000001U;
3154}
3155static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void)
3156{
3157 return 0x00504508U;
3158}
3159static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_v(u32 r)
3160{
3161 return (r >> 0U) & 0x1U;
3162}
3163static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_pending_v(void)
3164{
3165 return 0x00000001U;
3166}
3167static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r)
3168{
3169 return (r >> 1U) & 0x1U;
3170}
3171static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void)
3172{
3173 return 0x00000001U;
3174}
3175static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_r(void)
3176{
3177 return 0x00504610U;
3178}
3179static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_m(void)
3180{
3181 return 0x1U << 0U;
3182}
3183static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_v(u32 r)
3184{
3185 return (r >> 0U) & 0x1U;
3186}
3187static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_v(void)
3188{
3189 return 0x00000001U;
3190}
3191static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_f(void)
3192{
3193 return 0x1U;
3194}
3195static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_v(void)
3196{
3197 return 0x00000000U;
3198}
3199static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_f(void)
3200{
3201 return 0x0U;
3202}
3203static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_enable_f(void)
3204{
3205 return 0x80000000U;
3206}
3207static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_disable_f(void)
3208{
3209 return 0x0U;
3210}
3211static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_enable_f(void)
3212{
3213 return 0x8U;
3214}
3215static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_disable_f(void)
3216{
3217 return 0x0U;
3218}
3219static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void)
3220{
3221 return 0x40000000U;
3222}
3223static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_m(void)
3224{
3225 return 0x1U << 1U;
3226}
3227static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_v(u32 r)
3228{
3229 return (r >> 1U) & 0x1U;
3230}
3231static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_disable_f(void)
3232{
3233 return 0x0U;
3234}
3235static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_m(void)
3236{
3237 return 0x1U << 2U;
3238}
3239static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_v(u32 r)
3240{
3241 return (r >> 2U) & 0x1U;
3242}
3243static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_disable_f(void)
3244{
3245 return 0x0U;
3246}
3247static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_warp_disable_v(void)
3248{
3249 return 0x00000000U;
3250}
3251static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_sm_disable_v(void)
3252{
3253 return 0x00000000U;
3254}
3255static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_r(void)
3256{
3257 return 0x00504614U;
3258}
3259static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_1_r(void)
3260{
3261 return 0x00504618U;
3262}
3263static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r(void)
3264{
3265 return 0x00504624U;
3266}
3267static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_1_r(void)
3268{
3269 return 0x00504628U;
3270}
3271static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r(void)
3272{
3273 return 0x00504634U;
3274}
3275static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_1_r(void)
3276{
3277 return 0x00504638U;
3278}
3279static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_r(void)
3280{
3281 return 0x00419e24U;
3282}
3283static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void)
3284{
3285 return 0x0050460cU;
3286}
3287static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_sm_in_trap_mode_v(u32 r)
3288{
3289 return (r >> 0U) & 0x1U;
3290}
3291static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_v(u32 r)
3292{
3293 return (r >> 4U) & 0x1U;
3294}
3295static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_true_v(void)
3296{
3297 return 0x00000001U;
3298}
3299static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_r(void)
3300{
3301 return 0x00419e50U;
3302}
3303static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_int_pending_f(void)
3304{
3305 return 0x10U;
3306}
3307static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_pause_pending_f(void)
3308{
3309 return 0x20U;
3310}
3311static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_single_step_complete_pending_f(void)
3312{
3313 return 0x40U;
3314}
3315static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_sm_to_sm_fault_pending_f(void)
3316{
3317 return 0x1U;
3318}
3319static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_l1_error_pending_f(void)
3320{
3321 return 0x2U;
3322}
3323static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_multiple_warp_errors_pending_f(void)
3324{
3325 return 0x4U;
3326}
3327static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void)
3328{
3329 return 0x8U;
3330}
3331static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_timeout_error_pending_f(void)
3332{
3333 return 0x80000000U;
3334}
3335static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_r(void)
3336{
3337 return 0x00504650U;
3338}
3339static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f(void)
3340{
3341 return 0x10U;
3342}
3343static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_pause_pending_f(void)
3344{
3345 return 0x20U;
3346}
3347static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f(void)
3348{
3349 return 0x40U;
3350}
3351static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_sm_to_sm_fault_pending_f(void)
3352{
3353 return 0x1U;
3354}
3355static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_l1_error_pending_f(void)
3356{
3357 return 0x2U;
3358}
3359static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_multiple_warp_errors_pending_f(void)
3360{
3361 return 0x4U;
3362}
3363static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void)
3364{
3365 return 0x8U;
3366}
3367static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_timeout_error_pending_f(void)
3368{
3369 return 0x80000000U;
3370}
3371static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_r(void)
3372{
3373 return 0x00504224U;
3374}
3375static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_intr_pending_f(void)
3376{
3377 return 0x1U;
3378}
3379static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_r(void)
3380{
3381 return 0x00504648U;
3382}
3383static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_v(u32 r)
3384{
3385 return (r >> 0U) & 0xffffU;
3386}
3387static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_v(void)
3388{
3389 return 0x00000000U;
3390}
3391static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_f(void)
3392{
3393 return 0x0U;
3394}
3395static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void)
3396{
3397 return 0x00504770U;
3398}
3399static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void)
3400{
3401 return 0x00419f70U;
3402}
3403static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void)
3404{
3405 return 0x1U << 4U;
3406}
3407static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v)
3408{
3409 return (v & 0x1U) << 4U;
3410}
3411static inline u32 gr_gpc0_tpc0_sm_debug_sfe_control_r(void)
3412{
3413 return 0x0050477cU;
3414}
3415static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void)
3416{
3417 return 0x00419f7cU;
3418}
3419static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void)
3420{
3421 return 0x1U << 0U;
3422}
3423static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v)
3424{
3425 return (v & 0x1U) << 0U;
3426}
3427static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void)
3428{
3429 return 0x0041be08U;
3430}
3431static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f(void)
3432{
3433 return 0x4U;
3434}
3435static inline u32 gr_ppcs_wwdx_map_gpc_map0_r(void)
3436{
3437 return 0x0041bf00U;
3438}
3439static inline u32 gr_ppcs_wwdx_map_gpc_map1_r(void)
3440{
3441 return 0x0041bf04U;
3442}
3443static inline u32 gr_ppcs_wwdx_map_gpc_map2_r(void)
3444{
3445 return 0x0041bf08U;
3446}
3447static inline u32 gr_ppcs_wwdx_map_gpc_map3_r(void)
3448{
3449 return 0x0041bf0cU;
3450}
3451static inline u32 gr_ppcs_wwdx_map_gpc_map4_r(void)
3452{
3453 return 0x0041bf10U;
3454}
3455static inline u32 gr_ppcs_wwdx_map_gpc_map5_r(void)
3456{
3457 return 0x0041bf14U;
3458}
3459static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void)
3460{
3461 return 0x0041bfd0U;
3462}
3463static inline u32 gr_ppcs_wwdx_map_table_cfg_row_offset_f(u32 v)
3464{
3465 return (v & 0xffU) << 0U;
3466}
3467static inline u32 gr_ppcs_wwdx_map_table_cfg_num_entries_f(u32 v)
3468{
3469 return (v & 0xffU) << 8U;
3470}
3471static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(u32 v)
3472{
3473 return (v & 0x1fU) << 16U;
3474}
3475static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(u32 v)
3476{
3477 return (v & 0x7U) << 21U;
3478}
3479static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff5_mod_value_f(u32 v)
3480{
3481 return (v & 0x1fU) << 24U;
3482}
3483static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_r(void)
3484{
3485 return 0x0041bfd4U;
3486}
3487static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(u32 v)
3488{
3489 return (v & 0xffffffU) << 0U;
3490}
3491static inline u32 gr_ppcs_wwdx_map_table_cfg2_r(void)
3492{
3493 return 0x0041bfe4U;
3494}
3495static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff6_mod_value_f(u32 v)
3496{
3497 return (v & 0x1fU) << 0U;
3498}
3499static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff7_mod_value_f(u32 v)
3500{
3501 return (v & 0x1fU) << 5U;
3502}
3503static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff8_mod_value_f(u32 v)
3504{
3505 return (v & 0x1fU) << 10U;
3506}
3507static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff9_mod_value_f(u32 v)
3508{
3509 return (v & 0x1fU) << 15U;
3510}
3511static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff10_mod_value_f(u32 v)
3512{
3513 return (v & 0x1fU) << 20U;
3514}
3515static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff11_mod_value_f(u32 v)
3516{
3517 return (v & 0x1fU) << 25U;
3518}
3519static inline u32 gr_gpcs_ppcs_cbm_cfg_r(void)
3520{
3521 return 0x0041bec0U;
3522}
3523static inline u32 gr_gpcs_ppcs_cbm_cfg_timeslice_mode_enable_v(void)
3524{
3525 return 0x00000001U;
3526}
3527static inline u32 gr_bes_zrop_settings_r(void)
3528{
3529 return 0x00408850U;
3530}
3531static inline u32 gr_bes_zrop_settings_num_active_fbps_f(u32 v)
3532{
3533 return (v & 0xfU) << 0U;
3534}
3535static inline u32 gr_bes_crop_settings_r(void)
3536{
3537 return 0x00408958U;
3538}
3539static inline u32 gr_bes_crop_settings_num_active_fbps_f(u32 v)
3540{
3541 return (v & 0xfU) << 0U;
3542}
3543static inline u32 gr_zcull_bytes_per_aliquot_per_gpu_v(void)
3544{
3545 return 0x00000020U;
3546}
3547static inline u32 gr_zcull_save_restore_header_bytes_per_gpc_v(void)
3548{
3549 return 0x00000020U;
3550}
3551static inline u32 gr_zcull_save_restore_subregion_header_bytes_per_gpc_v(void)
3552{
3553 return 0x000000c0U;
3554}
3555static inline u32 gr_zcull_subregion_qty_v(void)
3556{
3557 return 0x00000010U;
3558}
3559static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel0_r(void)
3560{
3561 return 0x00504604U;
3562}
3563static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel1_r(void)
3564{
3565 return 0x00504608U;
3566}
3567static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control0_r(void)
3568{
3569 return 0x0050465cU;
3570}
3571static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control1_r(void)
3572{
3573 return 0x00504660U;
3574}
3575static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control2_r(void)
3576{
3577 return 0x00504664U;
3578}
3579static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control3_r(void)
3580{
3581 return 0x00504668U;
3582}
3583static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control4_r(void)
3584{
3585 return 0x0050466cU;
3586}
3587static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control5_r(void)
3588{
3589 return 0x00504658U;
3590}
3591static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status_r(void)
3592{
3593 return 0x00504670U;
3594}
3595static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status1_r(void)
3596{
3597 return 0x00504694U;
3598}
3599static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_control_r(void)
3600{
3601 return 0x00504730U;
3602}
3603static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_control_r(void)
3604{
3605 return 0x00504734U;
3606}
3607static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_control_r(void)
3608{
3609 return 0x00504738U;
3610}
3611static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_control_r(void)
3612{
3613 return 0x0050473cU;
3614}
3615static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter4_control_r(void)
3616{
3617 return 0x00504740U;
3618}
3619static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter5_control_r(void)
3620{
3621 return 0x00504744U;
3622}
3623static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter6_control_r(void)
3624{
3625 return 0x00504748U;
3626}
3627static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter7_control_r(void)
3628{
3629 return 0x0050474cU;
3630}
3631static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_r(void)
3632{
3633 return 0x00504674U;
3634}
3635static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_r(void)
3636{
3637 return 0x00504678U;
3638}
3639static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_r(void)
3640{
3641 return 0x0050467cU;
3642}
3643static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_r(void)
3644{
3645 return 0x00504680U;
3646}
3647static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter4_r(void)
3648{
3649 return 0x00504684U;
3650}
3651static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter5_r(void)
3652{
3653 return 0x00504688U;
3654}
3655static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter6_r(void)
3656{
3657 return 0x0050468cU;
3658}
3659static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter7_r(void)
3660{
3661 return 0x00504690U;
3662}
3663static inline u32 gr_fe_pwr_mode_r(void)
3664{
3665 return 0x00404170U;
3666}
3667static inline u32 gr_fe_pwr_mode_mode_auto_f(void)
3668{
3669 return 0x0U;
3670}
3671static inline u32 gr_fe_pwr_mode_mode_force_on_f(void)
3672{
3673 return 0x2U;
3674}
3675static inline u32 gr_fe_pwr_mode_req_v(u32 r)
3676{
3677 return (r >> 4U) & 0x1U;
3678}
3679static inline u32 gr_fe_pwr_mode_req_send_f(void)
3680{
3681 return 0x10U;
3682}
3683static inline u32 gr_fe_pwr_mode_req_done_v(void)
3684{
3685 return 0x00000000U;
3686}
3687static inline u32 gr_gpc0_tpc0_l1c_dbg_r(void)
3688{
3689 return 0x005044b0U;
3690}
3691static inline u32 gr_gpc0_tpc0_l1c_dbg_cya15_en_f(void)
3692{
3693 return 0x8000000U;
3694}
3695static inline u32 gr_gpcs_tpcs_sm_sch_texlock_r(void)
3696{
3697 return 0x00419ec8U;
3698}
3699static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_m(void)
3700{
3701 return 0x1U << 0U;
3702}
3703static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_disable_f(void)
3704{
3705 return 0x0U;
3706}
3707static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_tile_m(void)
3708{
3709 return 0x1U << 1U;
3710}
3711static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_tile_disable_f(void)
3712{
3713 return 0x0U;
3714}
3715static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_phase_m(void)
3716{
3717 return 0x1U << 2U;
3718}
3719static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_phase_disable_f(void)
3720{
3721 return 0x0U;
3722}
3723static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_tex_m(void)
3724{
3725 return 0x1U << 3U;
3726}
3727static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_tex_disable_f(void)
3728{
3729 return 0x0U;
3730}
3731static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_timeout_m(void)
3732{
3733 return 0xffU << 4U;
3734}
3735static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_timeout_disable_f(void)
3736{
3737 return 0x0U;
3738}
3739static inline u32 gr_gpcs_tpcs_sm_sch_texlock_dot_t_unlock_m(void)
3740{
3741 return 0x1U << 16U;
3742}
3743static inline u32 gr_gpcs_tpcs_sm_sch_texlock_dot_t_unlock_disable_f(void)
3744{
3745 return 0x0U;
3746}
3747static inline u32 gr_gpcs_tpcs_sm_sch_macro_sched_r(void)
3748{
3749 return 0x00419eacU;
3750}
3751static inline u32 gr_gpcs_tpcs_sm_sch_macro_sched_lockboost_size_f(u32 v)
3752{
3753 return (v & 0x1U) << 2U;
3754}
3755static inline u32 gr_gpcs_tpcs_sm_sch_macro_sched_lockboost_size_m(void)
3756{
3757 return 0x1U << 2U;
3758}
3759static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_r(void)
3760{
3761 return 0x00419e10U;
3762}
3763static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_f(u32 v)
3764{
3765 return (v & 0x1U) << 0U;
3766}
3767static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_on_v(void)
3768{
3769 return 0x00000001U;
3770}
3771static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_m(void)
3772{
3773 return 0x1U << 31U;
3774}
3775static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_v(u32 r)
3776{
3777 return (r >> 31U) & 0x1U;
3778}
3779static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_enable_f(void)
3780{
3781 return 0x80000000U;
3782}
3783static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f(void)
3784{
3785 return 0x0U;
3786}
3787static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_m(void)
3788{
3789 return 0x1U << 3U;
3790}
3791static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_enable_f(void)
3792{
3793 return 0x8U;
3794}
3795static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_disable_f(void)
3796{
3797 return 0x0U;
3798}
3799static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void)
3800{
3801 return 0x1U << 30U;
3802}
3803static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_v(u32 r)
3804{
3805 return (r >> 30U) & 0x1U;
3806}
3807static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f(void)
3808{
3809 return 0x40000000U;
3810}
3811
3812static inline u32 gr_gpc0_gpccs_falcon_irqstat_r(void)
3813{
3814 return 0x00502008U;
3815}
3816static inline u32 gr_gpc0_gpccs_falcon_irqmode_r(void)
3817{
3818 return 0x0050200cU;
3819}
3820static inline u32 gr_gpc0_gpccs_falcon_irqmask_r(void)
3821{
3822 return 0x00502018U;
3823}
3824static inline u32 gr_gpc0_gpccs_falcon_irqdest_r(void)
3825{
3826 return 0x0050201cU;
3827}
3828static inline u32 gr_gpc0_gpccs_falcon_debug1_r(void)
3829{
3830 return 0x00502090U;
3831}
3832static inline u32 gr_gpc0_gpccs_falcon_debuginfo_r(void)
3833{
3834 return 0x00502094U;
3835}
3836static inline u32 gr_gpc0_gpccs_falcon_engctl_r(void)
3837{
3838 return 0x005020a4U;
3839}
3840static inline u32 gr_gpc0_gpccs_falcon_curctx_r(void)
3841{
3842 return 0x00502050U;
3843}
3844static inline u32 gr_gpc0_gpccs_falcon_nxtctx_r(void)
3845{
3846 return 0x00502054U;
3847}
3848static inline u32 gr_gpc0_gpccs_ctxsw_mailbox_r(u32 i)
3849{
3850 return 0x00502800U + i*4U;
3851}
3852static inline u32 gr_gpc0_gpccs_falcon_icd_cmd_r(void)
3853{
3854 return 0x00502200U;
3855}
3856static inline u32 gr_gpc0_gpccs_falcon_icd_cmd_opc_rreg_f(void)
3857{
3858 return 0x8U;
3859}
3860static inline u32 gr_gpc0_gpccs_falcon_icd_cmd_idx_f(u32 v)
3861{
3862 return (v & 0x1fU) << 8U;
3863}
3864static inline u32 gr_gpc_gpccs_falcon_icd_rdata_r(void)
3865{
3866 return 0x0050220cU;
3867}
3868#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-30 18:14:13 -0400