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1/*
2 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef NVGPU_ERROR_NOTIFIER_H
24#define NVGPU_ERROR_NOTIFIER_H
25
26#include <nvgpu/types.h>
27
28struct channel_gk20a;
29
30enum {
31 NVGPU_ERR_NOTIFIER_FIFO_ERROR_IDLE_TIMEOUT = 0,
32 NVGPU_ERR_NOTIFIER_GR_ERROR_SW_METHOD,
33 NVGPU_ERR_NOTIFIER_GR_ERROR_SW_NOTIFY,
34 NVGPU_ERR_NOTIFIER_GR_EXCEPTION,
35 NVGPU_ERR_NOTIFIER_GR_SEMAPHORE_TIMEOUT,
36 NVGPU_ERR_NOTIFIER_GR_ILLEGAL_NOTIFY,
37 NVGPU_ERR_NOTIFIER_FIFO_ERROR_MMU_ERR_FLT,
38 NVGPU_ERR_NOTIFIER_PBDMA_ERROR,
39 NVGPU_ERR_NOTIFIER_FECS_ERR_UNIMP_FIRMWARE_METHOD,
40 NVGPU_ERR_NOTIFIER_RESETCHANNEL_VERIF_ERROR,
41 NVGPU_ERR_NOTIFIER_PBDMA_PUSHBUFFER_CRC_MISMATCH,
42};
43
44void nvgpu_set_error_notifier_locked(struct channel_gk20a *ch, u32 error);
45void nvgpu_set_error_notifier(struct channel_gk20a *ch, u32 error);
46void nvgpu_set_error_notifier_if_empty(struct channel_gk20a *ch, u32 error);
47bool nvgpu_is_error_notifier_set(struct channel_gk20a *ch, u32 error_notifier);
48
49#endif /* NVGPU_ERROR_NOTIFIER_H */