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diff --git a/include/nvgpu/enabled.h b/include/nvgpu/enabled.h
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1/*
2 * Copyright (c) 2017-2022, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef NVGPU_ENABLED_H
24#define NVGPU_ENABLED_H
25
26struct gk20a;
27
28#include <nvgpu/types.h>
29
30/*
31 * Available flags that describe what's enabled and what's not in the GPU. Each
32 * flag here is defined by it's offset in a bitmap.
33 */
34#define NVGPU_IS_FMODEL 1
35#define NVGPU_DRIVER_IS_DYING 2
36#define NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP 3
37#define NVGPU_FECS_TRACE_VA 4
38#define NVGPU_CAN_RAILGATE 5
39#define NVGPU_KERNEL_IS_DYING 6
40#define NVGPU_FECS_TRACE_FEATURE_CONTROL 7
41
42/*
43 * ECC flags
44 */
45/* SM LRF ECC is enabled */
46#define NVGPU_ECC_ENABLED_SM_LRF 8
47/* SM SHM ECC is enabled */
48#define NVGPU_ECC_ENABLED_SM_SHM 9
49/* TEX ECC is enabled */
50#define NVGPU_ECC_ENABLED_TEX 10
51/* L2 ECC is enabled */
52#define NVGPU_ECC_ENABLED_LTC 11
53/* SM L1 DATA ECC is enabled */
54#define NVGPU_ECC_ENABLED_SM_L1_DATA 12
55/* SM L1 TAG ECC is enabled */
56#define NVGPU_ECC_ENABLED_SM_L1_TAG 13
57/* SM CBU ECC is enabled */
58#define NVGPU_ECC_ENABLED_SM_CBU 14
59/* SM ICAHE ECC is enabled */
60#define NVGPU_ECC_ENABLED_SM_ICACHE 15
61
62/*
63 * MM flags.
64 */
65#define NVGPU_MM_UNIFY_ADDRESS_SPACES 16
66/* false if vidmem aperture actually points to sysmem */
67#define NVGPU_MM_HONORS_APERTURE 17
68/* unified or split memory with separate vidmem? */
69#define NVGPU_MM_UNIFIED_MEMORY 18
70/* User-space managed address spaces support */
71#define NVGPU_SUPPORT_USERSPACE_MANAGED_AS 20
72/* IO coherence support is available */
73#define NVGPU_SUPPORT_IO_COHERENCE 21
74/* MAP_BUFFER_EX with partial mappings */
75#define NVGPU_SUPPORT_PARTIAL_MAPPINGS 22
76/* MAP_BUFFER_EX with sparse allocations */
77#define NVGPU_SUPPORT_SPARSE_ALLOCS 23
78/* Direct PTE kind control is supported (map_buffer_ex) */
79#define NVGPU_SUPPORT_MAP_DIRECT_KIND_CTRL 24
80/* Support batch mapping */
81#define NVGPU_SUPPORT_MAP_BUFFER_BATCH 25
82/* Use coherent aperture for sysmem. */
83#define NVGPU_USE_COHERENT_SYSMEM 26
84/* Use physical scatter tables instead of IOMMU */
85#define NVGPU_MM_USE_PHYSICAL_SG 27
86/* WAR for gm20b chips. */
87#define NVGPU_MM_FORCE_128K_PMU_VM 28
88/* SW ERRATA to disable L3 alloc Bit of the physical address.
89 * Bit number varies between SOCs.
90 * E.g. 64GB physical RAM support for gv11b requires this SW errata
91 * to be enabled.
92 */
93#define NVGPU_DISABLE_L3_SUPPORT 29
94/*
95 * Host flags
96 */
97#define NVGPU_HAS_SYNCPOINTS 30
98/* sync fence FDs are available in, e.g., submit_gpfifo */
99#define NVGPU_SUPPORT_SYNC_FENCE_FDS 31
100/* NVGPU_DBG_GPU_IOCTL_CYCLE_STATS is available */
101#define NVGPU_SUPPORT_CYCLE_STATS 32
102/* NVGPU_DBG_GPU_IOCTL_CYCLE_STATS_SNAPSHOT is available */
103#define NVGPU_SUPPORT_CYCLE_STATS_SNAPSHOT 33
104/* Both gpu driver and device support TSG */
105#define NVGPU_SUPPORT_TSG 34
106/* Fast deterministic submits with no job tracking are supported */
107#define NVGPU_SUPPORT_DETERMINISTIC_SUBMIT_NO_JOBTRACKING 35
108/* Deterministic submits are supported even with job tracking */
109#define NVGPU_SUPPORT_DETERMINISTIC_SUBMIT_FULL 36
110/* NVGPU_IOCTL_CHANNEL_RESCHEDULE_RUNLIST is available */
111#define NVGPU_SUPPORT_RESCHEDULE_RUNLIST 37
112
113/* NVGPU_GPU_IOCTL_GET_EVENT_FD is available */
114#define NVGPU_SUPPORT_DEVICE_EVENTS 38
115/* FECS context switch tracing is available */
116#define NVGPU_SUPPORT_FECS_CTXSW_TRACE 39
117
118/* NVGPU_GPU_IOCTL_SET_DETERMINISTIC_OPTS is available */
119#define NVGPU_SUPPORT_DETERMINISTIC_OPTS 40
120
121/*
122 * Security flags
123 */
124
125#define NVGPU_SEC_SECUREGPCCS 41
126#define NVGPU_SEC_PRIVSECURITY 42
127/* VPR is supported */
128#define NVGPU_SUPPORT_VPR 43
129
130/*
131 * Nvlink flags
132 */
133
134#define NVGPU_SUPPORT_NVLINK 45
135/*
136 * PMU flags.
137 */
138/* perfmon enabled or disabled for PMU */
139#define NVGPU_PMU_PERFMON 48
140#define NVGPU_PMU_PSTATE 49
141#define NVGPU_PMU_ZBC_SAVE 50
142#define NVGPU_PMU_FECS_BOOTSTRAP_DONE 51
143#define NVGPU_GPU_CAN_BLCG 52
144#define NVGPU_GPU_CAN_SLCG 53
145#define NVGPU_GPU_CAN_ELCG 54
146/* Clock control support */
147#define NVGPU_SUPPORT_CLOCK_CONTROLS 55
148/* NVGPU_GPU_IOCTL_GET_VOLTAGE is available */
149#define NVGPU_SUPPORT_GET_VOLTAGE 56
150/* NVGPU_GPU_IOCTL_GET_CURRENT is available */
151#define NVGPU_SUPPORT_GET_CURRENT 57
152/* NVGPU_GPU_IOCTL_GET_POWER is available */
153#define NVGPU_SUPPORT_GET_POWER 58
154/* NVGPU_GPU_IOCTL_GET_TEMPERATURE is available */
155#define NVGPU_SUPPORT_GET_TEMPERATURE 59
156/* NVGPU_GPU_IOCTL_SET_THERM_ALERT_LIMIT is available */
157#define NVGPU_SUPPORT_SET_THERM_ALERT_LIMIT 60
158
159/* whether to run PREOS binary on dGPUs */
160#define NVGPU_PMU_RUN_PREOS 61
161
162/* set if ASPM is enabled; only makes sense for PCI */
163#define NVGPU_SUPPORT_ASPM 62
164/* subcontexts are available */
165#define NVGPU_SUPPORT_TSG_SUBCONTEXTS 63
166/* Simultaneous Compute and Graphics (SCG) is available */
167#define NVGPU_SUPPORT_SCG 64
168
169/* GPU_VA address of a syncpoint is supported */
170#define NVGPU_SUPPORT_SYNCPOINT_ADDRESS 65
171/* Allocating per-channel syncpoint in user space is supported */
172#define NVGPU_SUPPORT_USER_SYNCPOINT 66
173
174/* USERMODE enable bit */
175#define NVGPU_SUPPORT_USERMODE_SUBMIT 67
176
177/* Multiple WPR support */
178#define NVGPU_SUPPORT_MULTIPLE_WPR 68
179
180/* SEC2 RTOS support*/
181#define NVGPU_SUPPORT_SEC2_RTOS 69
182
183/* NVGPU_GPU_IOCTL_GET_GPU_LOAD is available */
184#define NVGPU_SUPPORT_GET_GPU_LOAD 70
185
186/* PLATFORM_ATOMIC support */
187#define NVGPU_SUPPORT_PLATFORM_ATOMIC 71
188
189/* NVGPU_GPU_IOCTL_SET_MMU_DEBUG_MODE is available */
190#define NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE 72
191
192/*
193 * Must be greater than the largest bit offset in the above list.
194 */
195#define NVGPU_MAX_ENABLED_BITS 73U
196
197/**
198 * nvgpu_is_enabled - Check if the passed flag is enabled.
199 *
200 * @g - The GPU.
201 * @flag - Which flag to check.
202 *
203 * Returns true if the passed @flag is true; false otherwise.
204 */
205bool nvgpu_is_enabled(struct gk20a *g, int flag);
206
207/**
208 * __nvgpu_set_enabled - Set the state of a flag.
209 *
210 * @g - The GPU.
211 * @flag - Which flag to modify.
212 * @state - The state to set the flag to.
213 *
214 * Set the state of the passed @flag to @state.
215 */
216void __nvgpu_set_enabled(struct gk20a *g, int flag, bool state);
217
218int nvgpu_init_enabled_flags(struct gk20a *g);
219void nvgpu_free_enabled_flags(struct gk20a *g);
220
221#endif /* NVGPU_ENABLED_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-30 08:13:08 -0400