diff options
Diffstat (limited to 'include/nvgpu/atomic.h')
| -rw-r--r-- | include/nvgpu/atomic.h | 130 |
1 files changed, 0 insertions, 130 deletions
diff --git a/include/nvgpu/atomic.h b/include/nvgpu/atomic.h deleted file mode 100644 index 3edc1fc..0000000 --- a/include/nvgpu/atomic.h +++ /dev/null | |||
| @@ -1,130 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. | ||
| 3 | * | ||
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
| 5 | * copy of this software and associated documentation files (the "Software"), | ||
| 6 | * to deal in the Software without restriction, including without limitation | ||
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
| 8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
| 9 | * Software is furnished to do so, subject to the following conditions: | ||
| 10 | * | ||
| 11 | * The above copyright notice and this permission notice shall be included in | ||
| 12 | * all copies or substantial portions of the Software. | ||
| 13 | * | ||
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
| 17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
| 18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
| 19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
| 20 | * DEALINGS IN THE SOFTWARE. | ||
| 21 | */ | ||
| 22 | #ifndef NVGPU_ATOMIC_H | ||
| 23 | #define NVGPU_ATOMIC_H | ||
| 24 | |||
| 25 | #ifdef __KERNEL__ | ||
| 26 | #include <nvgpu/linux/atomic.h> | ||
| 27 | #elif defined(__NVGPU_POSIX__) | ||
| 28 | #include <nvgpu/posix/atomic.h> | ||
| 29 | #else | ||
| 30 | #include <nvgpu_rmos/include/atomic.h> | ||
| 31 | #endif | ||
| 32 | |||
| 33 | #define NVGPU_ATOMIC_INIT(i) __nvgpu_atomic_init(i) | ||
| 34 | #define NVGPU_ATOMIC64_INIT(i) __nvgpu_atomic64_init(i) | ||
| 35 | |||
| 36 | static inline void nvgpu_atomic_set(nvgpu_atomic_t *v, int i) | ||
| 37 | { | ||
| 38 | __nvgpu_atomic_set(v, i); | ||
| 39 | } | ||
| 40 | static inline int nvgpu_atomic_read(nvgpu_atomic_t *v) | ||
| 41 | { | ||
| 42 | return __nvgpu_atomic_read(v); | ||
| 43 | } | ||
| 44 | static inline void nvgpu_atomic_inc(nvgpu_atomic_t *v) | ||
| 45 | { | ||
| 46 | __nvgpu_atomic_inc(v); | ||
| 47 | } | ||
| 48 | static inline int nvgpu_atomic_inc_return(nvgpu_atomic_t *v) | ||
| 49 | { | ||
| 50 | return __nvgpu_atomic_inc_return(v); | ||
| 51 | } | ||
| 52 | static inline void nvgpu_atomic_dec(nvgpu_atomic_t *v) | ||
| 53 | { | ||
| 54 | __nvgpu_atomic_dec(v); | ||
| 55 | } | ||
| 56 | static inline int nvgpu_atomic_dec_return(nvgpu_atomic_t *v) | ||
| 57 | { | ||
| 58 | return __nvgpu_atomic_dec_return(v); | ||
| 59 | } | ||
| 60 | static inline int nvgpu_atomic_cmpxchg(nvgpu_atomic_t *v, int old, int new) | ||
| 61 | { | ||
| 62 | return __nvgpu_atomic_cmpxchg(v, old, new); | ||
| 63 | } | ||
| 64 | static inline int nvgpu_atomic_xchg(nvgpu_atomic_t *v, int new) | ||
| 65 | { | ||
| 66 | return __nvgpu_atomic_xchg(v, new); | ||
| 67 | } | ||
| 68 | static inline bool nvgpu_atomic_inc_and_test(nvgpu_atomic_t *v) | ||
| 69 | { | ||
| 70 | return __nvgpu_atomic_inc_and_test(v); | ||
| 71 | } | ||
| 72 | static inline bool nvgpu_atomic_dec_and_test(nvgpu_atomic_t *v) | ||
| 73 | { | ||
| 74 | return __nvgpu_atomic_dec_and_test(v); | ||
| 75 | } | ||
| 76 | static inline bool nvgpu_atomic_sub_and_test(int i, nvgpu_atomic_t *v) | ||
| 77 | { | ||
| 78 | return __nvgpu_atomic_sub_and_test(i, v); | ||
| 79 | } | ||
| 80 | static inline int nvgpu_atomic_add_return(int i, nvgpu_atomic_t *v) | ||
| 81 | { | ||
| 82 | return __nvgpu_atomic_add_return(i, v); | ||
| 83 | } | ||
| 84 | static inline int nvgpu_atomic_add_unless(nvgpu_atomic_t *v, int a, int u) | ||
| 85 | { | ||
| 86 | return __nvgpu_atomic_add_unless(v, a, u); | ||
| 87 | } | ||
| 88 | static inline void nvgpu_atomic64_set(nvgpu_atomic64_t *v, long i) | ||
| 89 | { | ||
| 90 | return __nvgpu_atomic64_set(v, i); | ||
| 91 | } | ||
| 92 | static inline long nvgpu_atomic64_read(nvgpu_atomic64_t *v) | ||
| 93 | { | ||
| 94 | return __nvgpu_atomic64_read(v); | ||
| 95 | } | ||
| 96 | static inline void nvgpu_atomic64_add(long x, nvgpu_atomic64_t *v) | ||
| 97 | { | ||
| 98 | __nvgpu_atomic64_add(x, v); | ||
| 99 | } | ||
| 100 | static inline void nvgpu_atomic64_inc(nvgpu_atomic64_t *v) | ||
| 101 | { | ||
| 102 | __nvgpu_atomic64_inc(v); | ||
| 103 | } | ||
| 104 | static inline long nvgpu_atomic64_inc_return(nvgpu_atomic64_t *v) | ||
| 105 | { | ||
| 106 | return __nvgpu_atomic64_inc_return(v); | ||
| 107 | } | ||
| 108 | static inline void nvgpu_atomic64_dec(nvgpu_atomic64_t *v) | ||
| 109 | { | ||
| 110 | __nvgpu_atomic64_dec(v); | ||
| 111 | } | ||
| 112 | static inline void nvgpu_atomic64_dec_return(nvgpu_atomic64_t *v) | ||
| 113 | { | ||
| 114 | __nvgpu_atomic64_dec_return(v); | ||
| 115 | } | ||
| 116 | static inline long nvgpu_atomic64_cmpxchg(nvgpu_atomic64_t *v, long old, | ||
| 117 | long new) | ||
| 118 | { | ||
| 119 | return __nvgpu_atomic64_cmpxchg(v, old, new); | ||
| 120 | } | ||
| 121 | static inline void nvgpu_atomic64_sub(long x, nvgpu_atomic64_t *v) | ||
| 122 | { | ||
| 123 | __nvgpu_atomic64_sub(x, v); | ||
| 124 | } | ||
| 125 | static inline long nvgpu_atomic64_sub_return(long x, nvgpu_atomic64_t *v) | ||
| 126 | { | ||
| 127 | return __nvgpu_atomic64_sub_return(x, v); | ||
| 128 | } | ||
| 129 | |||
| 130 | #endif /* NVGPU_ATOMIC_H */ | ||