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-rw-r--r--include/nvgpu/acr/acr_flcnbl.h144
-rw-r--r--include/nvgpu/acr/acr_lsfm.h328
-rw-r--r--include/nvgpu/acr/acr_objflcn.h91
-rw-r--r--include/nvgpu/acr/acr_objlsfm.h97
-rw-r--r--include/nvgpu/acr/nvgpu_acr.h192
5 files changed, 0 insertions, 852 deletions
diff --git a/include/nvgpu/acr/acr_flcnbl.h b/include/nvgpu/acr/acr_flcnbl.h
deleted file mode 100644
index ad697b2..0000000
--- a/include/nvgpu/acr/acr_flcnbl.h
+++ /dev/null
@@ -1,144 +0,0 @@
1/*
2 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22#ifndef NVGPU_ACR_FLCNBL_H
23#define NVGPU_ACR_FLCNBL_H
24
25#include <nvgpu/flcnif_cmn.h>
26
27#ifndef NVGPU_ACR_H
28#warning "acr_flcnbl.h not included from nvgpu_acr.h!" \
29 "Include nvgpu_acr.h instead of acr_xxx.h to get access to ACR interfaces"
30#endif
31
32/*
33 * Structure used by the boot-loader to load the rest of the code. This has
34 * to be filled by NVGPU and copied into DMEM at offset provided in the
35 * hsflcn_bl_desc.bl_desc_dmem_load_off.
36 */
37struct flcn_bl_dmem_desc {
38 u32 reserved[4]; /*Should be the first element..*/
39 u32 signature[4]; /*Should be the first element..*/
40 u32 ctx_dma;
41 u32 code_dma_base;
42 u32 non_sec_code_off;
43 u32 non_sec_code_size;
44 u32 sec_code_off;
45 u32 sec_code_size;
46 u32 code_entry_point;
47 u32 data_dma_base;
48 u32 data_size;
49 u32 code_dma_base1;
50 u32 data_dma_base1;
51};
52
53struct flcn_bl_dmem_desc_v1 {
54 u32 reserved[4]; /*Should be the first element..*/
55 u32 signature[4]; /*Should be the first element..*/
56 u32 ctx_dma;
57 struct falc_u64 code_dma_base;
58 u32 non_sec_code_off;
59 u32 non_sec_code_size;
60 u32 sec_code_off;
61 u32 sec_code_size;
62 u32 code_entry_point;
63 struct falc_u64 data_dma_base;
64 u32 data_size;
65 u32 argc;
66 u32 argv;
67};
68
69/*
70 * The header used by NVGPU to figure out code and data sections of bootloader
71 *
72 * bl_code_off - Offset of code section in the image
73 * bl_code_size - Size of code section in the image
74 * bl_data_off - Offset of data section in the image
75 * bl_data_size - Size of data section in the image
76 */
77struct flcn_bl_img_hdr {
78 u32 bl_code_off;
79 u32 bl_code_size;
80 u32 bl_data_off;
81 u32 bl_data_size;
82};
83
84/*
85 * The descriptor used by NVGPU to figure out the requirements of bootloader
86 *
87 * bl_start_tag - Starting tag of bootloader
88 * bl_desc_dmem_load_off - Dmem offset where _def_rm_flcn_bl_dmem_desc
89 * to be loaded
90 * bl_img_hdr - Description of the image
91 */
92struct hsflcn_bl_desc {
93 u32 bl_start_tag;
94 u32 bl_desc_dmem_load_off;
95 struct flcn_bl_img_hdr bl_img_hdr;
96};
97
98/*
99 * Legacy structure used by the current PMU/DPU bootloader.
100 */
101struct loader_config {
102 u32 dma_idx;
103 u32 code_dma_base; /* upper 32-bits of 40-bit dma address */
104 u32 code_size_total;
105 u32 code_size_to_load;
106 u32 code_entry_point;
107 u32 data_dma_base; /* upper 32-bits of 40-bit dma address */
108 u32 data_size; /* initialized data of the application */
109 u32 overlay_dma_base; /* upper 32-bits of the 40-bit dma address */
110 u32 argc;
111 u32 argv;
112 u16 code_dma_base1; /* upper 7 bits of 47-bit dma address */
113 u16 data_dma_base1; /* upper 7 bits of 47-bit dma address */
114 u16 overlay_dma_base1; /* upper 7 bits of the 47-bit dma address */
115};
116
117struct loader_config_v1 {
118 u32 reserved;
119 u32 dma_idx;
120 struct falc_u64 code_dma_base;
121 u32 code_size_total;
122 u32 code_size_to_load;
123 u32 code_entry_point;
124 struct falc_u64 data_dma_base;
125 u32 data_size;
126 struct falc_u64 overlay_dma_base;
127 u32 argc;
128 u32 argv;
129};
130
131/*
132 * Union of all supported structures used by bootloaders.
133 */
134union flcn_bl_generic_desc {
135 struct flcn_bl_dmem_desc bl_dmem_desc;
136 struct loader_config loader_cfg;
137};
138
139union flcn_bl_generic_desc_v1 {
140 struct flcn_bl_dmem_desc_v1 bl_dmem_desc_v1;
141 struct loader_config_v1 loader_cfg_v1;
142};
143
144#endif /* NVGPU_ACR_FLCNBL_H */
diff --git a/include/nvgpu/acr/acr_lsfm.h b/include/nvgpu/acr/acr_lsfm.h
deleted file mode 100644
index ed58552..0000000
--- a/include/nvgpu/acr/acr_lsfm.h
+++ /dev/null
@@ -1,328 +0,0 @@
1/*
2 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22#ifndef NVGPU_ACR_LSFM_H
23#define NVGPU_ACR_LSFM_H
24
25#ifndef NVGPU_ACR_H
26#warning "acr_lsfm.h not included from nvgpu_acr.h!" \
27 "Include nvgpu_acr.h instead of acr_xxx.h to get access to ACR interfaces"
28#endif
29
30/*
31 * READ/WRITE masks for WPR region
32 */
33/* Readable only from level 2 and 3 client */
34#define LSF_WPR_REGION_RMASK (0xC)
35/* Writable only from level 2 and 3 client */
36#define LSF_WPR_REGION_WMASK (0xC)
37/* Readable only from level 3 client */
38#define LSF_WPR_REGION_RMASK_SUB_WPR_ENABLED (0x8)
39/* Writable only from level 3 client */
40#define LSF_WPR_REGION_WMASK_SUB_WPR_ENABLED (0x8)
41/* Disallow read mis-match for all clients */
42#define LSF_WPR_REGION_ALLOW_READ_MISMATCH_NO (0x0)
43/* Disallow write mis-match for all clients */
44#define LSF_WPR_REGION_ALLOW_WRITE_MISMATCH_NO (0x0)
45
46/*
47 * Falcon Id Defines
48 * Defines a common Light Secure Falcon identifier.
49 */
50#define LSF_FALCON_ID_PMU (0)
51#define LSF_FALCON_ID_GSPLITE (1)
52#define LSF_FALCON_ID_FECS (2)
53#define LSF_FALCON_ID_GPCCS (3)
54#define LSF_FALCON_ID_SEC2 (7)
55#define LSF_FALCON_ID_END (11)
56#define LSF_FALCON_ID_INVALID (0xFFFFFFFF)
57
58/*
59 * Light Secure Falcon Ucode Description Defines
60 * This structure is prelim and may change as the ucode signing flow evolves.
61 */
62struct lsf_ucode_desc {
63 u8 prd_keys[2][16];
64 u8 dbg_keys[2][16];
65 u32 b_prd_present;
66 u32 b_dbg_present;
67 u32 falcon_id;
68};
69
70struct lsf_ucode_desc_v1 {
71 u8 prd_keys[2][16];
72 u8 dbg_keys[2][16];
73 u32 b_prd_present;
74 u32 b_dbg_present;
75 u32 falcon_id;
76 u32 bsupports_versioning;
77 u32 version;
78 u32 dep_map_count;
79 u8 dep_map[LSF_FALCON_ID_END * 2 * 4];
80 u8 kdf[16];
81};
82
83/*
84 * Light Secure WPR Header
85 * Defines state allowing Light Secure Falcon bootstrapping.
86 */
87struct lsf_wpr_header {
88 u32 falcon_id;
89 u32 lsb_offset;
90 u32 bootstrap_owner;
91 u32 lazy_bootstrap;
92 u32 status;
93};
94
95struct lsf_wpr_header_v1 {
96 u32 falcon_id;
97 u32 lsb_offset;
98 u32 bootstrap_owner;
99 u32 lazy_bootstrap;
100 u32 bin_version;
101 u32 status;
102};
103
104
105/*
106 * LSF shared SubWpr Header
107 *
108 * use_case_id - Shared SubWpr use case ID (updated by nvgpu)
109 * start_addr - start address of subWpr (updated by nvgpu)
110 * size_4K - size of subWpr in 4K (updated by nvgpu)
111 */
112struct lsf_shared_sub_wpr_header {
113 u32 use_case_id;
114 u32 start_addr;
115 u32 size_4K;
116};
117
118/* shared sub_wpr use case IDs */
119enum {
120 LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_FRTS_VBIOS_TABLES = 1,
121 LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_PLAYREADY_SHARED_DATA = 2
122};
123
124#define LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_MAX \
125 LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_PLAYREADY_SHARED_DATA
126
127#define LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_INVALID (0xFFFFFFFF)
128
129#define MAX_SUPPORTED_SHARED_SUB_WPR_USE_CASES \
130 LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_MAX
131
132/* Static sizes of shared subWPRs */
133/* Minimum granularity supported is 4K */
134/* 1MB in 4K */
135#define LSF_SHARED_DATA_SUB_WPR_FRTS_VBIOS_TABLES_SIZE_IN_4K (0x100)
136/* 4K */
137#define LSF_SHARED_DATA_SUB_WPR_PLAYREADY_SHARED_DATA_SIZE_IN_4K (0x1)
138
139/*
140 * Bootstrap Owner Defines
141 */
142#define LSF_BOOTSTRAP_OWNER_DEFAULT (LSF_FALCON_ID_PMU)
143
144/*
145 * Image Status Defines
146 */
147#define LSF_IMAGE_STATUS_NONE (0)
148#define LSF_IMAGE_STATUS_COPY (1)
149#define LSF_IMAGE_STATUS_VALIDATION_CODE_FAILED (2)
150#define LSF_IMAGE_STATUS_VALIDATION_DATA_FAILED (3)
151#define LSF_IMAGE_STATUS_VALIDATION_DONE (4)
152#define LSF_IMAGE_STATUS_VALIDATION_SKIPPED (5)
153#define LSF_IMAGE_STATUS_BOOTSTRAP_READY (6)
154
155/*Light Secure Bootstrap header related defines*/
156#define NV_FLCN_ACR_LSF_FLAG_LOAD_CODE_AT_0_FALSE 0
157#define NV_FLCN_ACR_LSF_FLAG_LOAD_CODE_AT_0_TRUE 1
158#define NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_FALSE 0
159#define NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_TRUE 4
160#define NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_TRUE 8
161#define NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_FALSE 0
162
163/*
164 * Light Secure Bootstrap Header
165 * Defines state allowing Light Secure Falcon bootstrapping.
166 */
167struct lsf_lsb_header {
168 struct lsf_ucode_desc signature;
169 u32 ucode_off;
170 u32 ucode_size;
171 u32 data_size;
172 u32 bl_code_size;
173 u32 bl_imem_off;
174 u32 bl_data_off;
175 u32 bl_data_size;
176 u32 app_code_off;
177 u32 app_code_size;
178 u32 app_data_off;
179 u32 app_data_size;
180 u32 flags;
181};
182
183struct lsf_lsb_header_v1 {
184 struct lsf_ucode_desc_v1 signature;
185 u32 ucode_off;
186 u32 ucode_size;
187 u32 data_size;
188 u32 bl_code_size;
189 u32 bl_imem_off;
190 u32 bl_data_off;
191 u32 bl_data_size;
192 u32 app_code_off;
193 u32 app_code_size;
194 u32 app_data_off;
195 u32 app_data_size;
196 u32 flags;
197};
198
199/*
200 * Light Secure WPR Content Alignments
201 */
202#define LSF_WPR_HEADER_ALIGNMENT (256U)
203#define LSF_SUB_WPR_HEADER_ALIGNMENT (256U)
204#define LSF_LSB_HEADER_ALIGNMENT (256U)
205#define LSF_BL_DATA_ALIGNMENT (256U)
206#define LSF_BL_DATA_SIZE_ALIGNMENT (256U)
207#define LSF_BL_CODE_SIZE_ALIGNMENT (256U)
208#define LSF_DATA_SIZE_ALIGNMENT (256U)
209#define LSF_CODE_SIZE_ALIGNMENT (256U)
210
211/* MMU excepts sub_wpr sizes in units of 4K */
212#define SUB_WPR_SIZE_ALIGNMENT (4096U)
213
214/*
215 * Maximum WPR Header size
216 */
217#define LSF_WPR_HEADERS_TOTAL_SIZE_MAX \
218 (ALIGN_UP((sizeof(struct lsf_wpr_header_v1) * LSF_FALCON_ID_END), \
219 LSF_WPR_HEADER_ALIGNMENT))
220#define LSF_LSB_HEADER_TOTAL_SIZE_MAX (\
221 ALIGN_UP(sizeof(struct lsf_lsb_header_v1), LSF_LSB_HEADER_ALIGNMENT))
222
223/* Maximum SUB WPR header size */
224#define LSF_SUB_WPR_HEADERS_TOTAL_SIZE_MAX (ALIGN_UP( \
225 (sizeof(struct lsf_shared_sub_wpr_header) * \
226 LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_MAX), \
227 LSF_SUB_WPR_HEADER_ALIGNMENT))
228
229
230#define LSF_UCODE_DATA_ALIGNMENT 4096
231
232/* Defined for 1MB alignment */
233#define SHIFT_1MB (20)
234#define SHIFT_4KB (12)
235
236/*
237 * Supporting maximum of 2 regions.
238 * This is needed to pre-allocate space in DMEM
239 */
240#define NVGPU_FLCN_ACR_MAX_REGIONS (2)
241#define LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE (0x200)
242
243/*
244 * start_addr - Starting address of region
245 * end_addr - Ending address of region
246 * region_id - Region ID
247 * read_mask - Read Mask
248 * write_mask - WriteMask
249 * client_mask - Bit map of all clients currently using this region
250 */
251struct flcn_acr_region_prop {
252 u32 start_addr;
253 u32 end_addr;
254 u32 region_id;
255 u32 read_mask;
256 u32 write_mask;
257 u32 client_mask;
258};
259
260struct flcn_acr_region_prop_v1 {
261 u32 start_addr;
262 u32 end_addr;
263 u32 region_id;
264 u32 read_mask;
265 u32 write_mask;
266 u32 client_mask;
267 u32 shadowmMem_startaddress;
268};
269
270/*
271 * no_regions - Number of regions used.
272 * region_props - Region properties
273 */
274struct flcn_acr_regions {
275 u32 no_regions;
276 struct flcn_acr_region_prop region_props[NVGPU_FLCN_ACR_MAX_REGIONS];
277};
278
279struct flcn_acr_regions_v1 {
280 u32 no_regions;
281 struct flcn_acr_region_prop_v1 region_props[NVGPU_FLCN_ACR_MAX_REGIONS];
282};
283/*
284 * reserved_dmem-When the bootstrap owner has done bootstrapping other falcons,
285 * and need to switch into LS mode, it needs to have its own
286 * actual DMEM image copied into DMEM as part of LS setup. If
287 * ACR desc is at location 0, it will definitely get overwritten
288 * causing data corruption. Hence we are reserving 0x200 bytes
289 * to give room for any loading data. NOTE: This has to be the
290 * first member always
291 * signature - Signature of ACR ucode.
292 * wpr_region_id - Region ID holding the WPR header and its details
293 * wpr_offset - Offset from the WPR region holding the wpr header
294 * regions - Region descriptors
295 * nonwpr_ucode_blob_start -stores non-WPR start where kernel stores ucode blob
296 * nonwpr_ucode_blob_end -stores non-WPR end where kernel stores ucode blob
297 */
298struct flcn_acr_desc {
299 union {
300 u32 reserved_dmem[(LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE/4)];
301 u32 signatures[4];
302 } ucode_reserved_space;
303 /*Always 1st*/
304 u32 wpr_region_id;
305 u32 wpr_offset;
306 u32 mmu_mem_range;
307 struct flcn_acr_regions regions;
308 u32 nonwpr_ucode_blob_size;
309 u64 nonwpr_ucode_blob_start;
310};
311
312struct flcn_acr_desc_v1 {
313 union {
314 u32 reserved_dmem[(LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE/4)];
315 } ucode_reserved_space;
316 u32 signatures[4];
317 /*Always 1st*/
318 u32 wpr_region_id;
319 u32 wpr_offset;
320 u32 mmu_mem_range;
321 struct flcn_acr_regions_v1 regions;
322 u32 nonwpr_ucode_blob_size;
323 u64 nonwpr_ucode_blob_start;
324 u32 dummy[4]; /* ACR_BSI_VPR_DESC */
325};
326
327
328#endif /* NVGPU_ACR_LSFM_H */
diff --git a/include/nvgpu/acr/acr_objflcn.h b/include/nvgpu/acr/acr_objflcn.h
deleted file mode 100644
index 57b43c8..0000000
--- a/include/nvgpu/acr/acr_objflcn.h
+++ /dev/null
@@ -1,91 +0,0 @@
1/*
2 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22#ifndef NVGPU_ACR_OBJFLCN_H
23#define NVGPU_ACR_OBJFLCN_H
24
25#ifndef NVGPU_ACR_H
26#warning "acr_objflcn.h not included from nvgpu_acr.h!" \
27 "Include nvgpu_acr.h instead of acr_xxx.h to get access to ACR interfaces"
28#endif
29
30struct flcn_ucode_img {
31 u32 *header; /* only some falcons have header */
32 u32 *data;
33 struct pmu_ucode_desc *desc; /* only some falcons have descriptor */
34 u32 data_size;
35 void *fw_ver; /* CTRL_GPU_GET_FIRMWARE_VERSION_PARAMS struct */
36 u8 load_entire_os_data; /* load the whole osData section at boot time.*/
37 /* NULL if not a light secure falcon.*/
38 struct lsf_ucode_desc *lsf_desc;
39 /* True if there a resources to freed by the client. */
40 u8 free_res_allocs;
41 u32 flcn_inst;
42};
43
44struct flcn_ucode_img_v1 {
45 u32 *header;
46 u32 *data;
47 struct pmu_ucode_desc_v1 *desc;
48 u32 data_size;
49 void *fw_ver;
50 u8 load_entire_os_data;
51 struct lsf_ucode_desc_v1 *lsf_desc;
52 u8 free_res_allocs;
53 u32 flcn_inst;
54};
55
56/*
57 * Falcon UCODE header index.
58 */
59#define FLCN_NL_UCODE_HDR_OS_CODE_OFF_IND (0)
60#define FLCN_NL_UCODE_HDR_OS_CODE_SIZE_IND (1)
61#define FLCN_NL_UCODE_HDR_OS_DATA_OFF_IND (2)
62#define FLCN_NL_UCODE_HDR_OS_DATA_SIZE_IND (3)
63#define FLCN_NL_UCODE_HDR_NUM_APPS_IND (4)
64
65/*
66 * There are total N number of Apps with code and offset defined in UCODE header
67 * This macro provides the CODE and DATA offset and size of Ath application.
68 */
69#define FLCN_NL_UCODE_HDR_APP_CODE_START_IND (5)
70#define FLCN_NL_UCODE_HDR_APP_CODE_OFF_IND(N, A) \
71 (FLCN_NL_UCODE_HDR_APP_CODE_START_IND + (A*2))
72#define FLCN_NL_UCODE_HDR_APP_CODE_SIZE_IND(N, A) \
73 (FLCN_NL_UCODE_HDR_APP_CODE_START_IND + (A*2) + 1)
74#define FLCN_NL_UCODE_HDR_APP_CODE_END_IND(N) \
75 (FLCN_NL_UCODE_HDR_APP_CODE_START_IND + (N*2) - 1)
76
77#define FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) \
78 (FLCN_NL_UCODE_HDR_APP_CODE_END_IND(N) + 1)
79#define FLCN_NL_UCODE_HDR_APP_DATA_OFF_IND(N, A) \
80 (FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) + (A*2))
81#define FLCN_NL_UCODE_HDR_APP_DATA_SIZE_IND(N, A) \
82 (FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) + (A*2) + 1)
83#define FLCN_NL_UCODE_HDR_APP_DATA_END_IND(N) \
84 (FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) + (N*2) - 1)
85
86#define FLCN_NL_UCODE_HDR_OS_OVL_OFF_IND(N) \
87 (FLCN_NL_UCODE_HDR_APP_DATA_END_IND(N) + 1)
88#define FLCN_NL_UCODE_HDR_OS_OVL_SIZE_IND(N) \
89 (FLCN_NL_UCODE_HDR_APP_DATA_END_IND(N) + 2)
90
91#endif /* NVGPU_ACR_OBJFLCN_H */
diff --git a/include/nvgpu/acr/acr_objlsfm.h b/include/nvgpu/acr/acr_objlsfm.h
deleted file mode 100644
index e3769bb..0000000
--- a/include/nvgpu/acr/acr_objlsfm.h
+++ /dev/null
@@ -1,97 +0,0 @@
1/*
2 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22#ifndef NVGPU_ACR_OBJLSFM_H
23#define NVGPU_ACR_OBJLSFM_H
24
25#ifndef NVGPU_ACR_H
26#warning "acr_objlsfm.h not included from nvgpu_acr.h!" \
27 "Include nvgpu_acr.h instead of acr_xxx.h to get access to ACR interfaces"
28#endif
29
30#include "acr_flcnbl.h"
31#include "acr_objflcn.h"
32
33/*
34 * LSFM Managed Ucode Image
35 * next : Next image the list, NULL if last.
36 * wpr_header : WPR header for this ucode image
37 * lsb_header : LSB header for this ucode image
38 * bl_gen_desc : Bootloader generic desc structure for this ucode image
39 * bl_gen_desc_size : Sizeof bootloader desc structure for this ucode image
40 * full_ucode_size : Surface size required for final ucode image
41 * ucode_img : Ucode image info
42 */
43struct lsfm_managed_ucode_img {
44 struct lsfm_managed_ucode_img *next;
45 struct lsf_wpr_header wpr_header;
46 struct lsf_lsb_header lsb_header;
47 union flcn_bl_generic_desc bl_gen_desc;
48 u32 bl_gen_desc_size;
49 u32 full_ucode_size;
50 struct flcn_ucode_img ucode_img;
51};
52
53struct lsfm_managed_ucode_img_v2 {
54 struct lsfm_managed_ucode_img_v2 *next;
55 struct lsf_wpr_header_v1 wpr_header;
56 struct lsf_lsb_header_v1 lsb_header;
57 union flcn_bl_generic_desc_v1 bl_gen_desc;
58 u32 bl_gen_desc_size;
59 u32 full_ucode_size;
60 struct flcn_ucode_img_v1 ucode_img;
61};
62
63/*
64 * Defines the structure used to contain all generic information related to
65 * the LSFM.
66 * Contains the Light Secure Falcon Manager (LSFM) feature related data.
67 */
68struct ls_flcn_mgr {
69 u16 managed_flcn_cnt;
70 u32 wpr_size;
71 u32 disable_mask;
72 struct lsfm_managed_ucode_img *ucode_img_list;
73 void *wpr_client_req_state;/*PACR_CLIENT_REQUEST_STATE originally*/
74};
75
76/*
77 * LSFM SUB WPRs struct
78 * pnext : Next entry in the list, NULL if last
79 * sub_wpr_header : SubWpr Header struct
80 */
81struct lsfm_sub_wpr {
82 struct lsfm_sub_wpr *pnext;
83 struct lsf_shared_sub_wpr_header sub_wpr_header;
84};
85
86struct ls_flcn_mgr_v1 {
87 u16 managed_flcn_cnt;
88 u32 wpr_size;
89 u32 disable_mask;
90 struct lsfm_managed_ucode_img_v2 *ucode_img_list;
91 void *wpr_client_req_state;/*PACR_CLIENT_REQUEST_STATE originally*/
92 u16 managed_sub_wpr_count;
93 struct lsfm_sub_wpr *psub_wpr_list;
94};
95
96
97#endif /* NVGPU_ACR_OBJLSFM_H */
diff --git a/include/nvgpu/acr/nvgpu_acr.h b/include/nvgpu/acr/nvgpu_acr.h
deleted file mode 100644
index cdb7bb8..0000000
--- a/include/nvgpu/acr/nvgpu_acr.h
+++ /dev/null
@@ -1,192 +0,0 @@
1/*
2 * Copyright (c) 2016-2021, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef NVGPU_ACR_H
24#define NVGPU_ACR_H
25
26#include <nvgpu/falcon.h>
27
28#include "gk20a/mm_gk20a.h"
29
30#include "acr_lsfm.h"
31#include "acr_flcnbl.h"
32#include "acr_objlsfm.h"
33#include "acr_objflcn.h"
34
35struct nvgpu_firmware;
36struct gk20a;
37struct hs_acr_ops;
38struct hs_acr;
39struct nvgpu_acr;
40
41#define HSBIN_ACR_BL_UCODE_IMAGE "pmu_bl.bin"
42#define GM20B_HSBIN_ACR_PROD_UCODE "nv_acr_ucode_prod.bin"
43#define GM20B_HSBIN_ACR_DBG_UCODE "nv_acr_ucode_dbg.bin"
44#define HSBIN_ACR_UCODE_IMAGE "acr_ucode.bin"
45#define HSBIN_ACR_PROD_UCODE "acr_ucode_prod.bin"
46#define HSBIN_ACR_DBG_UCODE "acr_ucode_dbg.bin"
47#define HSBIN_ACR_AHESASC_PROD_UCODE "acr_ahesasc_prod_ucode.bin"
48#define HSBIN_ACR_ASB_PROD_UCODE "acr_asb_prod_ucode.bin"
49#define HSBIN_ACR_AHESASC_DBG_UCODE "acr_ahesasc_dbg_ucode.bin"
50#define HSBIN_ACR_ASB_DBG_UCODE "acr_asb_dbg_ucode.bin"
51
52#define LSF_SEC2_UCODE_IMAGE_BIN "sec2_ucode_image.bin"
53#define LSF_SEC2_UCODE_DESC_BIN "sec2_ucode_desc.bin"
54#define LSF_SEC2_UCODE_SIG_BIN "sec2_sig.bin"
55
56#define MAX_SUPPORTED_LSFM 3 /*PMU, FECS, GPCCS*/
57
58#define ACR_COMPLETION_TIMEOUT_MS 10000 /*in msec */
59
60#define PMU_SECURE_MODE (0x1)
61#define PMU_LSFM_MANAGED (0x2)
62
63struct bin_hdr {
64 /* 0x10de */
65 u32 bin_magic;
66 /* versioning of bin format */
67 u32 bin_ver;
68 /* Entire image size including this header */
69 u32 bin_size;
70 /*
71 * Header offset of executable binary metadata,
72 * start @ offset- 0x100 *
73 */
74 u32 header_offset;
75 /*
76 * Start of executable binary data, start @
77 * offset- 0x200
78 */
79 u32 data_offset;
80 /* Size of executable binary */
81 u32 data_size;
82};
83
84struct acr_fw_header {
85 u32 sig_dbg_offset;
86 u32 sig_dbg_size;
87 u32 sig_prod_offset;
88 u32 sig_prod_size;
89 u32 patch_loc;
90 u32 patch_sig;
91 u32 hdr_offset; /* This header points to acr_ucode_header_t210_load */
92 u32 hdr_size; /* Size of above header */
93};
94
95struct wpr_carveout_info {
96 u64 wpr_base;
97 u64 nonwpr_base;
98 u64 size;
99};
100
101/* ACR interfaces */
102
103struct hs_flcn_bl {
104 char *bl_fw_name;
105 struct nvgpu_firmware *hs_bl_fw;
106 struct hsflcn_bl_desc *hs_bl_desc;
107 struct bin_hdr *hs_bl_bin_hdr;
108 struct nvgpu_mem hs_bl_ucode;
109};
110
111struct hs_acr {
112 u32 acr_type;
113
114 /* HS bootloader to validate & load ACR ucode */
115 struct hs_flcn_bl acr_hs_bl;
116
117 /* ACR ucode */
118 char *acr_fw_name;
119 struct nvgpu_firmware *acr_fw;
120 struct nvgpu_mem acr_ucode;
121
122 union {
123 struct flcn_bl_dmem_desc bl_dmem_desc;
124 struct flcn_bl_dmem_desc_v1 bl_dmem_desc_v1;
125 };
126
127 void *ptr_bl_dmem_desc;
128 u32 bl_dmem_desc_size;
129
130 union{
131 struct flcn_acr_desc *acr_dmem_desc;
132 struct flcn_acr_desc_v1 *acr_dmem_desc_v1;
133 };
134
135 /* Falcon used to execute ACR ucode */
136 struct nvgpu_falcon *acr_flcn;
137
138 int (*acr_flcn_setup_hw_and_bl_bootstrap)(struct gk20a *g,
139 struct hs_acr *acr_desc,
140 struct nvgpu_falcon_bl_info *bl_info);
141};
142
143#define ACR_DEFAULT 0U
144#define ACR_AHESASC 1U
145#define ACR_ASB 2U
146
147struct nvgpu_acr {
148 struct gk20a *g;
149
150 u32 bootstrap_owner;
151 u32 max_supported_lsfm;
152 u32 capabilities;
153
154 /*
155 * non-wpr space to hold LSF ucodes,
156 * ACR does copy ucode from non-wpr to wpr
157 */
158 struct nvgpu_mem ucode_blob;
159 /*
160 * Even though this mem_desc wouldn't be used,
161 * the wpr region needs to be reserved in the
162 * allocator in dGPU case.
163 */
164 struct nvgpu_mem wpr_dummy;
165
166 /* ACR member for different types of ucode */
167 /* For older dgpu/tegra ACR cuode */
168 struct hs_acr acr;
169 /* ACR load split feature support */
170 struct hs_acr acr_ahesasc;
171 struct hs_acr acr_asb;
172
173 u32 pmu_args;
174 struct nvgpu_firmware *pmu_fw;
175 struct nvgpu_firmware *pmu_desc;
176
177 int (*prepare_ucode_blob)(struct gk20a *g, struct nvgpu_acr *acr);
178 void (*get_wpr_info)(struct gk20a *g, struct wpr_carveout_info *inf);
179 int (*alloc_blob_space)(struct gk20a *g, size_t size,
180 struct nvgpu_mem *mem);
181 int (*patch_wpr_info_to_ucode)(struct gk20a *g, struct nvgpu_acr *acr,
182 struct hs_acr *acr_desc, bool is_recovery);
183 int (*acr_fill_bl_dmem_desc)(struct gk20a *g,
184 struct nvgpu_acr *acr, struct hs_acr *acr_desc,
185 u32 *acr_ucode_header);
186 int (*bootstrap_hs_acr)(struct gk20a *g, struct nvgpu_acr *acr,
187 struct hs_acr *acr_desc);
188
189 void (*remove_support)(struct nvgpu_acr *acr);
190};
191#endif /* NVGPU_ACR_H */
192
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-30 20:22:45 -0400