aboutsummaryrefslogtreecommitdiffstats
path: root/include/nvgpu/acr/acr_lsfm.h
diff options
context:
space:
mode:
Diffstat (limited to 'include/nvgpu/acr/acr_lsfm.h')
-rw-r--r--include/nvgpu/acr/acr_lsfm.h328
1 files changed, 0 insertions, 328 deletions
diff --git a/include/nvgpu/acr/acr_lsfm.h b/include/nvgpu/acr/acr_lsfm.h
deleted file mode 100644
index ed58552..0000000
--- a/include/nvgpu/acr/acr_lsfm.h
+++ /dev/null
@@ -1,328 +0,0 @@
1/*
2 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22#ifndef NVGPU_ACR_LSFM_H
23#define NVGPU_ACR_LSFM_H
24
25#ifndef NVGPU_ACR_H
26#warning "acr_lsfm.h not included from nvgpu_acr.h!" \
27 "Include nvgpu_acr.h instead of acr_xxx.h to get access to ACR interfaces"
28#endif
29
30/*
31 * READ/WRITE masks for WPR region
32 */
33/* Readable only from level 2 and 3 client */
34#define LSF_WPR_REGION_RMASK (0xC)
35/* Writable only from level 2 and 3 client */
36#define LSF_WPR_REGION_WMASK (0xC)
37/* Readable only from level 3 client */
38#define LSF_WPR_REGION_RMASK_SUB_WPR_ENABLED (0x8)
39/* Writable only from level 3 client */
40#define LSF_WPR_REGION_WMASK_SUB_WPR_ENABLED (0x8)
41/* Disallow read mis-match for all clients */
42#define LSF_WPR_REGION_ALLOW_READ_MISMATCH_NO (0x0)
43/* Disallow write mis-match for all clients */
44#define LSF_WPR_REGION_ALLOW_WRITE_MISMATCH_NO (0x0)
45
46/*
47 * Falcon Id Defines
48 * Defines a common Light Secure Falcon identifier.
49 */
50#define LSF_FALCON_ID_PMU (0)
51#define LSF_FALCON_ID_GSPLITE (1)
52#define LSF_FALCON_ID_FECS (2)
53#define LSF_FALCON_ID_GPCCS (3)
54#define LSF_FALCON_ID_SEC2 (7)
55#define LSF_FALCON_ID_END (11)
56#define LSF_FALCON_ID_INVALID (0xFFFFFFFF)
57
58/*
59 * Light Secure Falcon Ucode Description Defines
60 * This structure is prelim and may change as the ucode signing flow evolves.
61 */
62struct lsf_ucode_desc {
63 u8 prd_keys[2][16];
64 u8 dbg_keys[2][16];
65 u32 b_prd_present;
66 u32 b_dbg_present;
67 u32 falcon_id;
68};
69
70struct lsf_ucode_desc_v1 {
71 u8 prd_keys[2][16];
72 u8 dbg_keys[2][16];
73 u32 b_prd_present;
74 u32 b_dbg_present;
75 u32 falcon_id;
76 u32 bsupports_versioning;
77 u32 version;
78 u32 dep_map_count;
79 u8 dep_map[LSF_FALCON_ID_END * 2 * 4];
80 u8 kdf[16];
81};
82
83/*
84 * Light Secure WPR Header
85 * Defines state allowing Light Secure Falcon bootstrapping.
86 */
87struct lsf_wpr_header {
88 u32 falcon_id;
89 u32 lsb_offset;
90 u32 bootstrap_owner;
91 u32 lazy_bootstrap;
92 u32 status;
93};
94
95struct lsf_wpr_header_v1 {
96 u32 falcon_id;
97 u32 lsb_offset;
98 u32 bootstrap_owner;
99 u32 lazy_bootstrap;
100 u32 bin_version;
101 u32 status;
102};
103
104
105/*
106 * LSF shared SubWpr Header
107 *
108 * use_case_id - Shared SubWpr use case ID (updated by nvgpu)
109 * start_addr - start address of subWpr (updated by nvgpu)
110 * size_4K - size of subWpr in 4K (updated by nvgpu)
111 */
112struct lsf_shared_sub_wpr_header {
113 u32 use_case_id;
114 u32 start_addr;
115 u32 size_4K;
116};
117
118/* shared sub_wpr use case IDs */
119enum {
120 LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_FRTS_VBIOS_TABLES = 1,
121 LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_PLAYREADY_SHARED_DATA = 2
122};
123
124#define LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_MAX \
125 LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_PLAYREADY_SHARED_DATA
126
127#define LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_INVALID (0xFFFFFFFF)
128
129#define MAX_SUPPORTED_SHARED_SUB_WPR_USE_CASES \
130 LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_MAX
131
132/* Static sizes of shared subWPRs */
133/* Minimum granularity supported is 4K */
134/* 1MB in 4K */
135#define LSF_SHARED_DATA_SUB_WPR_FRTS_VBIOS_TABLES_SIZE_IN_4K (0x100)
136/* 4K */
137#define LSF_SHARED_DATA_SUB_WPR_PLAYREADY_SHARED_DATA_SIZE_IN_4K (0x1)
138
139/*
140 * Bootstrap Owner Defines
141 */
142#define LSF_BOOTSTRAP_OWNER_DEFAULT (LSF_FALCON_ID_PMU)
143
144/*
145 * Image Status Defines
146 */
147#define LSF_IMAGE_STATUS_NONE (0)
148#define LSF_IMAGE_STATUS_COPY (1)
149#define LSF_IMAGE_STATUS_VALIDATION_CODE_FAILED (2)
150#define LSF_IMAGE_STATUS_VALIDATION_DATA_FAILED (3)
151#define LSF_IMAGE_STATUS_VALIDATION_DONE (4)
152#define LSF_IMAGE_STATUS_VALIDATION_SKIPPED (5)
153#define LSF_IMAGE_STATUS_BOOTSTRAP_READY (6)
154
155/*Light Secure Bootstrap header related defines*/
156#define NV_FLCN_ACR_LSF_FLAG_LOAD_CODE_AT_0_FALSE 0
157#define NV_FLCN_ACR_LSF_FLAG_LOAD_CODE_AT_0_TRUE 1
158#define NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_FALSE 0
159#define NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_TRUE 4
160#define NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_TRUE 8
161#define NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_FALSE 0
162
163/*
164 * Light Secure Bootstrap Header
165 * Defines state allowing Light Secure Falcon bootstrapping.
166 */
167struct lsf_lsb_header {
168 struct lsf_ucode_desc signature;
169 u32 ucode_off;
170 u32 ucode_size;
171 u32 data_size;
172 u32 bl_code_size;
173 u32 bl_imem_off;
174 u32 bl_data_off;
175 u32 bl_data_size;
176 u32 app_code_off;
177 u32 app_code_size;
178 u32 app_data_off;
179 u32 app_data_size;
180 u32 flags;
181};
182
183struct lsf_lsb_header_v1 {
184 struct lsf_ucode_desc_v1 signature;
185 u32 ucode_off;
186 u32 ucode_size;
187 u32 data_size;
188 u32 bl_code_size;
189 u32 bl_imem_off;
190 u32 bl_data_off;
191 u32 bl_data_size;
192 u32 app_code_off;
193 u32 app_code_size;
194 u32 app_data_off;
195 u32 app_data_size;
196 u32 flags;
197};
198
199/*
200 * Light Secure WPR Content Alignments
201 */
202#define LSF_WPR_HEADER_ALIGNMENT (256U)
203#define LSF_SUB_WPR_HEADER_ALIGNMENT (256U)
204#define LSF_LSB_HEADER_ALIGNMENT (256U)
205#define LSF_BL_DATA_ALIGNMENT (256U)
206#define LSF_BL_DATA_SIZE_ALIGNMENT (256U)
207#define LSF_BL_CODE_SIZE_ALIGNMENT (256U)
208#define LSF_DATA_SIZE_ALIGNMENT (256U)
209#define LSF_CODE_SIZE_ALIGNMENT (256U)
210
211/* MMU excepts sub_wpr sizes in units of 4K */
212#define SUB_WPR_SIZE_ALIGNMENT (4096U)
213
214/*
215 * Maximum WPR Header size
216 */
217#define LSF_WPR_HEADERS_TOTAL_SIZE_MAX \
218 (ALIGN_UP((sizeof(struct lsf_wpr_header_v1) * LSF_FALCON_ID_END), \
219 LSF_WPR_HEADER_ALIGNMENT))
220#define LSF_LSB_HEADER_TOTAL_SIZE_MAX (\
221 ALIGN_UP(sizeof(struct lsf_lsb_header_v1), LSF_LSB_HEADER_ALIGNMENT))
222
223/* Maximum SUB WPR header size */
224#define LSF_SUB_WPR_HEADERS_TOTAL_SIZE_MAX (ALIGN_UP( \
225 (sizeof(struct lsf_shared_sub_wpr_header) * \
226 LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_MAX), \
227 LSF_SUB_WPR_HEADER_ALIGNMENT))
228
229
230#define LSF_UCODE_DATA_ALIGNMENT 4096
231
232/* Defined for 1MB alignment */
233#define SHIFT_1MB (20)
234#define SHIFT_4KB (12)
235
236/*
237 * Supporting maximum of 2 regions.
238 * This is needed to pre-allocate space in DMEM
239 */
240#define NVGPU_FLCN_ACR_MAX_REGIONS (2)
241#define LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE (0x200)
242
243/*
244 * start_addr - Starting address of region
245 * end_addr - Ending address of region
246 * region_id - Region ID
247 * read_mask - Read Mask
248 * write_mask - WriteMask
249 * client_mask - Bit map of all clients currently using this region
250 */
251struct flcn_acr_region_prop {
252 u32 start_addr;
253 u32 end_addr;
254 u32 region_id;
255 u32 read_mask;
256 u32 write_mask;
257 u32 client_mask;
258};
259
260struct flcn_acr_region_prop_v1 {
261 u32 start_addr;
262 u32 end_addr;
263 u32 region_id;
264 u32 read_mask;
265 u32 write_mask;
266 u32 client_mask;
267 u32 shadowmMem_startaddress;
268};
269
270/*
271 * no_regions - Number of regions used.
272 * region_props - Region properties
273 */
274struct flcn_acr_regions {
275 u32 no_regions;
276 struct flcn_acr_region_prop region_props[NVGPU_FLCN_ACR_MAX_REGIONS];
277};
278
279struct flcn_acr_regions_v1 {
280 u32 no_regions;
281 struct flcn_acr_region_prop_v1 region_props[NVGPU_FLCN_ACR_MAX_REGIONS];
282};
283/*
284 * reserved_dmem-When the bootstrap owner has done bootstrapping other falcons,
285 * and need to switch into LS mode, it needs to have its own
286 * actual DMEM image copied into DMEM as part of LS setup. If
287 * ACR desc is at location 0, it will definitely get overwritten
288 * causing data corruption. Hence we are reserving 0x200 bytes
289 * to give room for any loading data. NOTE: This has to be the
290 * first member always
291 * signature - Signature of ACR ucode.
292 * wpr_region_id - Region ID holding the WPR header and its details
293 * wpr_offset - Offset from the WPR region holding the wpr header
294 * regions - Region descriptors
295 * nonwpr_ucode_blob_start -stores non-WPR start where kernel stores ucode blob
296 * nonwpr_ucode_blob_end -stores non-WPR end where kernel stores ucode blob
297 */
298struct flcn_acr_desc {
299 union {
300 u32 reserved_dmem[(LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE/4)];
301 u32 signatures[4];
302 } ucode_reserved_space;
303 /*Always 1st*/
304 u32 wpr_region_id;
305 u32 wpr_offset;
306 u32 mmu_mem_range;
307 struct flcn_acr_regions regions;
308 u32 nonwpr_ucode_blob_size;
309 u64 nonwpr_ucode_blob_start;
310};
311
312struct flcn_acr_desc_v1 {
313 union {
314 u32 reserved_dmem[(LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE/4)];
315 } ucode_reserved_space;
316 u32 signatures[4];
317 /*Always 1st*/
318 u32 wpr_region_id;
319 u32 wpr_offset;
320 u32 mmu_mem_range;
321 struct flcn_acr_regions_v1 regions;
322 u32 nonwpr_ucode_blob_size;
323 u64 nonwpr_ucode_blob_start;
324 u32 dummy[4]; /* ACR_BSI_VPR_DESC */
325};
326
327
328#endif /* NVGPU_ACR_LSFM_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-30 14:22:09 -0400