aboutsummaryrefslogtreecommitdiffstats
path: root/include/lpwr/rppg.c
diff options
context:
space:
mode:
Diffstat (limited to 'include/lpwr/rppg.c')
-rw-r--r--include/lpwr/rppg.c160
1 files changed, 160 insertions, 0 deletions
diff --git a/include/lpwr/rppg.c b/include/lpwr/rppg.c
new file mode 100644
index 0000000..13e8126
--- /dev/null
+++ b/include/lpwr/rppg.c
@@ -0,0 +1,160 @@
1/*
2 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#include <nvgpu/pmu.h>
24#include <nvgpu/gk20a.h>
25
26#include "gp106/bios_gp106.h"
27#include "pstate/pstate.h"
28#include "lpwr/rppg.h"
29
30static void pmu_handle_rppg_init_msg(struct gk20a *g, struct pmu_msg *msg,
31 void *param, u32 handle, u32 status)
32{
33 u32 *success = param;
34
35 if (status == 0) {
36 switch (msg->msg.pg.rppg_msg.cmn.msg_id) {
37 case NV_PMU_RPPG_MSG_ID_INIT_CTRL_ACK:
38 *success = 1;
39 nvgpu_pmu_dbg(g, "RPPG is acknowledged from PMU %x",
40 msg->msg.pg.msg_type);
41 break;
42 }
43 }
44
45 nvgpu_pmu_dbg(g, "RPPG is acknowledged from PMU %x",
46 msg->msg.pg.msg_type);
47}
48
49static u32 rppg_send_cmd(struct gk20a *g, struct nv_pmu_rppg_cmd *prppg_cmd)
50{
51 struct pmu_cmd cmd;
52 u32 seq;
53 u32 status = 0;
54 u32 success = 0;
55
56 memset(&cmd, 0, sizeof(struct pmu_cmd));
57 cmd.hdr.unit_id = PMU_UNIT_PG;
58 cmd.hdr.size = PMU_CMD_HDR_SIZE +
59 sizeof(struct nv_pmu_rppg_cmd);
60
61 cmd.cmd.pg.rppg_cmd.cmn.cmd_type = PMU_PMU_PG_CMD_ID_RPPG;
62 cmd.cmd.pg.rppg_cmd.cmn.cmd_id = prppg_cmd->cmn.cmd_id;
63
64 switch (prppg_cmd->cmn.cmd_id) {
65 case NV_PMU_RPPG_CMD_ID_INIT:
66 break;
67 case NV_PMU_RPPG_CMD_ID_INIT_CTRL:
68 cmd.cmd.pg.rppg_cmd.init_ctrl.ctrl_id =
69 prppg_cmd->init_ctrl.ctrl_id;
70 cmd.cmd.pg.rppg_cmd.init_ctrl.domain_id =
71 prppg_cmd->init_ctrl.domain_id;
72 break;
73 case NV_PMU_RPPG_CMD_ID_STATS_RESET:
74 cmd.cmd.pg.rppg_cmd.stats_reset.ctrl_id =
75 prppg_cmd->stats_reset.ctrl_id;
76 break;
77 default:
78 nvgpu_err(g, "Inivalid RPPG command %d",
79 prppg_cmd->cmn.cmd_id);
80 return -1;
81 }
82
83 status = nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
84 pmu_handle_rppg_init_msg, &success, &seq, ~0);
85 if (status) {
86 nvgpu_err(g, "Unable to submit parameter command %d",
87 prppg_cmd->cmn.cmd_id);
88 goto exit;
89 }
90
91 if (prppg_cmd->cmn.cmd_id == NV_PMU_RPPG_CMD_ID_INIT_CTRL) {
92 pmu_wait_message_cond(&g->pmu, gk20a_get_gr_idle_timeout(g),
93 &success, 1);
94 if (success == 0) {
95 status = -EINVAL;
96 nvgpu_err(g, "Ack for the parameter command %x",
97 prppg_cmd->cmn.cmd_id);
98 }
99 }
100
101exit:
102 return status;
103}
104
105static u32 rppg_init(struct gk20a *g)
106{
107 struct nv_pmu_rppg_cmd rppg_cmd;
108
109 rppg_cmd.init.cmd_id = NV_PMU_RPPG_CMD_ID_INIT;
110
111 return rppg_send_cmd(g, &rppg_cmd);
112}
113
114static u32 rppg_ctrl_init(struct gk20a *g, u8 ctrl_id)
115{
116 struct nv_pmu_rppg_cmd rppg_cmd;
117
118 rppg_cmd.init_ctrl.cmd_id = NV_PMU_RPPG_CMD_ID_INIT_CTRL;
119 rppg_cmd.init_ctrl.ctrl_id = ctrl_id;
120
121 switch (ctrl_id) {
122 case NV_PMU_RPPG_CTRL_ID_GR:
123 case NV_PMU_RPPG_CTRL_ID_MS:
124 rppg_cmd.init_ctrl.domain_id = NV_PMU_RPPG_DOMAIN_ID_GFX;
125 break;
126 }
127
128 return rppg_send_cmd(g, &rppg_cmd);
129}
130
131u32 init_rppg(struct gk20a *g)
132{
133 u32 status;
134
135 status = rppg_init(g);
136 if (status != 0) {
137 nvgpu_err(g,
138 "Failed to initialize RPPG in PMU: 0x%08x", status);
139 return status;
140 }
141
142
143 status = rppg_ctrl_init(g, NV_PMU_RPPG_CTRL_ID_GR);
144 if (status != 0) {
145 nvgpu_err(g,
146 "Failed to initialize RPPG_CTRL: GR in PMU: 0x%08x",
147 status);
148 return status;
149 }
150
151 status = rppg_ctrl_init(g, NV_PMU_RPPG_CTRL_ID_MS);
152 if (status != 0) {
153 nvgpu_err(g,
154 "Failed to initialize RPPG_CTRL: MS in PMU: 0x%08x",
155 status);
156 return status;
157 }
158
159 return status;
160}