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1/*
2 * drivers/video/tegra/host/gk20a/pmu_gk20a.h
3 *
4 * GK20A PMU (aka. gPMU outside gk20a context)
5 *
6 * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 */
26#ifndef NVGPU_GK20A_PMU_GK20A_H
27#define NVGPU_GK20A_PMU_GK20A_H
28
29#include <nvgpu/flcnif_cmn.h>
30#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
31#include <nvgpu/pmu.h>
32
33struct nvgpu_firmware;
34
35#define ZBC_MASK(i) (~(~(0) << ((i)+1)) & 0xfffe)
36
37bool gk20a_pmu_is_interrupted(struct nvgpu_pmu *pmu);
38void gk20a_pmu_isr(struct gk20a *g);
39
40u32 gk20a_pmu_pg_engines_list(struct gk20a *g);
41u32 gk20a_pmu_pg_feature_list(struct gk20a *g, u32 pg_engine_id);
42
43void gk20a_pmu_save_zbc(struct gk20a *g, u32 entries);
44
45void gk20a_pmu_init_perfmon_counter(struct gk20a *g);
46
47void gk20a_pmu_pg_idle_counter_config(struct gk20a *g, u32 pg_engine_id);
48
49int gk20a_pmu_mutex_acquire(struct nvgpu_pmu *pmu, u32 id, u32 *token);
50int gk20a_pmu_mutex_release(struct nvgpu_pmu *pmu, u32 id, u32 *token);
51
52int gk20a_pmu_queue_head(struct gk20a *g, struct nvgpu_falcon_queue *queue,
53 u32 *head, bool set);
54int gk20a_pmu_queue_tail(struct gk20a *g, struct nvgpu_falcon_queue *queue,
55 u32 *tail, bool set);
56void gk20a_pmu_msgq_tail(struct nvgpu_pmu *pmu, u32 *tail, bool set);
57
58u32 gk20a_pmu_read_idle_counter(struct gk20a *g, u32 counter_id);
59void gk20a_pmu_reset_idle_counter(struct gk20a *g, u32 counter_id);
60
61u32 gk20a_pmu_read_idle_intr_status(struct gk20a *g);
62void gk20a_pmu_clear_idle_intr_status(struct gk20a *g);
63
64void gk20a_write_dmatrfbase(struct gk20a *g, u32 addr);
65bool gk20a_is_pmu_supported(struct gk20a *g);
66
67int pmu_bootstrap(struct nvgpu_pmu *pmu);
68
69void gk20a_pmu_dump_elpg_stats(struct nvgpu_pmu *pmu);
70void gk20a_pmu_dump_falcon_stats(struct nvgpu_pmu *pmu);
71
72void gk20a_pmu_enable_irq(struct nvgpu_pmu *pmu, bool enable);
73void pmu_handle_fecs_boot_acr_msg(struct gk20a *g, struct pmu_msg *msg,
74 void *param, u32 handle, u32 status);
75void gk20a_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id,
76 struct pmu_pg_stats_data *pg_stat_data);
77bool gk20a_pmu_is_engine_in_reset(struct gk20a *g);
78int gk20a_pmu_engine_reset(struct gk20a *g, bool do_reset);
79u32 gk20a_pmu_get_irqdest(struct gk20a *g);
80#endif /*NVGPU_GK20A_PMU_GK20A_H*/