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Diffstat (limited to 'include/gk20a/gr_ctx_gk20a_sim.c')
-rw-r--r--include/gk20a/gr_ctx_gk20a_sim.c356
1 files changed, 356 insertions, 0 deletions
diff --git a/include/gk20a/gr_ctx_gk20a_sim.c b/include/gk20a/gr_ctx_gk20a_sim.c
new file mode 100644
index 0000000..ce65c77
--- /dev/null
+++ b/include/gk20a/gr_ctx_gk20a_sim.c
@@ -0,0 +1,356 @@
1/*
2 * GK20A Graphics Context for Simulation
3 *
4 * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25#include "gk20a.h"
26#include <nvgpu/sim.h>
27#include "gr_ctx_gk20a.h"
28
29#include <nvgpu/log.h>
30
31int gr_gk20a_init_ctx_vars_sim(struct gk20a *g, struct gr_gk20a *gr)
32{
33 int err = -ENOMEM;
34 u32 i, temp;
35
36 nvgpu_log(g, gpu_dbg_fn | gpu_dbg_info,
37 "querying grctx info from chiplib");
38
39 g->gr.ctx_vars.dynamic = true;
40 g->gr.netlist = GR_NETLIST_DYNAMIC;
41
42 if (g->sim->esc_readl == NULL) {
43 nvgpu_err(g, "Invalid pointer to query function.");
44 err = -ENOENT;
45 goto fail;
46 }
47
48 /* query sizes and counts */
49 g->sim->esc_readl(g, "GRCTX_UCODE_INST_FECS_COUNT", 0,
50 &g->gr.ctx_vars.ucode.fecs.inst.count);
51 g->sim->esc_readl(g, "GRCTX_UCODE_DATA_FECS_COUNT", 0,
52 &g->gr.ctx_vars.ucode.fecs.data.count);
53 g->sim->esc_readl(g, "GRCTX_UCODE_INST_GPCCS_COUNT", 0,
54 &g->gr.ctx_vars.ucode.gpccs.inst.count);
55 g->sim->esc_readl(g, "GRCTX_UCODE_DATA_GPCCS_COUNT", 0,
56 &g->gr.ctx_vars.ucode.gpccs.data.count);
57 g->sim->esc_readl(g, "GRCTX_ALL_CTX_TOTAL_WORDS", 0, &temp);
58 g->gr.ctx_vars.buffer_size = temp << 2;
59 g->sim->esc_readl(g, "GRCTX_SW_BUNDLE_INIT_SIZE", 0,
60 &g->gr.ctx_vars.sw_bundle_init.count);
61 g->sim->esc_readl(g, "GRCTX_SW_METHOD_INIT_SIZE", 0,
62 &g->gr.ctx_vars.sw_method_init.count);
63 g->sim->esc_readl(g, "GRCTX_SW_CTX_LOAD_SIZE", 0,
64 &g->gr.ctx_vars.sw_ctx_load.count);
65 g->sim->esc_readl(g, "GRCTX_SW_VEID_BUNDLE_INIT_SIZE", 0,
66 &g->gr.ctx_vars.sw_veid_bundle_init.count);
67 g->sim->esc_readl(g, "GRCTX_SW_BUNDLE64_INIT_SIZE", 0,
68 &g->gr.ctx_vars.sw_bundle64_init.count);
69
70 g->sim->esc_readl(g, "GRCTX_NONCTXSW_REG_SIZE", 0,
71 &g->gr.ctx_vars.sw_non_ctx_load.count);
72 g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_COUNT", 0,
73 &g->gr.ctx_vars.ctxsw_regs.sys.count);
74 g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_COUNT", 0,
75 &g->gr.ctx_vars.ctxsw_regs.gpc.count);
76 g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_COUNT", 0,
77 &g->gr.ctx_vars.ctxsw_regs.tpc.count);
78 g->sim->esc_readl(g, "GRCTX_REG_LIST_ZCULL_GPC_COUNT", 0,
79 &g->gr.ctx_vars.ctxsw_regs.zcull_gpc.count);
80 g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_SYS_COUNT", 0,
81 &g->gr.ctx_vars.ctxsw_regs.pm_sys.count);
82 g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_GPC_COUNT", 0,
83 &g->gr.ctx_vars.ctxsw_regs.pm_gpc.count);
84 g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_TPC_COUNT", 0,
85 &g->gr.ctx_vars.ctxsw_regs.pm_tpc.count);
86 g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_COUNT", 0,
87 &g->gr.ctx_vars.ctxsw_regs.ppc.count);
88 g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_COUNT", 0,
89 &g->gr.ctx_vars.ctxsw_regs.etpc.count);
90 g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_COUNT", 0,
91 &g->gr.ctx_vars.ctxsw_regs.ppc.count);
92
93 if (alloc_u32_list_gk20a(g, &g->gr.ctx_vars.ucode.fecs.inst) == NULL) {
94 goto fail;
95 }
96 if (alloc_u32_list_gk20a(g, &g->gr.ctx_vars.ucode.fecs.data) == NULL) {
97 goto fail;
98 }
99 if (alloc_u32_list_gk20a(g, &g->gr.ctx_vars.ucode.gpccs.inst) == NULL) {
100 goto fail;
101 }
102 if (alloc_u32_list_gk20a(g, &g->gr.ctx_vars.ucode.gpccs.data) == NULL) {
103 goto fail;
104 }
105 if (alloc_av_list_gk20a(g, &g->gr.ctx_vars.sw_bundle_init) == NULL) {
106 goto fail;
107 }
108 if (alloc_av64_list_gk20a(g,
109 &g->gr.ctx_vars.sw_bundle64_init) == NULL) {
110 goto fail;
111 }
112 if (alloc_av_list_gk20a(g, &g->gr.ctx_vars.sw_method_init) == NULL) {
113 goto fail;
114 }
115 if (alloc_aiv_list_gk20a(g, &g->gr.ctx_vars.sw_ctx_load) == NULL) {
116 goto fail;
117 }
118 if (alloc_av_list_gk20a(g, &g->gr.ctx_vars.sw_non_ctx_load) == NULL) {
119 goto fail;
120 }
121 if (alloc_av_list_gk20a(g,
122 &g->gr.ctx_vars.sw_veid_bundle_init) == NULL) {
123 goto fail;
124 }
125 if (alloc_aiv_list_gk20a(g, &g->gr.ctx_vars.ctxsw_regs.sys) == NULL) {
126 goto fail;
127 }
128 if (alloc_aiv_list_gk20a(g, &g->gr.ctx_vars.ctxsw_regs.gpc) == NULL) {
129 goto fail;
130 }
131 if (alloc_aiv_list_gk20a(g, &g->gr.ctx_vars.ctxsw_regs.tpc) == NULL) {
132 goto fail;
133 }
134 if (alloc_aiv_list_gk20a(g,
135 &g->gr.ctx_vars.ctxsw_regs.zcull_gpc) == NULL) {
136 goto fail;
137 }
138 if (alloc_aiv_list_gk20a(g, &g->gr.ctx_vars.ctxsw_regs.ppc) == NULL) {
139 goto fail;
140 }
141 if (alloc_aiv_list_gk20a(g,
142 &g->gr.ctx_vars.ctxsw_regs.pm_sys) == NULL) {
143 goto fail;
144 }
145 if (alloc_aiv_list_gk20a(g,
146 &g->gr.ctx_vars.ctxsw_regs.pm_gpc) == NULL) {
147 goto fail;
148 }
149 if (alloc_aiv_list_gk20a(g,
150 &g->gr.ctx_vars.ctxsw_regs.pm_tpc) == NULL) {
151 goto fail;
152 }
153 if (alloc_aiv_list_gk20a(g, &g->gr.ctx_vars.ctxsw_regs.etpc) == NULL) {
154 goto fail;
155 }
156
157 for (i = 0; i < g->gr.ctx_vars.ucode.fecs.inst.count; i++) {
158 g->sim->esc_readl(g, "GRCTX_UCODE_INST_FECS",
159 i, &g->gr.ctx_vars.ucode.fecs.inst.l[i]);
160 }
161
162 for (i = 0; i < g->gr.ctx_vars.ucode.fecs.data.count; i++) {
163 g->sim->esc_readl(g, "GRCTX_UCODE_DATA_FECS",
164 i, &g->gr.ctx_vars.ucode.fecs.data.l[i]);
165 }
166
167 for (i = 0; i < g->gr.ctx_vars.ucode.gpccs.inst.count; i++) {
168 g->sim->esc_readl(g, "GRCTX_UCODE_INST_GPCCS",
169 i, &g->gr.ctx_vars.ucode.gpccs.inst.l[i]);
170 }
171
172 for (i = 0; i < g->gr.ctx_vars.ucode.gpccs.data.count; i++) {
173 g->sim->esc_readl(g, "GRCTX_UCODE_DATA_GPCCS",
174 i, &g->gr.ctx_vars.ucode.gpccs.data.l[i]);
175 }
176
177 for (i = 0; i < g->gr.ctx_vars.sw_bundle_init.count; i++) {
178 struct av_gk20a *l = g->gr.ctx_vars.sw_bundle_init.l;
179 g->sim->esc_readl(g, "GRCTX_SW_BUNDLE_INIT:ADDR",
180 i, &l[i].addr);
181 g->sim->esc_readl(g, "GRCTX_SW_BUNDLE_INIT:VALUE",
182 i, &l[i].value);
183 }
184
185 for (i = 0; i < g->gr.ctx_vars.sw_method_init.count; i++) {
186 struct av_gk20a *l = g->gr.ctx_vars.sw_method_init.l;
187 g->sim->esc_readl(g, "GRCTX_SW_METHOD_INIT:ADDR",
188 i, &l[i].addr);
189 g->sim->esc_readl(g, "GRCTX_SW_METHOD_INIT:VALUE",
190 i, &l[i].value);
191 }
192
193 for (i = 0; i < g->gr.ctx_vars.sw_ctx_load.count; i++) {
194 struct aiv_gk20a *l = g->gr.ctx_vars.sw_ctx_load.l;
195 g->sim->esc_readl(g, "GRCTX_SW_CTX_LOAD:ADDR",
196 i, &l[i].addr);
197 g->sim->esc_readl(g, "GRCTX_SW_CTX_LOAD:INDEX",
198 i, &l[i].index);
199 g->sim->esc_readl(g, "GRCTX_SW_CTX_LOAD:VALUE",
200 i, &l[i].value);
201 }
202
203 for (i = 0; i < g->gr.ctx_vars.sw_non_ctx_load.count; i++) {
204 struct av_gk20a *l = g->gr.ctx_vars.sw_non_ctx_load.l;
205 g->sim->esc_readl(g, "GRCTX_NONCTXSW_REG:REG",
206 i, &l[i].addr);
207 g->sim->esc_readl(g, "GRCTX_NONCTXSW_REG:VALUE",
208 i, &l[i].value);
209 }
210
211 for (i = 0; i < g->gr.ctx_vars.sw_veid_bundle_init.count; i++) {
212 struct av_gk20a *l = g->gr.ctx_vars.sw_veid_bundle_init.l;
213
214 g->sim->esc_readl(g, "GRCTX_SW_VEID_BUNDLE_INIT:ADDR",
215 i, &l[i].addr);
216 g->sim->esc_readl(g, "GRCTX_SW_VEID_BUNDLE_INIT:VALUE",
217 i, &l[i].value);
218 }
219
220 for (i = 0; i < g->gr.ctx_vars.sw_bundle64_init.count; i++) {
221 struct av64_gk20a *l = g->gr.ctx_vars.sw_bundle64_init.l;
222
223 g->sim->esc_readl(g, "GRCTX_SW_BUNDLE64_INIT:ADDR",
224 i, &l[i].addr);
225 g->sim->esc_readl(g, "GRCTX_SW_BUNDLE64_INIT:VALUE_LO",
226 i, &l[i].value_lo);
227 g->sim->esc_readl(g, "GRCTX_SW_BUNDLE64_INIT:VALUE_HI",
228 i, &l[i].value_hi);
229 }
230
231 for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.sys.count; i++) {
232 struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.sys.l;
233 g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS:ADDR",
234 i, &l[i].addr);
235 g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS:INDEX",
236 i, &l[i].index);
237 g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS:VALUE",
238 i, &l[i].value);
239 }
240
241 for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.gpc.count; i++) {
242 struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.gpc.l;
243 g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC:ADDR",
244 i, &l[i].addr);
245 g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC:INDEX",
246 i, &l[i].index);
247 g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC:VALUE",
248 i, &l[i].value);
249 }
250
251 for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.tpc.count; i++) {
252 struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.tpc.l;
253 g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC:ADDR",
254 i, &l[i].addr);
255 g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC:INDEX",
256 i, &l[i].index);
257 g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC:VALUE",
258 i, &l[i].value);
259 }
260
261 for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.ppc.count; i++) {
262 struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.ppc.l;
263 g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC:ADDR",
264 i, &l[i].addr);
265 g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC:INDEX",
266 i, &l[i].index);
267 g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC:VALUE",
268 i, &l[i].value);
269 }
270
271 for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.zcull_gpc.count; i++) {
272 struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.zcull_gpc.l;
273 g->sim->esc_readl(g, "GRCTX_REG_LIST_ZCULL_GPC:ADDR",
274 i, &l[i].addr);
275 g->sim->esc_readl(g, "GRCTX_REG_LIST_ZCULL_GPC:INDEX",
276 i, &l[i].index);
277 g->sim->esc_readl(g, "GRCTX_REG_LIST_ZCULL_GPC:VALUE",
278 i, &l[i].value);
279 }
280
281 for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.pm_sys.count; i++) {
282 struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.pm_sys.l;
283 g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_SYS:ADDR",
284 i, &l[i].addr);
285 g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_SYS:INDEX",
286 i, &l[i].index);
287 g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_SYS:VALUE",
288 i, &l[i].value);
289 }
290
291 for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.pm_gpc.count; i++) {
292 struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.pm_gpc.l;
293 g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_GPC:ADDR",
294 i, &l[i].addr);
295 g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_GPC:INDEX",
296 i, &l[i].index);
297 g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_GPC:VALUE",
298 i, &l[i].value);
299 }
300
301 for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.pm_tpc.count; i++) {
302 struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.pm_tpc.l;
303 g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_TPC:ADDR",
304 i, &l[i].addr);
305 g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_TPC:INDEX",
306 i, &l[i].index);
307 g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_TPC:VALUE",
308 i, &l[i].value);
309 }
310
311 nvgpu_log(g, gpu_dbg_info | gpu_dbg_fn, "query GRCTX_REG_LIST_ETPC");
312 for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.etpc.count; i++) {
313 struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.etpc.l;
314 g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC:ADDR",
315 i, &l[i].addr);
316 g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC:INDEX",
317 i, &l[i].index);
318 g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC:VALUE",
319 i, &l[i].value);
320 nvgpu_log(g, gpu_dbg_info | gpu_dbg_fn,
321 "addr:0x%#08x index:0x%08x value:0x%08x",
322 l[i].addr, l[i].index, l[i].value);
323 }
324
325 g->gr.ctx_vars.valid = true;
326
327 g->sim->esc_readl(g, "GRCTX_GEN_CTX_REGS_BASE_INDEX", 0,
328 &g->gr.ctx_vars.regs_base_index);
329
330 nvgpu_log(g, gpu_dbg_info | gpu_dbg_fn, "finished querying grctx info from chiplib");
331 return 0;
332fail:
333 nvgpu_err(g, "failed querying grctx info from chiplib");
334
335 nvgpu_kfree(g, g->gr.ctx_vars.ucode.fecs.inst.l);
336 nvgpu_kfree(g, g->gr.ctx_vars.ucode.fecs.data.l);
337 nvgpu_kfree(g, g->gr.ctx_vars.ucode.gpccs.inst.l);
338 nvgpu_kfree(g, g->gr.ctx_vars.ucode.gpccs.data.l);
339 nvgpu_kfree(g, g->gr.ctx_vars.sw_bundle_init.l);
340 nvgpu_kfree(g, g->gr.ctx_vars.sw_bundle64_init.l);
341 nvgpu_kfree(g, g->gr.ctx_vars.sw_method_init.l);
342 nvgpu_kfree(g, g->gr.ctx_vars.sw_ctx_load.l);
343 nvgpu_kfree(g, g->gr.ctx_vars.sw_non_ctx_load.l);
344 nvgpu_kfree(g, g->gr.ctx_vars.sw_veid_bundle_init.l);
345 nvgpu_kfree(g, g->gr.ctx_vars.ctxsw_regs.sys.l);
346 nvgpu_kfree(g, g->gr.ctx_vars.ctxsw_regs.gpc.l);
347 nvgpu_kfree(g, g->gr.ctx_vars.ctxsw_regs.tpc.l);
348 nvgpu_kfree(g, g->gr.ctx_vars.ctxsw_regs.zcull_gpc.l);
349 nvgpu_kfree(g, g->gr.ctx_vars.ctxsw_regs.ppc.l);
350 nvgpu_kfree(g, g->gr.ctx_vars.ctxsw_regs.pm_sys.l);
351 nvgpu_kfree(g, g->gr.ctx_vars.ctxsw_regs.pm_gpc.l);
352 nvgpu_kfree(g, g->gr.ctx_vars.ctxsw_regs.pm_tpc.l);
353 nvgpu_kfree(g, g->gr.ctx_vars.ctxsw_regs.etpc.l);
354
355 return err;
356}
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-30 06:18:45 -0400