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1/*
2 * Tegra GK20A GPU Debugger Driver
3 *
4 * Copyright (c) 2013-2018, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24#ifndef DBG_GPU_H
25#define DBG_GPU_H
26
27#include <nvgpu/cond.h>
28#include <nvgpu/lock.h>
29#include <nvgpu/list.h>
30
31struct gk20a;
32struct channel_gk20a;
33struct dbg_session_gk20a;
34
35/* used by the interrupt handler to post events */
36void gk20a_dbg_gpu_post_events(struct channel_gk20a *fault_ch);
37
38struct channel_gk20a *
39nvgpu_dbg_gpu_get_session_channel(struct dbg_session_gk20a *dbg_s);
40
41struct dbg_gpu_session_events {
42 struct nvgpu_cond wait_queue;
43 bool events_enabled;
44 int num_pending_events;
45};
46
47struct dbg_session_gk20a {
48 /* dbg session id used for trace/prints */
49 int id;
50
51 /* profiler session, if any */
52 bool is_profiler;
53
54 /* has a valid profiler reservation */
55 bool has_profiler_reservation;
56
57 /* power enabled or disabled */
58 bool is_pg_disabled;
59
60 /* timeouts enabled or disabled */
61 bool is_timeout_disabled;
62
63 struct gk20a *g;
64
65 /* list of bound channels, if any */
66 struct nvgpu_list_node ch_list;
67 struct nvgpu_mutex ch_list_lock;
68
69 /* event support */
70 struct dbg_gpu_session_events dbg_events;
71
72 bool broadcast_stop_trigger;
73
74 struct nvgpu_mutex ioctl_lock;
75};
76
77struct dbg_session_data {
78 struct dbg_session_gk20a *dbg_s;
79 struct nvgpu_list_node dbg_s_entry;
80};
81
82static inline struct dbg_session_data *
83dbg_session_data_from_dbg_s_entry(struct nvgpu_list_node *node)
84{
85 return (struct dbg_session_data *)
86 ((uintptr_t)node - offsetof(struct dbg_session_data, dbg_s_entry));
87};
88
89struct dbg_session_channel_data {
90 int channel_fd;
91 u32 chid;
92 struct nvgpu_list_node ch_entry;
93 struct dbg_session_data *session_data;
94 int (*unbind_single_channel)(struct dbg_session_gk20a *dbg_s,
95 struct dbg_session_channel_data *ch_data);
96};
97
98static inline struct dbg_session_channel_data *
99dbg_session_channel_data_from_ch_entry(struct nvgpu_list_node *node)
100{
101 return (struct dbg_session_channel_data *)
102 ((uintptr_t)node - offsetof(struct dbg_session_channel_data, ch_entry));
103};
104
105struct dbg_profiler_object_data {
106 int session_id;
107 u32 prof_handle;
108 struct channel_gk20a *ch;
109 bool has_reservation;
110 struct nvgpu_list_node prof_obj_entry;
111};
112
113static inline struct dbg_profiler_object_data *
114dbg_profiler_object_data_from_prof_obj_entry(struct nvgpu_list_node *node)
115{
116 return (struct dbg_profiler_object_data *)
117 ((uintptr_t)node - offsetof(struct dbg_profiler_object_data, prof_obj_entry));
118};
119
120bool gk20a_dbg_gpu_broadcast_stop_trigger(struct channel_gk20a *ch);
121int gk20a_dbg_gpu_clear_broadcast_stop_trigger(struct channel_gk20a *ch);
122
123int dbg_set_powergate(struct dbg_session_gk20a *dbg_s, bool disable_powergate);
124bool nvgpu_check_and_set_global_reservation(
125 struct dbg_session_gk20a *dbg_s,
126 struct dbg_profiler_object_data *prof_obj);
127bool nvgpu_check_and_set_context_reservation(
128 struct dbg_session_gk20a *dbg_s,
129 struct dbg_profiler_object_data *prof_obj);
130void nvgpu_release_profiler_reservation(struct dbg_session_gk20a *dbg_s,
131 struct dbg_profiler_object_data *prof_obj);
132int gk20a_perfbuf_enable_locked(struct gk20a *g, u64 offset, u32 size);
133int gk20a_perfbuf_disable_locked(struct gk20a *g);
134
135void nvgpu_dbg_session_post_event(struct dbg_session_gk20a *dbg_s);
136u32 nvgpu_set_powergate_locked(struct dbg_session_gk20a *dbg_s,
137 bool mode);
138
139 /* PM Context Switch Mode */
140/*This mode says that the pms are not to be context switched. */
141#define NVGPU_DBG_HWPM_CTXSW_MODE_NO_CTXSW (0x00000000)
142/* This mode says that the pms in Mode-B are to be context switched */
143#define NVGPU_DBG_HWPM_CTXSW_MODE_CTXSW (0x00000001)
144/* This mode says that the pms in Mode-E (stream out) are to be context switched. */
145#define NVGPU_DBG_HWPM_CTXSW_MODE_STREAM_OUT_CTXSW (0x00000002)
146
147#endif /* DBG_GPU_GK20A_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-30 06:19:47 -0400