diff options
Diffstat (limited to 'include/ctrl/ctrlpmgr.h')
-rw-r--r-- | include/ctrl/ctrlpmgr.h | 98 |
1 files changed, 98 insertions, 0 deletions
diff --git a/include/ctrl/ctrlpmgr.h b/include/ctrl/ctrlpmgr.h new file mode 100644 index 0000000..90f6501 --- /dev/null +++ b/include/ctrl/ctrlpmgr.h | |||
@@ -0,0 +1,98 @@ | |||
1 | /* | ||
2 | * Control pmgr state infrastructure | ||
3 | * | ||
4 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | #ifndef NVGPU_CTRLPMGR_H | ||
25 | #define NVGPU_CTRLPMGR_H | ||
26 | |||
27 | #include "ctrlboardobj.h" | ||
28 | |||
29 | /* valid power domain values */ | ||
30 | #define CTRL_PMGR_PWR_DEVICES_MAX_DEVICES 32U | ||
31 | #define CTRL_PMGR_PWR_VIOLATION_MAX 0x06U | ||
32 | |||
33 | #define CTRL_PMGR_PWR_DEVICE_TYPE_INA3221 0x4EU | ||
34 | |||
35 | #define CTRL_PMGR_PWR_CHANNEL_INDEX_INVALID 0xFFU | ||
36 | #define CTRL_PMGR_PWR_CHANNEL_TYPE_SENSOR 0x08U | ||
37 | |||
38 | #define CTRL_PMGR_PWR_POLICY_TABLE_VERSION_3X 0x30U | ||
39 | #define CTRL_PMGR_PWR_POLICY_TYPE_HW_THRESHOLD 0x04U | ||
40 | #define CTRL_PMGR_PWR_POLICY_TYPE_SW_THRESHOLD 0x0CU | ||
41 | |||
42 | #define CTRL_PMGR_PWR_POLICY_MAX_LIMIT_INPUTS 0x8U | ||
43 | #define CTRL_PMGR_PWR_POLICY_IDX_NUM_INDEXES 0x08U | ||
44 | #define CTRL_PMGR_PWR_POLICY_INDEX_INVALID 0xFFU | ||
45 | #define CTRL_PMGR_PWR_POLICY_LIMIT_INPUT_CLIENT_IDX_RM 0xFEU | ||
46 | #define CTRL_PMGR_PWR_POLICY_LIMIT_MAX (0xFFFFFFFFU) | ||
47 | |||
48 | struct ctrl_pmgr_pwr_device_info_rshunt { | ||
49 | bool use_fxp8_8; | ||
50 | u16 rshunt_value; | ||
51 | }; | ||
52 | |||
53 | struct ctrl_pmgr_pwr_policy_info_integral { | ||
54 | u8 past_sample_count; | ||
55 | u8 next_sample_count; | ||
56 | u16 ratio_limit_min; | ||
57 | u16 ratio_limit_max; | ||
58 | }; | ||
59 | |||
60 | enum ctrl_pmgr_pwr_policy_filter_type { | ||
61 | CTRL_PMGR_PWR_POLICY_FILTER_TYPE_NONE = 0, | ||
62 | CTRL_PMGR_PWR_POLICY_FILTER_TYPE_BLOCK, | ||
63 | CTRL_PMGR_PWR_POLICY_FILTER_TYPE_MOVING_AVERAGE, | ||
64 | CTRL_PMGR_PWR_POLICY_FILTER_TYPE_IIR | ||
65 | }; | ||
66 | |||
67 | struct ctrl_pmgr_pwr_policy_filter_param_block { | ||
68 | u32 block_size; | ||
69 | }; | ||
70 | |||
71 | struct ctrl_pmgr_pwr_policy_filter_param_moving_average { | ||
72 | u32 window_size; | ||
73 | }; | ||
74 | |||
75 | struct ctrl_pmgr_pwr_policy_filter_param_iir { | ||
76 | u32 divisor; | ||
77 | }; | ||
78 | |||
79 | union ctrl_pmgr_pwr_policy_filter_param { | ||
80 | struct ctrl_pmgr_pwr_policy_filter_param_block block; | ||
81 | struct ctrl_pmgr_pwr_policy_filter_param_moving_average moving_avg; | ||
82 | struct ctrl_pmgr_pwr_policy_filter_param_iir iir; | ||
83 | }; | ||
84 | |||
85 | struct ctrl_pmgr_pwr_policy_limit_input { | ||
86 | u8 pwr_policy_idx; | ||
87 | u32 limit_value; | ||
88 | }; | ||
89 | |||
90 | struct ctrl_pmgr_pwr_policy_limit_arbitration { | ||
91 | bool b_arb_max; | ||
92 | u8 num_inputs; | ||
93 | u32 output; | ||
94 | struct ctrl_pmgr_pwr_policy_limit_input | ||
95 | inputs[CTRL_PMGR_PWR_POLICY_MAX_LIMIT_INPUTS]; | ||
96 | }; | ||
97 | |||
98 | #endif /* NVGPU_CTRLPMGR_H */ | ||