diff options
Diffstat (limited to 'include/ctrl/ctrlperf.h')
-rw-r--r-- | include/ctrl/ctrlperf.h | 103 |
1 files changed, 103 insertions, 0 deletions
diff --git a/include/ctrl/ctrlperf.h b/include/ctrl/ctrlperf.h new file mode 100644 index 0000000..2928cad --- /dev/null +++ b/include/ctrl/ctrlperf.h | |||
@@ -0,0 +1,103 @@ | |||
1 | /* | ||
2 | * general p state infrastructure | ||
3 | * | ||
4 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | #ifndef NVGPU_CTRLPERF_H | ||
25 | #define NVGPU_CTRLPERF_H | ||
26 | |||
27 | struct ctrl_perf_volt_rail_list_item { | ||
28 | u8 volt_domain; | ||
29 | u32 voltage_uv; | ||
30 | u32 voltage_min_noise_unaware_uv; | ||
31 | }; | ||
32 | |||
33 | struct ctrl_perf_volt_rail_list { | ||
34 | u8 num_rails; | ||
35 | struct ctrl_perf_volt_rail_list_item | ||
36 | rails[CTRL_VOLT_VOLT_RAIL_MAX_RAILS]; | ||
37 | }; | ||
38 | |||
39 | union ctrl_perf_vfe_var_single_sensed_fuse_value_data { | ||
40 | int signed_value; | ||
41 | u32 unsigned_value; | ||
42 | }; | ||
43 | |||
44 | struct ctrl_perf_vfe_var_single_sensed_fuse_value { | ||
45 | bool b_signed; | ||
46 | union ctrl_perf_vfe_var_single_sensed_fuse_value_data data; | ||
47 | }; | ||
48 | |||
49 | struct ctrl_bios_vfield_register_segment_super { | ||
50 | u8 low_bit; | ||
51 | u8 high_bit; | ||
52 | }; | ||
53 | |||
54 | struct ctrl_bios_vfield_register_segment_reg { | ||
55 | struct ctrl_bios_vfield_register_segment_super super; | ||
56 | u32 addr; | ||
57 | }; | ||
58 | |||
59 | struct ctrl_bios_vfield_register_segment_index_reg { | ||
60 | struct ctrl_bios_vfield_register_segment_super super; | ||
61 | u32 addr; | ||
62 | u32 reg_index; | ||
63 | u32 index; | ||
64 | }; | ||
65 | |||
66 | union ctrl_bios_vfield_register_segment_data { | ||
67 | struct ctrl_bios_vfield_register_segment_reg reg; | ||
68 | struct ctrl_bios_vfield_register_segment_index_reg index_reg; | ||
69 | }; | ||
70 | |||
71 | struct ctrl_bios_vfield_register_segment { | ||
72 | u8 type; | ||
73 | union ctrl_bios_vfield_register_segment_data data; | ||
74 | }; | ||
75 | |||
76 | #define NV_PMU_VFE_VAR_SINGLE_SENSED_FUSE_SEGMENTS_MAX 1 | ||
77 | |||
78 | struct ctrl_perf_vfe_var_single_sensed_fuse_info { | ||
79 | u8 segment_count; | ||
80 | struct ctrl_bios_vfield_register_segment segments[NV_PMU_VFE_VAR_SINGLE_SENSED_FUSE_SEGMENTS_MAX]; | ||
81 | }; | ||
82 | |||
83 | struct ctrl_perf_vfe_var_single_sensed_fuse_override_info { | ||
84 | u32 fuse_val_override; | ||
85 | u8 b_fuse_regkey_override; | ||
86 | }; | ||
87 | |||
88 | struct ctrl_perf_vfe_var_single_sensed_fuse_vfield_info { | ||
89 | struct ctrl_perf_vfe_var_single_sensed_fuse_info fuse; | ||
90 | u32 fuse_val_default; | ||
91 | u32 hw_correction_scale; | ||
92 | int hw_correction_offset; | ||
93 | u8 v_field_id; | ||
94 | }; | ||
95 | |||
96 | struct ctrl_perf_vfe_var_single_sensed_fuse_ver_vfield_info { | ||
97 | struct ctrl_perf_vfe_var_single_sensed_fuse_info fuse; | ||
98 | u8 ver_expected; | ||
99 | bool b_ver_check; | ||
100 | bool b_use_default_on_ver_check_fail; | ||
101 | u8 v_field_id_ver; | ||
102 | }; | ||
103 | #endif /* NVGPU_CTRLPERF_H */ | ||