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Diffstat (limited to 'include/ctrl/ctrlclkavfs.h')
-rw-r--r-- | include/ctrl/ctrlclkavfs.h | 112 |
1 files changed, 112 insertions, 0 deletions
diff --git a/include/ctrl/ctrlclkavfs.h b/include/ctrl/ctrlclkavfs.h new file mode 100644 index 0000000..676ae7e --- /dev/null +++ b/include/ctrl/ctrlclkavfs.h | |||
@@ -0,0 +1,112 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #ifndef NVGPU_CTRLCLKAVFS_H | ||
24 | #define NVGPU_CTRLCLKAVFS_H | ||
25 | |||
26 | #include "ctrlboardobj.h" | ||
27 | /*! | ||
28 | * Valid global VIN ID values | ||
29 | */ | ||
30 | #define CTRL_CLK_VIN_ID_SYS 0x00000000 | ||
31 | #define CTRL_CLK_VIN_ID_LTC 0x00000001 | ||
32 | #define CTRL_CLK_VIN_ID_XBAR 0x00000002 | ||
33 | #define CTRL_CLK_VIN_ID_GPC0 0x00000003 | ||
34 | #define CTRL_CLK_VIN_ID_GPC1 0x00000004 | ||
35 | #define CTRL_CLK_VIN_ID_GPC2 0x00000005 | ||
36 | #define CTRL_CLK_VIN_ID_GPC3 0x00000006 | ||
37 | #define CTRL_CLK_VIN_ID_GPC4 0x00000007 | ||
38 | #define CTRL_CLK_VIN_ID_GPC5 0x00000008 | ||
39 | #define CTRL_CLK_VIN_ID_GPCS 0x00000009 | ||
40 | #define CTRL_CLK_VIN_ID_SRAM 0x0000000A | ||
41 | #define CTRL_CLK_VIN_ID_UNDEFINED 0x000000FF | ||
42 | |||
43 | #define CTRL_CLK_VIN_TYPE_DISABLED 0x00000000 | ||
44 | #define CTRL_CLK_VIN_TYPE_V10 0x00000001 | ||
45 | #define CTRL_CLK_VIN_TYPE_V20 0x00000002 | ||
46 | |||
47 | /*! | ||
48 | * Various types of VIN calibration that the GPU can support | ||
49 | */ | ||
50 | #define CTRL_CLK_VIN_CAL_TYPE_V10 (0x00000000) | ||
51 | #define CTRL_CLK_VIN_CAL_TYPE_V20 (0x00000001) | ||
52 | |||
53 | /*! | ||
54 | * Mask of all GPC VIN IDs supported by RM | ||
55 | */ | ||
56 | #define CTRL_CLK_VIN_MASK_UNICAST_GPC (BIT(CTRL_CLK_VIN_ID_GPC0) | \ | ||
57 | BIT(CTRL_CLK_VIN_ID_GPC1) | \ | ||
58 | BIT(CTRL_CLK_VIN_ID_GPC2) | \ | ||
59 | BIT(CTRL_CLK_VIN_ID_GPC3) | \ | ||
60 | BIT(CTRL_CLK_VIN_ID_GPC4) | \ | ||
61 | BIT(CTRL_CLK_VIN_ID_GPC5)) | ||
62 | #define CTRL_CLK_LUT_NUM_ENTRIES_MAX (128) | ||
63 | #define CTRL_CLK_LUT_NUM_ENTRIES_GV10x (128) | ||
64 | #define CTRL_CLK_LUT_NUM_ENTRIES_GP10x (100) | ||
65 | #define CTRL_CLK_VIN_STEP_SIZE_UV (10000) | ||
66 | #define CTRL_CLK_LUT_MIN_VOLTAGE_UV (450000) | ||
67 | #define CTRL_CLK_FLL_TYPE_DISABLED 0 | ||
68 | |||
69 | #define CTRL_CLK_FLL_ID_SYS (0x00000000) | ||
70 | #define CTRL_CLK_FLL_ID_LTC (0x00000001) | ||
71 | #define CTRL_CLK_FLL_ID_XBAR (0x00000002) | ||
72 | #define CTRL_CLK_FLL_ID_GPC0 (0x00000003) | ||
73 | #define CTRL_CLK_FLL_ID_GPC1 (0x00000004) | ||
74 | #define CTRL_CLK_FLL_ID_GPC2 (0x00000005) | ||
75 | #define CTRL_CLK_FLL_ID_GPC3 (0x00000006) | ||
76 | #define CTRL_CLK_FLL_ID_GPC4 (0x00000007) | ||
77 | #define CTRL_CLK_FLL_ID_GPC5 (0x00000008) | ||
78 | #define CTRL_CLK_FLL_ID_GPCS (0x00000009) | ||
79 | #define CTRL_CLK_FLL_ID_UNDEFINED (0x000000FF) | ||
80 | #define CTRL_CLK_FLL_MASK_UNDEFINED (0x00000000) | ||
81 | |||
82 | /*! | ||
83 | * Mask of all GPC FLL IDs supported by RM | ||
84 | */ | ||
85 | #define CTRL_CLK_FLL_MASK_UNICAST_GPC (BIT(CTRL_CLK_FLL_ID_GPC0) | \ | ||
86 | BIT(CTRL_CLK_FLL_ID_GPC1) | \ | ||
87 | BIT(CTRL_CLK_FLL_ID_GPC2) | \ | ||
88 | BIT(CTRL_CLK_FLL_ID_GPC3) | \ | ||
89 | BIT(CTRL_CLK_FLL_ID_GPC4) | \ | ||
90 | BIT(CTRL_CLK_FLL_ID_GPC5)) | ||
91 | /*! | ||
92 | * Mask of all FLL IDs supported by Nvgpu driver | ||
93 | */ | ||
94 | #define CTRL_CLK_FLL_ID_ALL_MASK (BIT(CTRL_CLK_FLL_ID_SYS) | \ | ||
95 | BIT(CTRL_CLK_FLL_ID_LTC) | \ | ||
96 | BIT(CTRL_CLK_FLL_ID_XBAR) | \ | ||
97 | BIT(CTRL_CLK_FLL_ID_GPC0) | \ | ||
98 | BIT(CTRL_CLK_FLL_ID_GPC1) | \ | ||
99 | BIT(CTRL_CLK_FLL_ID_GPC2) | \ | ||
100 | BIT(CTRL_CLK_FLL_ID_GPC3) | \ | ||
101 | BIT(CTRL_CLK_FLL_ID_GPC4) | \ | ||
102 | BIT(CTRL_CLK_FLL_ID_GPC5) | \ | ||
103 | BIT(CTRL_CLK_FLL_ID_GPCS)) | ||
104 | |||
105 | #define CTRL_CLK_FLL_REGIME_ID_INVALID (0x00000000) | ||
106 | #define CTRL_CLK_FLL_REGIME_ID_FFR (0x00000001) | ||
107 | #define CTRL_CLK_FLL_REGIME_ID_FR (0x00000002) | ||
108 | |||
109 | #define CTRL_CLK_FLL_LUT_VSELECT_LOGIC (0x00000000) | ||
110 | #define CTRL_CLK_FLL_LUT_VSELECT_MIN (0x00000001) | ||
111 | #define CTRL_CLK_FLL_LUT_VSELECT_SRAM (0x00000002) | ||
112 | #endif /* NVGPU_CTRLCLKAVFS_H */ | ||