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-rw-r--r--include/ctrl/ctrlclk.h212
1 files changed, 0 insertions, 212 deletions
diff --git a/include/ctrl/ctrlclk.h b/include/ctrl/ctrlclk.h
deleted file mode 100644
index fbd5677..0000000
--- a/include/ctrl/ctrlclk.h
+++ /dev/null
@@ -1,212 +0,0 @@
1/*
2 * general p state infrastructure
3 *
4 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24#ifndef NVGPU_CTRLCLK_H
25#define NVGPU_CTRLCLK_H
26
27#include "ctrlboardobj.h"
28#include "ctrlclkavfs.h"
29#include "ctrlvolt.h"
30
31#define CTRL_CLK_CLK_DELTA_MAX_VOLT_RAILS 4
32
33/* valid clock domain values */
34#define CTRL_CLK_DOMAIN_MCLK (0x00000010)
35#define CTRL_CLK_DOMAIN_HOSTCLK (0x00000020)
36#define CTRL_CLK_DOMAIN_DISPCLK (0x00000040)
37#define CTRL_CLK_DOMAIN_GPC2CLK (0x00010000)
38#define CTRL_CLK_DOMAIN_XBAR2CLK (0x00040000)
39#define CTRL_CLK_DOMAIN_SYS2CLK (0x00800000)
40#define CTRL_CLK_DOMAIN_HUB2CLK (0x01000000)
41#define CTRL_CLK_DOMAIN_PWRCLK (0x00080000)
42#define CTRL_CLK_DOMAIN_NVDCLK (0x00100000)
43#define CTRL_CLK_DOMAIN_PCIEGENCLK (0x00200000)
44
45#define CTRL_CLK_DOMAIN_GPCCLK (0x00000001)
46#define CTRL_CLK_DOMAIN_XBARCLK (0x00000002)
47#define CTRL_CLK_DOMAIN_SYSCLK (0x00000004)
48#define CTRL_CLK_DOMAIN_HUBCLK (0x00000008)
49
50#define CTRL_CLK_CLK_DOMAIN_TYPE_3X 0x01
51#define CTRL_CLK_CLK_DOMAIN_TYPE_3X_FIXED 0x02
52#define CTRL_CLK_CLK_DOMAIN_TYPE_3X_PROG 0x03
53#define CTRL_CLK_CLK_DOMAIN_TYPE_3X_MASTER 0x04
54#define CTRL_CLK_CLK_DOMAIN_TYPE_3X_SLAVE 0x05
55#define CTRL_CLK_CLK_DOMAIN_TYPE_30_PROG 0x06
56#define CTRL_CLK_CLK_DOMAIN_TYPE_35_MASTER 0x07
57#define CTRL_CLK_CLK_DOMAIN_TYPE_35_SLAVE 0x08
58#define CTRL_CLK_CLK_DOMAIN_TYPE_35_PROG 0x09
59
60#define CTRL_CLK_CLK_DOMAIN_3X_PROG_ORDERING_INDEX_INVALID 0xFF
61#define CTRL_CLK_CLK_DOMAIN_INDEX_INVALID 0xFF
62
63#define CTRL_CLK_CLK_PROG_TYPE_1X 0x01
64#define CTRL_CLK_CLK_PROG_TYPE_1X_MASTER 0x02
65#define CTRL_CLK_CLK_PROG_TYPE_1X_MASTER_RATIO 0x03
66#define CTRL_CLK_CLK_PROG_TYPE_1X_MASTER_TABLE 0x04
67#define CTRL_CLK_CLK_PROG_TYPE_UNKNOWN 255
68
69/*!
70 * Enumeration of CLK_PROG source types.
71 */
72#define CTRL_CLK_PROG_1X_SOURCE_PLL 0x00
73#define CTRL_CLK_PROG_1X_SOURCE_ONE_SOURCE 0x01
74#define CTRL_CLK_PROG_1X_SOURCE_FLL 0x02
75#define CTRL_CLK_PROG_1X_SOURCE_INVALID 255
76
77#define CTRL_CLK_CLK_PROG_1X_MASTER_VF_ENTRY_MAX_ENTRIES 4
78#define CTRL_CLK_PROG_1X_MASTER_MAX_SLAVE_ENTRIES 6
79
80#define CTRL_CLK_CLK_VF_POINT_IDX_INVALID 255
81
82#define CTRL_CLK_CLK_VF_POINT_TYPE_FREQ 0x01
83#define CTRL_CLK_CLK_VF_POINT_TYPE_VOLT 0x02
84#define CTRL_CLK_CLK_VF_POINT_TYPE_UNKNOWN 255
85
86struct ctrl_clk_clk_prog_1x_master_source_fll {
87 u32 base_vfsmooth_volt_uv;
88 u32 max_vf_ramprate;
89 u32 max_freq_stepsize_mhz;
90};
91
92union ctrl_clk_clk_prog_1x_master_source_data {
93 struct ctrl_clk_clk_prog_1x_master_source_fll fll;
94};
95
96struct ctrl_clk_clk_vf_point_info_freq {
97 u16 freq_mhz;
98};
99
100struct ctrl_clk_clk_vf_point_info_volt {
101 u32 sourceVoltageuV;
102 u8 vfGainVfeEquIdx;
103 u8 clkDomainIdx;
104};
105
106struct ctrl_clk_clk_prog_1x_master_vf_entry {
107 u8 vfe_idx;
108 u8 gain_vfe_idx;
109 u8 vf_point_idx_first;
110 u8 vf_point_idx_last;
111};
112
113struct ctrl_clk_clk_prog_1x_master_ratio_slave_entry {
114 u8 clk_dom_idx;
115 u8 ratio;
116};
117
118struct ctrl_clk_clk_prog_1x_master_table_slave_entry {
119 u8 clk_dom_idx;
120 u16 freq_mhz;
121};
122
123struct ctrl_clk_clk_prog_1x_source_pll {
124 u8 pll_idx;
125 u8 freq_step_size_mhz;
126};
127
128union ctrl_clk_freq_delta_data {
129 s32 delta_khz;
130 s16 delta_percent;
131};
132struct ctrl_clk_freq_delta {
133 u8 type;
134 union ctrl_clk_freq_delta_data data;
135};
136
137struct ctrl_clk_clk_delta {
138 struct ctrl_clk_freq_delta freq_delta;
139 int volt_deltauv[CTRL_CLK_CLK_DELTA_MAX_VOLT_RAILS];
140};
141
142struct ctrl_clk_vin_v10 {
143 u32 slope;
144 u32 intercept;
145};
146
147struct ctrl_clk_vin_v20 {
148 s8 offset;
149 s8 gain;
150};
151
152union ctrl_clk_vin_data_v20 {
153 struct ctrl_clk_vin_v10 cal_v10;
154 struct ctrl_clk_vin_v20 cal_v20;
155};
156
157struct ctrl_clk_vin_device_info_data_v10 {
158 struct ctrl_clk_vin_v10 vin_cal;
159};
160
161struct ctrl_clk_vin_device_info_data_v20 {
162 u8 cal_type;
163 union ctrl_clk_vin_data_v20 vin_cal;
164};
165
166union ctrl_clk_clk_prog_1x_source_data {
167 struct ctrl_clk_clk_prog_1x_source_pll pll;
168};
169
170struct ctrl_clk_vf_pair {
171 u16 freq_mhz;
172 u32 voltage_uv;
173};
174
175struct ctrl_clk_clk_domain_list_item {
176 u32 clk_domain;
177 u32 clk_freq_khz;
178 u32 clk_flags;
179 u8 current_regime_id;
180 u8 target_regime_id;
181};
182
183struct ctrl_clk_clk_domain_list_item_v1 {
184 u32 clk_domain;
185 u32 clk_freq_khz;
186 u8 regime_id;
187 u8 source;
188};
189
190struct ctrl_clk_clk_domain_list {
191 u8 num_domains;
192 struct ctrl_clk_clk_domain_list_item_v1
193 clk_domains[CTRL_BOARDOBJ_MAX_BOARD_OBJECTS];
194};
195
196#define CTRL_CLK_VF_PAIR_FREQ_MHZ_GET(pvfpair) \
197 ((pvfpair)->freq_mhz)
198
199#define CTRL_CLK_VF_PAIR_VOLTAGE_UV_GET(pvfpair) \
200 ((pvfpair)->voltage_uv)
201
202#define CTRL_CLK_VF_PAIR_FREQ_MHZ_SET(pvfpair, _freqmhz) \
203 (((pvfpair)->freq_mhz) = (_freqmhz))
204
205#define CTRL_CLK_VF_PAIR_FREQ_MHZ_SET(pvfpair, _freqmhz) \
206 (((pvfpair)->freq_mhz) = (_freqmhz))
207
208
209#define CTRL_CLK_VF_PAIR_VOLTAGE_UV_SET(pvfpair, _voltageuv) \
210 (((pvfpair)->voltage_uv) = (_voltageuv))
211
212#endif /* NVGPU_CTRLCLK_H */
generated by cgit v1.2.2 (git 2.25.0) at 2026-03-22 04:07:34 -0400