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-rw-r--r--include/clk/clk_freq_controller.h84
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diff --git a/include/clk/clk_freq_controller.h b/include/clk/clk_freq_controller.h
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1/*
2* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3*
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21*/
22
23#ifndef NVGPU_CLK_FREQ_CONTROLLER_H
24#define NVGPU_CLK_FREQ_CONTROLLER_H
25
26#define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_ALL 0xFF
27#define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_SYS 0x00
28#define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_LTC 0x01
29#define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_XBAR 0x02
30#define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC0 0x03
31#define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC1 0x04
32#define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC2 0x05
33#define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC3 0x06
34#define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC4 0x07
35#define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC5 0x08
36#define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPCS 0x09
37
38#define CTRL_CLK_CLK_FREQ_CONTROLLER_MASK_UNICAST_GPC \
39 (BIT(CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC0) | \
40 BIT(CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC1) | \
41 BIT(CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC2) | \
42 BIT(CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC3) | \
43 BIT(CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC4) | \
44 BIT(CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC5))
45
46#define CTRL_CLK_CLK_FREQ_CONTROLLER_TYPE_DISABLED 0x00
47#define CTRL_CLK_CLK_FREQ_CONTROLLER_TYPE_PI 0x01
48
49
50struct clk_freq_controller {
51 struct boardobj super;
52 u8 controller_id;
53 u8 parts_freq_mode;
54 bool bdisable;
55 u32 clk_domain;
56 s16 freq_cap_noise_unaware_vmin_above;
57 s16 freq_cap_noise_unaware_vmin_below;
58 s16 freq_hyst_pos_mhz;
59 s16 freq_hyst_neg_mhz;
60};
61
62struct clk_freq_controller_pi {
63 struct clk_freq_controller super;
64 s32 prop_gain;
65 s32 integ_gain;
66 s32 integ_decay;
67 s32 volt_delta_min;
68 s32 volt_delta_max;
69 u8 slowdown_pct_min;
70 bool bpoison;
71};
72
73struct clk_freq_controllers {
74 struct boardobjgrp_e32 super;
75 u32 sampling_period_ms;
76 struct boardobjgrpmask_e32 freq_ctrl_load_mask;
77 u8 volt_policy_idx;
78 void *pprereq_load;
79};
80
81int clk_freq_controller_sw_setup(struct gk20a *g);
82int clk_freq_controller_pmu_setup(struct gk20a *g);
83
84#endif /* NVGPU_CLK_FREQ_CONTROLLER_H */