2 files changed, 56 insertions, 55 deletions

diff --git a/mmu.c b/mmu.c
index 4881f66..23adaf2 100644
--- a/mmu.c
+++ b/mmu.c
@@ -39,46 +39,6 @@ uint32_t vram2PRAMIN(struct nvdebug_state *g, uint64_t addr) {
         return addr - pramin_base_va;
 }
 
-/* NVIDIA GMMU (GPU Memory Management Unit) uses page tables that are mostly
-  straight-forward starting with Pascal ("page table version 2"), except for a
-  few quirks (like 16-byte PDE0 entries, but all other entries are 8 bytes).
-
-  All you really need to know is that any given Page Directory Entry (PDE)
-  contains a pointer to the start of a 4k page densely filled with PDEs or Page
-  Table Entries (PTEs).
-
-  == Page Table Refresher ==
-  Page tables convert virtual addresses to physical addresses, and they do this
-  via a tree structure. Leafs (PTEs) contain a physical address, and the path
-  from root to leaf is defined by the virtual address. Non-leaf nodes are PDEs.
-  When decending, the virtual address is sliced into pieces, and one slice is
-  used at each level (as an index) to select the next-visited node (in level+1).
-
-  V2 of NVIDIA's page table format uses 4 levels of PDEs and a final level of
-  PTEs. How the virtual address is sliced to yield an index into each level and
-  a page offset is shown by Fig 1.
-
-  == Figure 1 ==
-  Page Offset (12 bits) <---------------------------------------+
-  Page Table Entry (PTE) (9 bits) <--------------------+        |
-  Page Directory Entry (PDE) 0 (8 bits) <-----+        |        |
-  PDE1 (8 bits) <--------------------+        |        |        |
-  PDE2 (8 bits) <-----------+        |        |        |        |
-  PDE3 (2 bits) <--+        |        |        |        |        |
-                   ^        ^        ^        ^        ^        ^
-  Virtual addr: [49, 47] [46, 38] [37, 29] [28, 21] [20, 12] [11, 0]
-
-  The following arrays merely represent different projections of Fig. 1, and
-  only one is strictly needed to reconstruct all the others. However, due to
-  the complexity of page tables, we include all of these to aid in readability.
-*/
-// How many nodes/entries per level in V2 of NVIDIA's page table format
-static const int NV_MMU_PT_V2_SZ[5] = {4, 512, 512, 256, 512};
-// Size in bytes of an entry at a particular level
-static const int NV_MMU_PT_V2_ENTRY_SZ[5] = {8, 8, 8, 16, 8};
-// Which bit index is the least significant in indexing each page level
-static const int NV_MMU_PT_V2_LSB[5] = {47, 38, 29, 21, 12};
-
 // Convert a GPU physical address to CPU virtual address via the PRAMIN window
 void __iomem *phy2PRAMIN(struct nvdebug_state* g, uint64_t phy) {
         return g->regs + NV_PRAMIN + vram2PRAMIN(g, phy);
@@ -90,6 +50,7 @@ void __iomem *off2BAR2(struct nvdebug_state* g, uint32_t off) {
 }
 */
 
+// Internal helper for search_page_directory().
 uint64_t search_page_directory_subtree(struct nvdebug_state *g,
                                        void __iomem *pde_offset,
                                        void __iomem *(*off2addr)(struct nvdebug_state*, uint64_t),
@@ -114,7 +75,7 @@ uint64_t search_page_directory_subtree(struct nvdebug_state *g,
         }
         printk(KERN_INFO "[nvdebug] Found PDE pointing to %llx in ap '%d' at lvl %d (raw: %x)\n", ((u64)entry.addr) << 12, entry.target, level, entry.raw);
         // Depth-first search of the page table
-        for (i = 0; i < NV_MMU_PT_V2_SZ[level]; i++) {
+        for (i = 0; i < NV_MMU_PT_V2_SZ[level + 1]; i++) {
                 next = off2addr(g, ((uint64_t)entry.addr << 12) + NV_MMU_PT_V2_ENTRY_SZ[level + 1] * i);
                 // off2addr can fail
                 if (!next) {
@@ -128,12 +89,17 @@ uint64_t search_page_directory_subtree(struct nvdebug_state *g,
         return 0;
 }
 
-/* Search a page directory of the GPU MMU
+/* GPU Physical address -> Virtual address ("reverse" translation)
+
+   Depth-first search a page directory of the GPU MMU for where a particular
+   physical address is mapped. Upon finding a mapping, the virtual address is
+   returned.
+
   @param pde_offset   Dereferenceable pointer to the start of the PDE3 entries
-  @param off2addr     Func to converts VRAM phys addresses to valid CPU VAs
+  @param off2addr     Func to convert VRAM phys addresses to valid CPU VAs
   @param addr_to_find Physical address to reconstruct the virtual address of
   @return 0 on error, otherwise the virtual address at which addr_to_find is
-          mapped into by this page table.
+          mapped into by this page table. (Zero is not a valid virtual address)
 */
 uint64_t search_page_directory(struct nvdebug_state *g,
                                void __iomem *pde_offset,
diff --git a/nvdebug.h b/nvdebug.h
index 39b2e6e..fcc6cff 100644
--- a/nvdebug.h
+++ b/nvdebug.h
@@ -856,13 +856,46 @@ typedef union {
         uint64_t raw;
 } page_dir_config_t;
 
-/* Page directory entry
-
-  Note: Format changed with Pascal (how?)
-
-  Support: Pascal, Volta, Turing, Ampere, Ada
+/* NVIDIA GMMU (GPU Memory Management Unit) uses page tables that are mostly
+  straight-forward starting with Pascal ("page table version 2"), except for a
+  few quirks (like 16-byte PDE0 entries, but all other entries are 8 bytes).
+
+  All you really need to know is that any given Page Directory Entry (PDE)
+  contains a pointer to the start of a 4k page densely filled with PDEs or Page
+  Table Entries (PTEs).
+
+  == Page Table Refresher ==
+  Page tables convert virtual addresses to physical addresses, and they do this
+  via a tree structure. Leafs (PTEs) contain a physical address, and the path
+  from root to leaf is defined by the virtual address. Non-leaf nodes are PDEs.
+  When decending, the virtual address is sliced into pieces, and one slice is
+  used at each level (as an index) to select the next-visited node (in level+1).
+
+  V2 of NVIDIA's page table format uses 4 levels of PDEs and a final level of
+  PTEs. How the virtual address is sliced to yield an index into each level and
+  a page offset is shown by Fig 1.
+
+  == Figure 1 ==
+  Page Offset (12 bits) <---------------------------------------+
+  Page Table Entry (PTE) (9 bits) <--------------------+        |
+  Page Directory Entry (PDE) 0 (8 bits) <-----+        |        |
+  PDE1 (9 bits) <--------------------+        |        |        |
+  PDE2 (9 bits) <-----------+        |        |        |        |
+  PDE3 (2 bits) <--+        |        |        |        |        |
+                   ^        ^        ^        ^        ^        ^
+  Virtual addr: [48, 47] [46, 38] [37, 29] [28, 21] [20, 12] [11, 0]
+
+  The following arrays merely represent different projections of Fig. 1, and
+  only one is strictly needed to reconstruct all the others. However, due to
+  the complexity of page tables, we include all of these to aid in readability.
 */
-// FIXME: PDE/PTEs are actually 64 bits =S
+// How many nodes/entries per level in V2 of NVIDIA's page table format
+static const int NV_MMU_PT_V2_SZ[5] = {4, 512, 512, 256, 512};
+// Size in bytes of an entry at a particular level
+static const int NV_MMU_PT_V2_ENTRY_SZ[5] = {8, 8, 8, 16, 8};
+// Which bit index is the least significant in indexing each page level
+static const int NV_MMU_PT_V2_LSB[5] = {47, 38, 29, 21, 12};
+
 // Important: Aperture keys are different with PDEs
 enum PD_TARGET {
         PD_AND_TARGET_INVALID = 0,  // b000
@@ -894,25 +927,27 @@ static inline const char *pd_target_to_text(enum PD_TARGET t) {
         }
 }
 
-// PDE/PTE V2 type
+// Page Directory Entry/Page Table Entry V2 type
 // Note: As the meaning of target (bits 2:1) changes depending on if the entry
 //       is a PTE or not, this combines them into a single target field to
 //       simplify comparisons.
 // Support: Pascal, Volta, Turing, Ampere, Ada
 //
 // V3 introduced with Hopper, but Hopper and Blackwell also support V2
+//
+// FIXME: This structure is 32 bits, but PDE/PTEs are actually 64 bits!
 typedef union {
         // Page Directory Entry (PDE)
         struct {
-                bool is_pte:1;
-                 uint32_t __target:2;
+                enum PD_TARGET target:3;
                 bool is_volatile:1;
                  uint32_t padding1:4;
                 uint32_t addr:24;
         } __attribute__((packed));
         // Page Table Entry (PTE)
         struct {
-                enum PD_TARGET target:3;
+                bool is_pte:1;
+                enum INST_TARGET aperture:2;
                  uint32_t __is_volatile:1;
                 bool is_encrypted:1;
                 bool is_privileged:1;
@@ -923,7 +958,7 @@ typedef union {
         uint32_t raw;
 } page_dir_entry_t;
 
-// PDE/PTE V1 types
+// Page Directory Entry/Page Table Entry V1 type
 // Support: Fermi, Kepler, Maxwell
 enum V1_PD_TARGET {
         PD_TARGET_INVALID = 0,