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-rw-r--r--include/HOW_TO_REBUILD_THIS.md22
-rw-r--r--include/clk/clk_arb.c4
-rw-r--r--include/gk20a/fifo_gk20a.c54
-rw-r--r--include/gk20a/fifo_gk20a.h7
-rw-r--r--include/gk20a/gk20a.c7
-rw-r--r--include/gk20a/gr_gk20a.c108
-rw-r--r--include/gk20a/gr_gk20a.h5
-rw-r--r--include/gk20a/hw_bus_gk20a.h171
-rw-r--r--include/gk20a/hw_ccsr_gk20a.h163
-rw-r--r--include/gk20a/hw_ce2_gk20a.h87
-rw-r--r--include/gk20a/hw_ctxsw_prog_gk20a.h447
-rw-r--r--include/gk20a/hw_falcon_gk20a.h559
-rw-r--r--include/gk20a/hw_fb_gk20a.h263
-rw-r--r--include/gk20a/hw_fifo_gk20a.h619
-rw-r--r--include/gk20a/hw_flush_gk20a.h187
-rw-r--r--include/gk20a/hw_gmmu_gk20a.h283
-rw-r--r--include/gk20a/hw_gr_gk20a.h3807
-rw-r--r--include/gk20a/hw_ltc_gk20a.h455
-rw-r--r--include/gk20a/hw_mc_gk20a.h291
-rw-r--r--include/gk20a/hw_pbdma_gk20a.h575
-rw-r--r--include/gk20a/hw_perf_gk20a.h211
-rw-r--r--include/gk20a/hw_pram_gk20a.h63
-rw-r--r--include/gk20a/hw_pri_ringmaster_gk20a.h159
-rw-r--r--include/gk20a/hw_pri_ringstation_fbp_gk20a.h231
-rw-r--r--include/gk20a/hw_pri_ringstation_gpc_gk20a.h79
-rw-r--r--include/gk20a/hw_pri_ringstation_sys_gk20a.h91
-rw-r--r--include/gk20a/hw_proj_gk20a.h167
-rw-r--r--include/gk20a/hw_pwr_gk20a.h823
-rw-r--r--include/gk20a/hw_ram_gk20a.h443
-rw-r--r--include/gk20a/hw_therm_gk20a.h367
-rw-r--r--include/gk20a/hw_timer_gk20a.h127
-rw-r--r--include/gk20a/hw_top_gk20a.h211
-rw-r--r--include/gk20a/hw_trim_gk20a.h315
-rw-r--r--include/nvgpu/acr/nvgpu_acr.h6
-rw-r--r--include/nvgpu/bug.h20
-rw-r--r--include/nvgpu/enabled.h9
-rw-r--r--include/nvgpu/gk20a.h8
-rw-r--r--include/nvgpu/hw/gk20a/hw_gr_gk20a.h61
-rw-r--r--include/nvgpu/hw/gm20b/hw_gr_gm20b.h14
-rw-r--r--include/nvgpu/hw/gp106/hw_gr_gp106.h4
-rw-r--r--include/nvgpu/hw/gp10b/hw_gr_gp10b.h4
-rw-r--r--include/nvgpu/hw/gv100/hw_gr_gv100.h4
-rw-r--r--include/nvgpu/hw/gv11b/hw_gr_gv11b.h4
-rw-r--r--include/nvgpu/log.h3
-rw-r--r--include/nvgpu/nvgpu_err.h359
-rw-r--r--include/nvgpu/nvlink.h2
-rw-r--r--include/nvgpu/pmu.h20
-rw-r--r--include/nvgpu/pmuif/gpmuif_pg.h14
-rw-r--r--include/nvgpu/tsg.h4
-rw-r--r--include/os/linux/debug.c4
-rw-r--r--include/os/linux/driver_common.c69
-rw-r--r--include/os/linux/ecc_linux.h49
-rw-r--r--include/os/linux/ioctl_clk_arb.c17
-rw-r--r--include/os/linux/ioctl_ctrl.c122
-rw-r--r--include/os/linux/ioctl_tsg.c26
-rw-r--r--include/os/linux/module.c22
-rw-r--r--include/os/linux/os_linux.h7
-rw-r--r--include/os/linux/platform_gv11b_tegra.c4
-rw-r--r--include/os/linux/scale.c29
-rw-r--r--include/os/linux/sdl.c341
-rw-r--r--include/os/linux/vm.c8
-rw-r--r--include/os/posix/nvgpu.c18
-rw-r--r--nvdebug.h6
63 files changed, 1305 insertions, 11354 deletions
diff --git a/include/HOW_TO_REBUILD_THIS.md b/include/HOW_TO_REBUILD_THIS.md
new file mode 100644
index 0000000..dcb1084
--- /dev/null
+++ b/include/HOW_TO_REBUILD_THIS.md
@@ -0,0 +1,22 @@
1First the internal `include` and `os` directories:
2```
3cp -r /playpen/Linux_for_Tegra/source/public/kernel/nvgpu/drivers/gpu/nvgpu/include/nvgpu/
4cp -r /playpen/Linux_for_Tegra/source/public/kernel/nvgpu/drivers/gpu/nvgpu/os include/
5```
6
7Then every directory needed by either of those includes:
8```
9cp -r /playpen/Linux_for_Tegra/source/public/kernel/nvgpu/drivers/gpu/nvgpu/os include/
10/playpen/Linux_for_Tegra/source/public/kernel/nvgpu/drivers/gpu/nvgpu/gk20a include/
11/playpen/Linux_for_Tegra/source/public/kernel/nvgpu/drivers/gpu/nvgpu/ctrl include/
12/playpen/Linux_for_Tegra/source/public/kernel/nvgpu/drivers/gpu/nvgpu/clk include/
13/playpen/Linux_for_Tegra/source/public/kernel/nvgpu/drivers/gpu/nvgpu/boardobj include/
14/playpen/Linux_for_Tegra/source/public/kernel/nvgpu/drivers/gpu/nvgpu/pmu_perf include/
15/playpen/Linux_for_Tegra/source/public/kernel/nvgpu/drivers/gpu/nvgpu/pstate include/
16/playpen/Linux_for_Tegra/source/public/kernel/nvgpu/drivers/gpu/nvgpu/volt include/
17/playpen/Linux_for_Tegra/source/public/kernel/nvgpu/drivers/gpu/nvgpu/lpwr include/
18/playpen/Linux_for_Tegra/source/public/kernel/nvgpu/drivers/gpu/nvgpu/pmgr include/
19/playpen/Linux_for_Tegra/source/public/kernel/nvgpu/drivers/gpu/nvgpu/therm include/
20```
21
22Make sure to pull the same version of L4T that you're building on! The structure layout is highly dependant on the version.
diff --git a/include/clk/clk_arb.c b/include/clk/clk_arb.c
index 6cf005c..8e9fb41 100644
--- a/include/clk/clk_arb.c
+++ b/include/clk/clk_arb.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2016-2021, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"), 5 * copy of this software and associated documentation files (the "Software"),
@@ -886,8 +886,8 @@ void nvgpu_clk_arb_free_session(struct nvgpu_ref *refcount)
886 nvgpu_spinlock_acquire(&session->session_lock); 886 nvgpu_spinlock_acquire(&session->session_lock);
887 nvgpu_list_for_each_entry_safe(dev, tmp, &session->targets, 887 nvgpu_list_for_each_entry_safe(dev, tmp, &session->targets,
888 nvgpu_clk_dev, node) { 888 nvgpu_clk_dev, node) {
889 nvgpu_ref_put(&dev->refcount, nvgpu_clk_arb_free_fd);
890 nvgpu_list_del(&dev->node); 889 nvgpu_list_del(&dev->node);
890 nvgpu_ref_put(&dev->refcount, nvgpu_clk_arb_free_fd);
891 } 891 }
892 nvgpu_spinlock_release(&session->session_lock); 892 nvgpu_spinlock_release(&session->session_lock);
893 893
diff --git a/include/gk20a/fifo_gk20a.c b/include/gk20a/fifo_gk20a.c
index 4477f7c..77babc7 100644
--- a/include/gk20a/fifo_gk20a.c
+++ b/include/gk20a/fifo_gk20a.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * GK20A Graphics FIFO (gr host) 2 * GK20A Graphics FIFO (gr host)
3 * 3 *
4 * Copyright (c) 2011-2020, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2011-2021, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a 6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"), 7 * copy of this software and associated documentation files (the "Software"),
@@ -58,8 +58,6 @@
58#include <nvgpu/hw/gk20a/hw_top_gk20a.h> 58#include <nvgpu/hw/gk20a/hw_top_gk20a.h>
59#include <nvgpu/hw/gk20a/hw_gr_gk20a.h> 59#include <nvgpu/hw/gk20a/hw_gr_gk20a.h>
60 60
61#include <os/linux/os_linux.h>
62
63#define FECS_METHOD_WFI_RESTORE 0x80000 61#define FECS_METHOD_WFI_RESTORE 0x80000
64#define FECS_MAILBOX_0_ACK_RESTORE 0x4 62#define FECS_MAILBOX_0_ACK_RESTORE 0x4
65 63
@@ -1409,6 +1407,7 @@ static void gk20a_fifo_handle_chsw_fault(struct gk20a *g)
1409 intr = gk20a_readl(g, fifo_intr_chsw_error_r()); 1407 intr = gk20a_readl(g, fifo_intr_chsw_error_r());
1410 nvgpu_err(g, "chsw: %08x", intr); 1408 nvgpu_err(g, "chsw: %08x", intr);
1411 gk20a_fecs_dump_falcon_stats(g); 1409 gk20a_fecs_dump_falcon_stats(g);
1410 gk20a_gpccs_dump_falcon_stats(g);
1412 gk20a_writel(g, fifo_intr_chsw_error_r(), intr); 1411 gk20a_writel(g, fifo_intr_chsw_error_r(), intr);
1413} 1412}
1414 1413
@@ -1604,6 +1603,7 @@ int gk20a_fifo_deferred_reset(struct gk20a *g, struct channel_gk20a *ch)
1604 engines = gk20a_fifo_engines_on_id(g, tsg->tsgid, true); 1603 engines = gk20a_fifo_engines_on_id(g, tsg->tsgid, true);
1605 } else { 1604 } else {
1606 nvgpu_err(g, "chid: %d is not bound to tsg", ch->chid); 1605 nvgpu_err(g, "chid: %d is not bound to tsg", ch->chid);
1606 engines = g->fifo.deferred_fault_engines;
1607 } 1607 }
1608 1608
1609 if (engines == 0U) { 1609 if (engines == 0U) {
@@ -1724,6 +1724,7 @@ static bool gk20a_fifo_handle_mmu_fault_locked(
1724 1724
1725 if (ctxsw) { 1725 if (ctxsw) {
1726 gk20a_fecs_dump_falcon_stats(g); 1726 gk20a_fecs_dump_falcon_stats(g);
1727 gk20a_gpccs_dump_falcon_stats(g);
1727 nvgpu_err(g, "gr_status_r : 0x%x", 1728 nvgpu_err(g, "gr_status_r : 0x%x",
1728 gk20a_readl(g, gr_status_r())); 1729 gk20a_readl(g, gr_status_r()));
1729 } 1730 }
@@ -2198,9 +2199,9 @@ int gk20a_fifo_tsg_unbind_channel_verify_status(struct channel_gk20a *ch)
2198 struct gk20a *g = ch->g; 2199 struct gk20a *g = ch->g;
2199 2200
2200 if (gk20a_fifo_channel_status_is_next(g, ch->chid)) { 2201 if (gk20a_fifo_channel_status_is_next(g, ch->chid)) {
2201 nvgpu_err(g, "Channel %d to be removed from TSG %d has NEXT set!", 2202 nvgpu_log_info(g, "Channel %d to be removed from TSG %d has NEXT set!",
2202 ch->chid, ch->tsgid); 2203 ch->chid, ch->tsgid);
2203 return -EINVAL; 2204 return -EAGAIN;
2204 } 2205 }
2205 2206
2206 if (g->ops.fifo.tsg_verify_status_ctx_reload) { 2207 if (g->ops.fifo.tsg_verify_status_ctx_reload) {
@@ -2983,7 +2984,7 @@ static u32 gk20a_fifo_get_preempt_timeout(struct gk20a *g)
2983} 2984}
2984 2985
2985int gk20a_fifo_is_preempt_pending(struct gk20a *g, u32 id, 2986int gk20a_fifo_is_preempt_pending(struct gk20a *g, u32 id,
2986 unsigned int id_type) 2987 unsigned int id_type, bool preempt_retries_left)
2987{ 2988{
2988 struct nvgpu_timeout timeout; 2989 struct nvgpu_timeout timeout;
2989 u32 delay = GR_IDLE_CHECK_DEFAULT; 2990 u32 delay = GR_IDLE_CHECK_DEFAULT;
@@ -3039,7 +3040,8 @@ void gk20a_fifo_preempt_timeout_rc(struct gk20a *g, struct channel_gk20a *ch)
3039 RC_TYPE_PREEMPT_TIMEOUT); 3040 RC_TYPE_PREEMPT_TIMEOUT);
3040} 3041}
3041 3042
3042int __locked_fifo_preempt(struct gk20a *g, u32 id, bool is_tsg) 3043int __locked_fifo_preempt(struct gk20a *g, u32 id, bool is_tsg,
3044 bool preempt_retries_left)
3043{ 3045{
3044 int ret; 3046 int ret;
3045 unsigned int id_type; 3047 unsigned int id_type;
@@ -3051,8 +3053,17 @@ int __locked_fifo_preempt(struct gk20a *g, u32 id, bool is_tsg)
3051 3053
3052 id_type = is_tsg ? ID_TYPE_TSG : ID_TYPE_CHANNEL; 3054 id_type = is_tsg ? ID_TYPE_TSG : ID_TYPE_CHANNEL;
3053 3055
3054 /* wait for preempt */ 3056 /*
3055 ret = g->ops.fifo.is_preempt_pending(g, id, id_type); 3057 * Poll for preempt done. if stalling interrupts are pending
3058 * while preempt is in progress we poll for stalling interrupts
3059 * to finish based on return value from this function and
3060 * retry preempt again.
3061 * If HW is hung, on the last retry instance we try to identify
3062 * the engines hung and set the runlist reset_eng_bitmask
3063 * and mark preemption completion.
3064 */
3065 ret = g->ops.fifo.is_preempt_pending(g, id, id_type,
3066 preempt_retries_left);
3056 3067
3057 return ret; 3068 return ret;
3058} 3069}
@@ -3074,7 +3085,7 @@ int gk20a_fifo_preempt_channel(struct gk20a *g, struct channel_gk20a *ch)
3074 3085
3075 mutex_ret = nvgpu_pmu_mutex_acquire(&g->pmu, PMU_MUTEX_ID_FIFO, &token); 3086 mutex_ret = nvgpu_pmu_mutex_acquire(&g->pmu, PMU_MUTEX_ID_FIFO, &token);
3076 3087
3077 ret = __locked_fifo_preempt(g, ch->chid, false); 3088 ret = __locked_fifo_preempt(g, ch->chid, false, false);
3078 3089
3079 if (!mutex_ret) { 3090 if (!mutex_ret) {
3080 nvgpu_pmu_mutex_release(&g->pmu, PMU_MUTEX_ID_FIFO, &token); 3091 nvgpu_pmu_mutex_release(&g->pmu, PMU_MUTEX_ID_FIFO, &token);
@@ -3114,7 +3125,7 @@ int gk20a_fifo_preempt_tsg(struct gk20a *g, struct tsg_gk20a *tsg)
3114 3125
3115 mutex_ret = nvgpu_pmu_mutex_acquire(&g->pmu, PMU_MUTEX_ID_FIFO, &token); 3126 mutex_ret = nvgpu_pmu_mutex_acquire(&g->pmu, PMU_MUTEX_ID_FIFO, &token);
3116 3127
3117 ret = __locked_fifo_preempt(g, tsg->tsgid, true); 3128 ret = __locked_fifo_preempt(g, tsg->tsgid, true, false);
3118 3129
3119 if (!mutex_ret) { 3130 if (!mutex_ret) {
3120 nvgpu_pmu_mutex_release(&g->pmu, PMU_MUTEX_ID_FIFO, &token); 3131 nvgpu_pmu_mutex_release(&g->pmu, PMU_MUTEX_ID_FIFO, &token);
@@ -3584,36 +3595,17 @@ void gk20a_fifo_runlist_hw_submit(struct gk20a *g, u32 runlist_id,
3584{ 3595{
3585 struct fifo_runlist_info_gk20a *runlist = NULL; 3596 struct fifo_runlist_info_gk20a *runlist = NULL;
3586 u64 runlist_iova; 3597 u64 runlist_iova;
3587 u32 val_wrote;
3588 struct nvgpu_os_linux *l;
3589 3598
3590 runlist = &g->fifo.runlist_info[runlist_id]; 3599 runlist = &g->fifo.runlist_info[runlist_id];
3591 runlist_iova = nvgpu_mem_get_addr(g, &runlist->mem[buffer_index]); 3600 runlist_iova = nvgpu_mem_get_addr(g, &runlist->mem[buffer_index]);
3592 3601
3593
3594 if (count != 0) { 3602 if (count != 0) {
3595 printk(KERN_INFO "Runlist base register: %0x\n", fifo_runlist_base_r());
3596 printk(KERN_INFO "Runlist KVA: %px\n", (void*)(runlist->mem[buffer_index].cpu_va));
3597 printk(KERN_INFO "Runlist PA: %px\n", (void*)virt_to_phys((runlist->mem[buffer_index].cpu_va)));
3598 printk(KERN_INFO "Runlist dma_address: %px\n", (void*)(runlist->mem[buffer_index].priv.sgt->sgl->dma_address));
3599 printk(KERN_INFO "Runlist pages KVA: %px\n", (void*)(runlist->mem[buffer_index].priv.pages));
3600 printk(KERN_INFO "Runlist pages PA: %px\n", (void*)virt_to_phys(runlist->mem[buffer_index].priv.pages));
3601 printk(KERN_INFO "Runlist dma_address: %px\n", (void*)(runlist->mem[buffer_index].priv.sgt->sgl->dma_address));
3602 printk(KERN_INFO "Runlist page_to_phys %px + offset %px\n", (void*)(page_to_phys(sg_page(runlist->mem[buffer_index].priv.sgt->sgl))), (void*)(runlist->mem[buffer_index].priv.sgt->sgl->offset));
3603 printk(KERN_INFO "Runlist IOVA: %px\n", (void*)runlist_iova);
3604 printk(KERN_INFO "Using struct gk20* %px\n", g);
3605 printk(KERN_INFO "g->name: %s, g->power_on: %d, g->sw_ready: %d, g->is_virtual %d\n", g->name, g->power_on, g->sw_ready, g->is_virtual);
3606 printk(KERN_INFO "COHERENT_SYSMEM? %d, iommuable? %d\n", nvgpu_is_enabled(g, NVGPU_USE_COHERENT_SYSMEM), nvgpu_iommuable(g));
3607 l = container_of(g, struct nvgpu_os_linux, g);
3608 printk(KERN_INFO "l->regs %px\n", l->regs);
3609 gk20a_writel(g, fifo_runlist_base_r(), 3603 gk20a_writel(g, fifo_runlist_base_r(),
3610 fifo_runlist_base_ptr_f(u64_lo32(runlist_iova >> 12)) | 3604 fifo_runlist_base_ptr_f(u64_lo32(runlist_iova >> 12)) |
3611 nvgpu_aperture_mask(g, &runlist->mem[buffer_index], 3605 nvgpu_aperture_mask(g, &runlist->mem[buffer_index],
3612 fifo_runlist_base_target_sys_mem_ncoh_f(), 3606 fifo_runlist_base_target_sys_mem_ncoh_f(),
3613 fifo_runlist_base_target_sys_mem_coh_f(), 3607 fifo_runlist_base_target_sys_mem_coh_f(),
3614 fifo_runlist_base_target_vid_mem_f())); 3608 fifo_runlist_base_target_vid_mem_f()));
3615 val_wrote = nvgpu_readl(g, 0x2270);
3616 printk(KERN_INFO "Wrote runlist base as %0llx\n", (u64)(val_wrote & 0x0fffffff) << 12);
3617 } 3609 }
3618 3610
3619 gk20a_writel(g, fifo_runlist_r(), 3611 gk20a_writel(g, fifo_runlist_r(),
@@ -3806,7 +3798,7 @@ static int __locked_fifo_reschedule_preempt_next(struct channel_gk20a *ch,
3806 gk20a_readl(g, fifo_preempt_r())); 3798 gk20a_readl(g, fifo_preempt_r()));
3807#endif 3799#endif
3808 if (wait_preempt) { 3800 if (wait_preempt) {
3809 g->ops.fifo.is_preempt_pending(g, preempt_id, preempt_type); 3801 g->ops.fifo.is_preempt_pending(g, preempt_id, preempt_type, false);
3810 } 3802 }
3811#ifdef TRACEPOINTS_ENABLED 3803#ifdef TRACEPOINTS_ENABLED
3812 trace_gk20a_reschedule_preempted_next(ch->chid); 3804 trace_gk20a_reschedule_preempted_next(ch->chid);
diff --git a/include/gk20a/fifo_gk20a.h b/include/gk20a/fifo_gk20a.h
index 26365ca..078236d 100644
--- a/include/gk20a/fifo_gk20a.h
+++ b/include/gk20a/fifo_gk20a.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * GK20A graphics fifo (gr host) 2 * GK20A graphics fifo (gr host)
3 * 3 *
4 * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2011-2021, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a 6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"), 7 * copy of this software and associated documentation files (the "Software"),
@@ -388,8 +388,9 @@ void gk20a_fifo_channel_unbind(struct channel_gk20a *ch_gk20a);
388u32 gk20a_fifo_intr_0_error_mask(struct gk20a *g); 388u32 gk20a_fifo_intr_0_error_mask(struct gk20a *g);
389 389
390int gk20a_fifo_is_preempt_pending(struct gk20a *g, u32 id, 390int gk20a_fifo_is_preempt_pending(struct gk20a *g, u32 id,
391 unsigned int id_type); 391 unsigned int id_type, bool preempt_retries_left);
392int __locked_fifo_preempt(struct gk20a *g, u32 id, bool is_tsg); 392int __locked_fifo_preempt(struct gk20a *g, u32 id, bool is_tsg,
393 bool preempt_retries_left);
393void gk20a_fifo_preempt_timeout_rc_tsg(struct gk20a *g, struct tsg_gk20a *tsg); 394void gk20a_fifo_preempt_timeout_rc_tsg(struct gk20a *g, struct tsg_gk20a *tsg);
394void gk20a_fifo_preempt_timeout_rc(struct gk20a *g, struct channel_gk20a *ch); 395void gk20a_fifo_preempt_timeout_rc(struct gk20a *g, struct channel_gk20a *ch);
395int gk20a_fifo_setup_ramfc(struct channel_gk20a *c, 396int gk20a_fifo_setup_ramfc(struct channel_gk20a *c,
diff --git a/include/gk20a/gk20a.c b/include/gk20a/gk20a.c
index c3068b7..1a11716 100644
--- a/include/gk20a/gk20a.c
+++ b/include/gk20a/gk20a.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * GK20A Graphics 2 * GK20A Graphics
3 * 3 *
4 * Copyright (c) 2011-2020, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2011-2021, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a 6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"), 7 * copy of this software and associated documentation files (the "Software"),
@@ -39,6 +39,7 @@
39#include <nvgpu/therm.h> 39#include <nvgpu/therm.h>
40#include <nvgpu/mc.h> 40#include <nvgpu/mc.h>
41#include <nvgpu/channel_sync.h> 41#include <nvgpu/channel_sync.h>
42#include <nvgpu/nvgpu_err.h>
42 43
43#include <trace/events/gk20a.h> 44#include <trace/events/gk20a.h>
44 45
@@ -525,6 +526,10 @@ static void gk20a_free_cb(struct nvgpu_ref *refcount)
525 struct gk20a *g = container_of(refcount, 526 struct gk20a *g = container_of(refcount,
526 struct gk20a, refcount); 527 struct gk20a, refcount);
527 528
529#ifdef CONFIG_NVGPU_SUPPORT_LINUX_ECC_ERROR_REPORTING
530 nvgpu_deinit_ecc_reporting(g);
531#endif
532
528 nvgpu_log(g, gpu_dbg_shutdown, "Freeing GK20A struct!"); 533 nvgpu_log(g, gpu_dbg_shutdown, "Freeing GK20A struct!");
529 534
530 gk20a_ce_destroy(g); 535 gk20a_ce_destroy(g);
diff --git a/include/gk20a/gr_gk20a.c b/include/gk20a/gr_gk20a.c
index 7bcf528..1eda853 100644
--- a/include/gk20a/gr_gk20a.c
+++ b/include/gk20a/gr_gk20a.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * GK20A Graphics 2 * GK20A Graphics
3 * 3 *
4 * Copyright (c) 2011-2020, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2011-2023, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a 6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"), 7 * copy of this software and associated documentation files (the "Software"),
@@ -121,6 +121,83 @@ int gr_gk20a_get_ctx_id(struct gk20a *g,
121 return 0; 121 return 0;
122} 122}
123 123
124void gk20a_gpccs_dump_falcon_stats(struct gk20a *g)
125{
126 unsigned int i;
127
128 nvgpu_err(g, "gr_gpc0_gpccs_falcon_irqstat : %d",
129 gk20a_readl(g, gr_gpc0_gpccs_falcon_irqstat_r()));
130 nvgpu_err(g, "gr_gpc0_gpccs_falcon_irqmode : %d",
131 gk20a_readl(g, gr_gpc0_gpccs_falcon_irqmode_r()));
132 nvgpu_err(g, "gr_gpc0_gpccs_falcon_irqmask : %d",
133 gk20a_readl(g, gr_gpc0_gpccs_falcon_irqmask_r()));
134 nvgpu_err(g, "gr_gpc0_gpccs_falcon_irqdest : %d",
135 gk20a_readl(g, gr_gpc0_gpccs_falcon_irqdest_r()));
136 nvgpu_err(g, "gr_gpc0_gpccs_falcon_debug1 : %d",
137 gk20a_readl(g, gr_gpc0_gpccs_falcon_debug1_r()));
138 nvgpu_err(g, "gr_gpc0_gpccs_falcon_debuginfo : %d",
139 gk20a_readl(g, gr_gpc0_gpccs_falcon_debuginfo_r()));
140 nvgpu_err(g, "gr_gpc0_gpccs_falcon_engctl : %d",
141 gk20a_readl(g, gr_gpc0_gpccs_falcon_engctl_r()));
142 nvgpu_err(g, "gr_gpc0_gpccs_falcon_curctx : %d",
143 gk20a_readl(g, gr_gpc0_gpccs_falcon_curctx_r()));
144 nvgpu_err(g, "gr_gpc0_gpccs_falcon_nxtctx : %d",
145 gk20a_readl(g, gr_gpc0_gpccs_falcon_nxtctx_r()));
146 nvgpu_err(g, "gr_gpc0_gpccs_ctxsw_status_1 : %d",
147 gk20a_readl(g, gr_gpc0_gpccs_ctxsw_status_1_r()));
148
149 for (i = 0; i < g->ops.gr.gpc0_gpccs_ctxsw_mailbox_size(); i++) {
150 nvgpu_err(g, "gr_gpc0_gpccs_ctxsw_mailbox_r(%d) : 0x%x",
151 i, gk20a_readl(g, gr_gpc0_gpccs_ctxsw_mailbox_r(i)));
152 }
153
154
155 gk20a_writel(g, gr_gpc0_gpccs_falcon_icd_cmd_r(),
156 gr_gpc0_gpccs_falcon_icd_cmd_opc_rreg_f() |
157 gr_gpc0_gpccs_falcon_icd_cmd_idx_f(PMU_FALCON_REG_IMB));
158 nvgpu_err(g, "GPC0_GPCCS_FALCON_REG_IMB : 0x%x",
159 gk20a_readl(g, gr_gpc_gpccs_falcon_icd_rdata_r()));
160
161 gk20a_writel(g, gr_gpc0_gpccs_falcon_icd_cmd_r(),
162 gr_gpc0_gpccs_falcon_icd_cmd_opc_rreg_f() |
163 gr_gpc0_gpccs_falcon_icd_cmd_idx_f(PMU_FALCON_REG_DMB));
164 nvgpu_err(g, "GPC0_GPCCS_FALCON_REG_DMB : 0x%x",
165 gk20a_readl(g, gr_gpc_gpccs_falcon_icd_rdata_r()));
166
167 gk20a_writel(g, gr_gpc0_gpccs_falcon_icd_cmd_r(),
168 gr_gpc0_gpccs_falcon_icd_cmd_opc_rreg_f() |
169 gr_gpc0_gpccs_falcon_icd_cmd_idx_f(PMU_FALCON_REG_CSW));
170 nvgpu_err(g, "GPC0_GPCCS_FALCON_REG_CSW : 0x%x",
171 gk20a_readl(g, gr_gpc_gpccs_falcon_icd_rdata_r()));
172
173 gk20a_writel(g, gr_gpc0_gpccs_falcon_icd_cmd_r(),
174 gr_gpc0_gpccs_falcon_icd_cmd_opc_rreg_f() |
175 gr_gpc0_gpccs_falcon_icd_cmd_idx_f(PMU_FALCON_REG_CTX));
176 nvgpu_err(g, "GPC0_GPCCS_FALCON_REG_CTX : 0x%x",
177 gk20a_readl(g, gr_gpc_gpccs_falcon_icd_rdata_r()));
178
179 gk20a_writel(g, gr_gpc0_gpccs_falcon_icd_cmd_r(),
180 gr_gpc0_gpccs_falcon_icd_cmd_opc_rreg_f() |
181 gr_gpc0_gpccs_falcon_icd_cmd_idx_f(PMU_FALCON_REG_EXCI));
182 nvgpu_err(g, "GPC0_GPCCS_FALCON_REG_EXCI : 0x%x",
183 gk20a_readl(g, gr_gpc_gpccs_falcon_icd_rdata_r()));
184
185
186 for (i = 0; i < 4U; i++) {
187 gk20a_writel(g, gr_gpc0_gpccs_falcon_icd_cmd_r(),
188 gr_gpc0_gpccs_falcon_icd_cmd_opc_rreg_f() |
189 gr_gpc0_gpccs_falcon_icd_cmd_idx_f(PMU_FALCON_REG_PC));
190 nvgpu_err(g, "GPC0_GPCCS_FALCON_REG_PC : 0x%x",
191 gk20a_readl(g, gr_gpc_gpccs_falcon_icd_rdata_r()));
192
193 gk20a_writel(g, gr_gpc0_gpccs_falcon_icd_cmd_r(),
194 gr_gpc0_gpccs_falcon_icd_cmd_opc_rreg_f() |
195 gr_gpc0_gpccs_falcon_icd_cmd_idx_f(PMU_FALCON_REG_SP));
196 nvgpu_err(g, "GPC0_GPCCS_FALCON_REG_SP : 0x%x",
197 gk20a_readl(g, gr_gpc_gpccs_falcon_icd_rdata_r()));
198 }
199}
200
124void gk20a_fecs_dump_falcon_stats(struct gk20a *g) 201void gk20a_fecs_dump_falcon_stats(struct gk20a *g)
125{ 202{
126 unsigned int i; 203 unsigned int i;
@@ -527,6 +604,7 @@ int gr_gk20a_ctx_wait_ucode(struct gk20a *g, u32 mailbox_id,
527 "timeout waiting on mailbox=%d value=0x%08x", 604 "timeout waiting on mailbox=%d value=0x%08x",
528 mailbox_id, reg); 605 mailbox_id, reg);
529 gk20a_fecs_dump_falcon_stats(g); 606 gk20a_fecs_dump_falcon_stats(g);
607 gk20a_gpccs_dump_falcon_stats(g);
530 gk20a_gr_debug_dump(g); 608 gk20a_gr_debug_dump(g);
531 return -1; 609 return -1;
532 } else if (check == WAIT_UCODE_ERROR) { 610 } else if (check == WAIT_UCODE_ERROR) {
@@ -534,6 +612,7 @@ int gr_gk20a_ctx_wait_ucode(struct gk20a *g, u32 mailbox_id,
534 "ucode method failed on mailbox=%d value=0x%08x", 612 "ucode method failed on mailbox=%d value=0x%08x",
535 mailbox_id, reg); 613 mailbox_id, reg);
536 gk20a_fecs_dump_falcon_stats(g); 614 gk20a_fecs_dump_falcon_stats(g);
615 gk20a_gpccs_dump_falcon_stats(g);
537 return -1; 616 return -1;
538 } 617 }
539 618
@@ -1583,6 +1662,10 @@ static int gr_gk20a_init_golden_ctx_image(struct gk20a *g,
1583 sw_ctx_load->l[i].value); 1662 sw_ctx_load->l[i].value);
1584 } 1663 }
1585 1664
1665 if (g->ops.gr.disable_rd_coalesce) {
1666 g->ops.gr.disable_rd_coalesce(g);
1667 }
1668
1586 if (g->ops.gr.init_preemption_state) { 1669 if (g->ops.gr.init_preemption_state) {
1587 g->ops.gr.init_preemption_state(g); 1670 g->ops.gr.init_preemption_state(g);
1588 } 1671 }
@@ -4625,16 +4708,16 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g)
4625 g->ops.fb.init_cbc(g, gr); 4708 g->ops.fb.init_cbc(g, gr);
4626 } 4709 }
4627 4710
4628 if (g->ops.gr.disable_rd_coalesce) {
4629 g->ops.gr.disable_rd_coalesce(g);
4630 }
4631
4632 /* load ctx init */ 4711 /* load ctx init */
4633 for (i = 0; i < sw_ctx_load->count; i++) { 4712 for (i = 0; i < sw_ctx_load->count; i++) {
4634 gk20a_writel(g, sw_ctx_load->l[i].addr, 4713 gk20a_writel(g, sw_ctx_load->l[i].addr,
4635 sw_ctx_load->l[i].value); 4714 sw_ctx_load->l[i].value);
4636 } 4715 }
4637 4716
4717 if (g->ops.gr.disable_rd_coalesce) {
4718 g->ops.gr.disable_rd_coalesce(g);
4719 }
4720
4638 err = gr_gk20a_wait_idle(g, gk20a_get_gr_idle_timeout(g), 4721 err = gr_gk20a_wait_idle(g, gk20a_get_gr_idle_timeout(g),
4639 GR_IDLE_CHECK_DEFAULT); 4722 GR_IDLE_CHECK_DEFAULT);
4640 if (err != 0U) { 4723 if (err != 0U) {
@@ -5297,9 +5380,10 @@ int gk20a_gr_handle_fecs_error(struct gk20a *g, struct channel_gk20a *ch,
5297 } else if ((gr_fecs_intr & 5380 } else if ((gr_fecs_intr &
5298 gr_fecs_host_int_status_watchdog_active_f()) != 0U) { 5381 gr_fecs_host_int_status_watchdog_active_f()) != 0U) {
5299 /* currently, recovery is not initiated */ 5382 /* currently, recovery is not initiated */
5300 nvgpu_err(g, "fecs watchdog triggered for channel %u, " 5383 nvgpu_err(g, "fecs watchdog triggered for channel %u", chid);
5301 "cannot ctxsw anymore !!", chid);
5302 gk20a_fecs_dump_falcon_stats(g); 5384 gk20a_fecs_dump_falcon_stats(g);
5385 gk20a_gpccs_dump_falcon_stats(g);
5386 gk20a_gr_debug_dump(g);
5303 } else if ((gr_fecs_intr & 5387 } else if ((gr_fecs_intr &
5304 gr_fecs_host_int_status_ctxsw_intr_f(CTXSW_INTR0)) != 0U) { 5388 gr_fecs_host_int_status_ctxsw_intr_f(CTXSW_INTR0)) != 0U) {
5305 u32 mailbox_value = gk20a_readl(g, gr_fecs_ctxsw_mailbox_r(6)); 5389 u32 mailbox_value = gk20a_readl(g, gr_fecs_ctxsw_mailbox_r(6));
@@ -5321,8 +5405,9 @@ int gk20a_gr_handle_fecs_error(struct gk20a *g, struct channel_gk20a *ch,
5321 } else { 5405 } else {
5322 nvgpu_err(g, 5406 nvgpu_err(g,
5323 "unhandled fecs error interrupt 0x%08x for channel %u", 5407 "unhandled fecs error interrupt 0x%08x for channel %u",
5324 gr_fecs_intr, ch->chid); 5408 gr_fecs_intr, chid);
5325 gk20a_fecs_dump_falcon_stats(g); 5409 gk20a_fecs_dump_falcon_stats(g);
5410 gk20a_gpccs_dump_falcon_stats(g);
5326 } 5411 }
5327 5412
5328 gk20a_writel(g, gr_fecs_host_int_clear_r(), gr_fecs_intr); 5413 gk20a_writel(g, gr_fecs_host_int_clear_r(), gr_fecs_intr);
@@ -8851,6 +8936,10 @@ int gr_gk20a_wait_for_pause(struct gk20a *g, struct nvgpu_warpstate *w_state)
8851 u32 gpc, tpc, sm, sm_id; 8936 u32 gpc, tpc, sm, sm_id;
8852 u32 global_mask; 8937 u32 global_mask;
8853 8938
8939 if (!g->ops.gr.get_sm_no_lock_down_hww_global_esr_mask ||
8940 !g->ops.gr.lock_down_sm || !g->ops.gr.bpt_reg_info)
8941 return -EINVAL;
8942
8854 /* Wait for the SMs to reach full stop. This condition is: 8943 /* Wait for the SMs to reach full stop. This condition is:
8855 * 1) All SMs with valid warps must be in the trap handler (SM_IN_TRAP_MODE) 8944 * 1) All SMs with valid warps must be in the trap handler (SM_IN_TRAP_MODE)
8856 * 2) All SMs in the trap handler must have equivalent VALID and PAUSED warp 8945 * 2) All SMs in the trap handler must have equivalent VALID and PAUSED warp
@@ -8908,6 +8997,9 @@ int gr_gk20a_clear_sm_errors(struct gk20a *g)
8908 u32 global_esr; 8997 u32 global_esr;
8909 u32 sm_per_tpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_SM_PER_TPC); 8998 u32 sm_per_tpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_SM_PER_TPC);
8910 8999
9000 if (!g->ops.gr.get_sm_hww_global_esr || !g->ops.gr.clear_sm_hww)
9001 return -EINVAL;
9002
8911 for (gpc = 0; gpc < gr->gpc_count; gpc++) { 9003 for (gpc = 0; gpc < gr->gpc_count; gpc++) {
8912 9004
8913 /* check if any tpc has an exception */ 9005 /* check if any tpc has an exception */
diff --git a/include/gk20a/gr_gk20a.h b/include/gk20a/gr_gk20a.h
index 08b81e8..2cd6a4f 100644
--- a/include/gk20a/gr_gk20a.h
+++ b/include/gk20a/gr_gk20a.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * GK20A Graphics Engine 2 * GK20A Graphics Engine
3 * 3 *
4 * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2011-2021, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a 6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"), 7 * copy of this software and associated documentation files (the "Software"),
@@ -438,6 +438,7 @@ struct gr_gk20a {
438}; 438};
439 439
440void gk20a_fecs_dump_falcon_stats(struct gk20a *g); 440void gk20a_fecs_dump_falcon_stats(struct gk20a *g);
441void gk20a_gpccs_dump_falcon_stats(struct gk20a *g);
441 442
442/* contexts associated with a TSG */ 443/* contexts associated with a TSG */
443struct nvgpu_gr_ctx { 444struct nvgpu_gr_ctx {
@@ -602,7 +603,7 @@ u32 gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask(struct gk20a *g);
602 if (g->support_pmu) {\ 603 if (g->support_pmu) {\
603 err = nvgpu_pg_elpg_disable(g);\ 604 err = nvgpu_pg_elpg_disable(g);\
604 if (err != 0) {\ 605 if (err != 0) {\
605 err = nvgpu_pg_elpg_enable(g); \ 606 (void)nvgpu_pg_elpg_enable(g); \
606 } \ 607 } \
607 } \ 608 } \
608 if (err == 0) { \ 609 if (err == 0) { \
diff --git a/include/gk20a/hw_bus_gk20a.h b/include/gk20a/hw_bus_gk20a.h
deleted file mode 100644
index d3bb9e9..0000000
--- a/include/gk20a/hw_bus_gk20a.h
+++ /dev/null
@@ -1,171 +0,0 @@
1/*
2 * Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22/*
23 * Function naming determines intended use:
24 *
25 * <x>_r(void) : Returns the offset for register <x>.
26 *
27 * <x>_o(void) : Returns the offset for element <x>.
28 *
29 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
30 *
31 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
32 *
33 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
34 * and masked to place it at field <y> of register <x>. This value
35 * can be |'d with others to produce a full register value for
36 * register <x>.
37 *
38 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
39 * value can be ~'d and then &'d to clear the value of field <y> for
40 * register <x>.
41 *
42 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
43 * to place it at field <y> of register <x>. This value can be |'d
44 * with others to produce a full register value for <x>.
45 *
46 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
47 * <x> value 'r' after being shifted to place its LSB at bit 0.
48 * This value is suitable for direct comparison with other unshifted
49 * values appropriate for use in field <y> of register <x>.
50 *
51 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
52 * field <y> of register <x>. This value is suitable for direct
53 * comparison with unshifted values appropriate for use in field <y>
54 * of register <x>.
55 */
56#ifndef _hw_bus_gk20a_h_
57#define _hw_bus_gk20a_h_
58
59static inline u32 bus_bar0_window_r(void)
60{
61 return 0x00001700U;
62}
63static inline u32 bus_bar0_window_base_f(u32 v)
64{
65 return (v & 0xffffffU) << 0U;
66}
67static inline u32 bus_bar0_window_target_vid_mem_f(void)
68{
69 return 0x0U;
70}
71static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void)
72{
73 return 0x2000000U;
74}
75static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void)
76{
77 return 0x3000000U;
78}
79static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void)
80{
81 return 0x00000010U;
82}
83static inline u32 bus_bar1_block_r(void)
84{
85 return 0x00001704U;
86}
87static inline u32 bus_bar1_block_ptr_f(u32 v)
88{
89 return (v & 0xfffffffU) << 0U;
90}
91static inline u32 bus_bar1_block_target_vid_mem_f(void)
92{
93 return 0x0U;
94}
95static inline u32 bus_bar1_block_target_sys_mem_coh_f(void)
96{
97 return 0x20000000U;
98}
99static inline u32 bus_bar1_block_target_sys_mem_ncoh_f(void)
100{
101 return 0x30000000U;
102}
103static inline u32 bus_bar1_block_mode_virtual_f(void)
104{
105 return 0x80000000U;
106}
107static inline u32 bus_bar2_block_r(void)
108{
109 return 0x00001714U;
110}
111static inline u32 bus_bar2_block_ptr_f(u32 v)
112{
113 return (v & 0xfffffffU) << 0U;
114}
115static inline u32 bus_bar2_block_target_vid_mem_f(void)
116{
117 return 0x0U;
118}
119static inline u32 bus_bar2_block_target_sys_mem_coh_f(void)
120{
121 return 0x20000000U;
122}
123static inline u32 bus_bar2_block_target_sys_mem_ncoh_f(void)
124{
125 return 0x30000000U;
126}
127static inline u32 bus_bar2_block_mode_virtual_f(void)
128{
129 return 0x80000000U;
130}
131static inline u32 bus_bar1_block_ptr_shift_v(void)
132{
133 return 0x0000000cU;
134}
135static inline u32 bus_bar2_block_ptr_shift_v(void)
136{
137 return 0x0000000cU;
138}
139static inline u32 bus_intr_0_r(void)
140{
141 return 0x00001100U;
142}
143static inline u32 bus_intr_0_pri_squash_m(void)
144{
145 return 0x1U << 1U;
146}
147static inline u32 bus_intr_0_pri_fecserr_m(void)
148{
149 return 0x1U << 2U;
150}
151static inline u32 bus_intr_0_pri_timeout_m(void)
152{
153 return 0x1U << 3U;
154}
155static inline u32 bus_intr_en_0_r(void)
156{
157 return 0x00001140U;
158}
159static inline u32 bus_intr_en_0_pri_squash_m(void)
160{
161 return 0x1U << 1U;
162}
163static inline u32 bus_intr_en_0_pri_fecserr_m(void)
164{
165 return 0x1U << 2U;
166}
167static inline u32 bus_intr_en_0_pri_timeout_m(void)
168{
169 return 0x1U << 3U;
170}
171#endif
diff --git a/include/gk20a/hw_ccsr_gk20a.h b/include/gk20a/hw_ccsr_gk20a.h
deleted file mode 100644
index 95151f6..0000000
--- a/include/gk20a/hw_ccsr_gk20a.h
+++ /dev/null
@@ -1,163 +0,0 @@
1/*
2 * Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22/*
23 * Function naming determines intended use:
24 *
25 * <x>_r(void) : Returns the offset for register <x>.
26 *
27 * <x>_o(void) : Returns the offset for element <x>.
28 *
29 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
30 *
31 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
32 *
33 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
34 * and masked to place it at field <y> of register <x>. This value
35 * can be |'d with others to produce a full register value for
36 * register <x>.
37 *
38 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
39 * value can be ~'d and then &'d to clear the value of field <y> for
40 * register <x>.
41 *
42 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
43 * to place it at field <y> of register <x>. This value can be |'d
44 * with others to produce a full register value for <x>.
45 *
46 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
47 * <x> value 'r' after being shifted to place its LSB at bit 0.
48 * This value is suitable for direct comparison with other unshifted
49 * values appropriate for use in field <y> of register <x>.
50 *
51 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
52 * field <y> of register <x>. This value is suitable for direct
53 * comparison with unshifted values appropriate for use in field <y>
54 * of register <x>.
55 */
56#ifndef _hw_ccsr_gk20a_h_
57#define _hw_ccsr_gk20a_h_
58
59static inline u32 ccsr_channel_inst_r(u32 i)
60{
61 return 0x00800000U + i*8U;
62}
63static inline u32 ccsr_channel_inst__size_1_v(void)
64{
65 return 0x00000080U;
66}
67static inline u32 ccsr_channel_inst_ptr_f(u32 v)
68{
69 return (v & 0xfffffffU) << 0U;
70}
71static inline u32 ccsr_channel_inst_target_vid_mem_f(void)
72{
73 return 0x0U;
74}
75static inline u32 ccsr_channel_inst_target_sys_mem_coh_f(void)
76{
77 return 0x20000000U;
78}
79static inline u32 ccsr_channel_inst_target_sys_mem_ncoh_f(void)
80{
81 return 0x30000000U;
82}
83static inline u32 ccsr_channel_inst_bind_false_f(void)
84{
85 return 0x0U;
86}
87static inline u32 ccsr_channel_inst_bind_true_f(void)
88{
89 return 0x80000000U;
90}
91static inline u32 ccsr_channel_r(u32 i)
92{
93 return 0x00800004U + i*8U;
94}
95static inline u32 ccsr_channel__size_1_v(void)
96{
97 return 0x00000080U;
98}
99static inline u32 ccsr_channel_enable_v(u32 r)
100{
101 return (r >> 0U) & 0x1U;
102}
103static inline u32 ccsr_channel_enable_set_f(u32 v)
104{
105 return (v & 0x1U) << 10U;
106}
107static inline u32 ccsr_channel_enable_set_true_f(void)
108{
109 return 0x400U;
110}
111static inline u32 ccsr_channel_enable_clr_true_f(void)
112{
113 return 0x800U;
114}
115static inline u32 ccsr_channel_runlist_f(u32 v)
116{
117 return (v & 0xfU) << 16U;
118}
119static inline u32 ccsr_channel_status_v(u32 r)
120{
121 return (r >> 24U) & 0xfU;
122}
123static inline u32 ccsr_channel_status_pending_ctx_reload_v(void)
124{
125 return 0x00000002U;
126}
127static inline u32 ccsr_channel_status_pending_acq_ctx_reload_v(void)
128{
129 return 0x00000004U;
130}
131static inline u32 ccsr_channel_status_on_pbdma_ctx_reload_v(void)
132{
133 return 0x0000000aU;
134}
135static inline u32 ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v(void)
136{
137 return 0x0000000bU;
138}
139static inline u32 ccsr_channel_status_on_eng_ctx_reload_v(void)
140{
141 return 0x0000000cU;
142}
143static inline u32 ccsr_channel_status_on_eng_pending_ctx_reload_v(void)
144{
145 return 0x0000000dU;
146}
147static inline u32 ccsr_channel_status_on_eng_pending_acq_ctx_reload_v(void)
148{
149 return 0x0000000eU;
150}
151static inline u32 ccsr_channel_next_v(u32 r)
152{
153 return (r >> 1U) & 0x1U;
154}
155static inline u32 ccsr_channel_next_true_v(void)
156{
157 return 0x00000001U;
158}
159static inline u32 ccsr_channel_busy_v(u32 r)
160{
161 return (r >> 28U) & 0x1U;
162}
163#endif
diff --git a/include/gk20a/hw_ce2_gk20a.h b/include/gk20a/hw_ce2_gk20a.h
deleted file mode 100644
index 87481cd..0000000
--- a/include/gk20a/hw_ce2_gk20a.h
+++ /dev/null
@@ -1,87 +0,0 @@
1/*
2 * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22/*
23 * Function naming determines intended use:
24 *
25 * <x>_r(void) : Returns the offset for register <x>.
26 *
27 * <x>_o(void) : Returns the offset for element <x>.
28 *
29 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
30 *
31 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
32 *
33 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
34 * and masked to place it at field <y> of register <x>. This value
35 * can be |'d with others to produce a full register value for
36 * register <x>.
37 *
38 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
39 * value can be ~'d and then &'d to clear the value of field <y> for
40 * register <x>.
41 *
42 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
43 * to place it at field <y> of register <x>. This value can be |'d
44 * with others to produce a full register value for <x>.
45 *
46 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
47 * <x> value 'r' after being shifted to place its LSB at bit 0.
48 * This value is suitable for direct comparison with other unshifted
49 * values appropriate for use in field <y> of register <x>.
50 *
51 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
52 * field <y> of register <x>. This value is suitable for direct
53 * comparison with unshifted values appropriate for use in field <y>
54 * of register <x>.
55 */
56#ifndef _hw_ce2_gk20a_h_
57#define _hw_ce2_gk20a_h_
58
59static inline u32 ce2_intr_status_r(void)
60{
61 return 0x00106908U;
62}
63static inline u32 ce2_intr_status_blockpipe_pending_f(void)
64{
65 return 0x1U;
66}
67static inline u32 ce2_intr_status_blockpipe_reset_f(void)
68{
69 return 0x1U;
70}
71static inline u32 ce2_intr_status_nonblockpipe_pending_f(void)
72{
73 return 0x2U;
74}
75static inline u32 ce2_intr_status_nonblockpipe_reset_f(void)
76{
77 return 0x2U;
78}
79static inline u32 ce2_intr_status_launcherr_pending_f(void)
80{
81 return 0x4U;
82}
83static inline u32 ce2_intr_status_launcherr_reset_f(void)
84{
85 return 0x4U;
86}
87#endif
diff --git a/include/gk20a/hw_ctxsw_prog_gk20a.h b/include/gk20a/hw_ctxsw_prog_gk20a.h
deleted file mode 100644
index 131fd12..0000000
--- a/include/gk20a/hw_ctxsw_prog_gk20a.h
+++ /dev/null
@@ -1,447 +0,0 @@
1/*
2 * Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22/*
23 * Function naming determines intended use:
24 *
25 * <x>_r(void) : Returns the offset for register <x>.
26 *
27 * <x>_o(void) : Returns the offset for element <x>.
28 *
29 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
30 *
31 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
32 *
33 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
34 * and masked to place it at field <y> of register <x>. This value
35 * can be |'d with others to produce a full register value for
36 * register <x>.
37 *
38 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
39 * value can be ~'d and then &'d to clear the value of field <y> for
40 * register <x>.
41 *
42 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
43 * to place it at field <y> of register <x>. This value can be |'d
44 * with others to produce a full register value for <x>.
45 *
46 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
47 * <x> value 'r' after being shifted to place its LSB at bit 0.
48 * This value is suitable for direct comparison with other unshifted
49 * values appropriate for use in field <y> of register <x>.
50 *
51 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
52 * field <y> of register <x>. This value is suitable for direct
53 * comparison with unshifted values appropriate for use in field <y>
54 * of register <x>.
55 */
56#ifndef _hw_ctxsw_prog_gk20a_h_
57#define _hw_ctxsw_prog_gk20a_h_
58
59static inline u32 ctxsw_prog_fecs_header_v(void)
60{
61 return 0x00000100U;
62}
63static inline u32 ctxsw_prog_main_image_num_gpcs_o(void)
64{
65 return 0x00000008U;
66}
67static inline u32 ctxsw_prog_main_image_patch_count_o(void)
68{
69 return 0x00000010U;
70}
71static inline u32 ctxsw_prog_main_image_context_id_o(void)
72{
73 return 0x000000f0U;
74}
75static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void)
76{
77 return 0x00000014U;
78}
79static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void)
80{
81 return 0x00000018U;
82}
83static inline u32 ctxsw_prog_main_image_zcull_o(void)
84{
85 return 0x0000001cU;
86}
87static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void)
88{
89 return 0x00000001U;
90}
91static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void)
92{
93 return 0x00000002U;
94}
95static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void)
96{
97 return 0x00000020U;
98}
99static inline u32 ctxsw_prog_main_image_pm_o(void)
100{
101 return 0x00000028U;
102}
103static inline u32 ctxsw_prog_main_image_pm_mode_m(void)
104{
105 return 0x7U << 0U;
106}
107static inline u32 ctxsw_prog_main_image_pm_mode_ctxsw_f(void)
108{
109 return 0x1U;
110}
111static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void)
112{
113 return 0x0U;
114}
115static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void)
116{
117 return 0x7U << 3U;
118}
119static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void)
120{
121 return 0x8U;
122}
123static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void)
124{
125 return 0x0U;
126}
127static inline u32 ctxsw_prog_main_image_pm_ptr_o(void)
128{
129 return 0x0000002cU;
130}
131static inline u32 ctxsw_prog_main_image_num_save_ops_o(void)
132{
133 return 0x000000f4U;
134}
135static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void)
136{
137 return 0x000000f8U;
138}
139static inline u32 ctxsw_prog_main_image_magic_value_o(void)
140{
141 return 0x000000fcU;
142}
143static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void)
144{
145 return 0x600dc0deU;
146}
147static inline u32 ctxsw_prog_local_priv_register_ctl_o(void)
148{
149 return 0x0000000cU;
150}
151static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r)
152{
153 return (r >> 0U) & 0xffffU;
154}
155static inline u32 ctxsw_prog_local_image_ppc_info_o(void)
156{
157 return 0x000000f4U;
158}
159static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r)
160{
161 return (r >> 0U) & 0xffffU;
162}
163static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r)
164{
165 return (r >> 16U) & 0xffffU;
166}
167static inline u32 ctxsw_prog_local_image_num_tpcs_o(void)
168{
169 return 0x000000f8U;
170}
171static inline u32 ctxsw_prog_local_magic_value_o(void)
172{
173 return 0x000000fcU;
174}
175static inline u32 ctxsw_prog_local_magic_value_v_value_v(void)
176{
177 return 0xad0becabU;
178}
179static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void)
180{
181 return 0x000000ecU;
182}
183static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r)
184{
185 return (r >> 0U) & 0xffffU;
186}
187static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r)
188{
189 return (r >> 16U) & 0xffU;
190}
191static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void)
192{
193 return 0x00000100U;
194}
195static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void)
196{
197 return 0x00000004U;
198}
199static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void)
200{
201 return 0x00000005U;
202}
203static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void)
204{
205 return 0x00000004U;
206}
207static inline u32 ctxsw_prog_extended_num_smpc_quadrants_v(void)
208{
209 return 0x00000004U;
210}
211static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void)
212{
213 return 0x000000a0U;
214}
215static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void)
216{
217 return 2U;
218}
219static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v)
220{
221 return (v & 0x3U) << 0U;
222}
223static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void)
224{
225 return 0x3U << 0U;
226}
227static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r)
228{
229 return (r >> 0U) & 0x3U;
230}
231static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void)
232{
233 return 0x0U;
234}
235static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void)
236{
237 return 0x2U;
238}
239static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void)
240{
241 return 0x000000a4U;
242}
243static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void)
244{
245 return 0x000000a8U;
246}
247static inline u32 ctxsw_prog_main_image_misc_options_o(void)
248{
249 return 0x0000003cU;
250}
251static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void)
252{
253 return 0x1U << 3U;
254}
255static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void)
256{
257 return 0x0U;
258}
259static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_control_o(void)
260{
261 return 0x000000acU;
262}
263static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_control_num_records_f(u32 v)
264{
265 return (v & 0xffffU) << 0U;
266}
267static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o(void)
268{
269 return 0x000000b0U;
270}
271static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_v_m(void)
272{
273 return 0xfffffffU << 0U;
274}
275static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_m(void)
276{
277 return 0x3U << 28U;
278}
279static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_vid_mem_f(void)
280{
281 return 0x0U;
282}
283static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_coherent_f(void)
284{
285 return 0x20000000U;
286}
287static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_noncoherent_f(void)
288{
289 return 0x30000000U;
290}
291static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_o(void)
292{
293 return 0x000000b4U;
294}
295static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_v_f(u32 v)
296{
297 return (v & 0xffffffffU) << 0U;
298}
299static inline u32 ctxsw_prog_record_timestamp_record_size_in_bytes_v(void)
300{
301 return 0x00000080U;
302}
303static inline u32 ctxsw_prog_record_timestamp_record_size_in_words_v(void)
304{
305 return 0x00000020U;
306}
307static inline u32 ctxsw_prog_record_timestamp_magic_value_lo_o(void)
308{
309 return 0x00000000U;
310}
311static inline u32 ctxsw_prog_record_timestamp_magic_value_lo_v_value_v(void)
312{
313 return 0x00000000U;
314}
315static inline u32 ctxsw_prog_record_timestamp_magic_value_hi_o(void)
316{
317 return 0x00000004U;
318}
319static inline u32 ctxsw_prog_record_timestamp_magic_value_hi_v_value_v(void)
320{
321 return 0x600dbeefU;
322}
323static inline u32 ctxsw_prog_record_timestamp_context_id_o(void)
324{
325 return 0x00000008U;
326}
327static inline u32 ctxsw_prog_record_timestamp_context_ptr_o(void)
328{
329 return 0x0000000cU;
330}
331static inline u32 ctxsw_prog_record_timestamp_new_context_id_o(void)
332{
333 return 0x00000010U;
334}
335static inline u32 ctxsw_prog_record_timestamp_new_context_ptr_o(void)
336{
337 return 0x00000014U;
338}
339static inline u32 ctxsw_prog_record_timestamp_timestamp_lo_o(void)
340{
341 return 0x00000018U;
342}
343static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_o(void)
344{
345 return 0x0000001cU;
346}
347static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_v_f(u32 v)
348{
349 return (v & 0xffffffU) << 0U;
350}
351static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_v_v(u32 r)
352{
353 return (r >> 0U) & 0xffffffU;
354}
355static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_f(u32 v)
356{
357 return (v & 0xffU) << 24U;
358}
359static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_m(void)
360{
361 return 0xffU << 24U;
362}
363static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_v(u32 r)
364{
365 return (r >> 24U) & 0xffU;
366}
367static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_v(void)
368{
369 return 0x00000001U;
370}
371static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_f(void)
372{
373 return 0x1000000U;
374}
375static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_v(void)
376{
377 return 0x00000002U;
378}
379static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_f(void)
380{
381 return 0x2000000U;
382}
383static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_v(void)
384{
385 return 0x0000000aU;
386}
387static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_f(void)
388{
389 return 0xa000000U;
390}
391static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_v(void)
392{
393 return 0x0000000bU;
394}
395static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_f(void)
396{
397 return 0xb000000U;
398}
399static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_v(void)
400{
401 return 0x0000000cU;
402}
403static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_f(void)
404{
405 return 0xc000000U;
406}
407static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_v(void)
408{
409 return 0x0000000dU;
410}
411static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_f(void)
412{
413 return 0xd000000U;
414}
415static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_v(void)
416{
417 return 0x00000003U;
418}
419static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_f(void)
420{
421 return 0x3000000U;
422}
423static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_v(void)
424{
425 return 0x00000004U;
426}
427static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_f(void)
428{
429 return 0x4000000U;
430}
431static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_v(void)
432{
433 return 0x00000005U;
434}
435static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_f(void)
436{
437 return 0x5000000U;
438}
439static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_v(void)
440{
441 return 0x000000ffU;
442}
443static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_f(void)
444{
445 return 0xff000000U;
446}
447#endif
diff --git a/include/gk20a/hw_falcon_gk20a.h b/include/gk20a/hw_falcon_gk20a.h
deleted file mode 100644
index 7b4d87b..0000000
--- a/include/gk20a/hw_falcon_gk20a.h
+++ /dev/null
@@ -1,559 +0,0 @@
1/*
2 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22/*
23 * Function naming determines intended use:
24 *
25 * <x>_r(void) : Returns the offset for register <x>.
26 *
27 * <x>_o(void) : Returns the offset for element <x>.
28 *
29 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
30 *
31 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
32 *
33 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
34 * and masked to place it at field <y> of register <x>. This value
35 * can be |'d with others to produce a full register value for
36 * register <x>.
37 *
38 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
39 * value can be ~'d and then &'d to clear the value of field <y> for
40 * register <x>.
41 *
42 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
43 * to place it at field <y> of register <x>. This value can be |'d
44 * with others to produce a full register value for <x>.
45 *
46 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
47 * <x> value 'r' after being shifted to place its LSB at bit 0.
48 * This value is suitable for direct comparison with other unshifted
49 * values appropriate for use in field <y> of register <x>.
50 *
51 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
52 * field <y> of register <x>. This value is suitable for direct
53 * comparison with unshifted values appropriate for use in field <y>
54 * of register <x>.
55 */
56#ifndef _hw_falcon_gk20a_h_
57#define _hw_falcon_gk20a_h_
58
59static inline u32 falcon_falcon_irqsset_r(void)
60{
61 return 0x00000000U;
62}
63static inline u32 falcon_falcon_irqsset_swgen0_set_f(void)
64{
65 return 0x40U;
66}
67static inline u32 falcon_falcon_irqsclr_r(void)
68{
69 return 0x00000004U;
70}
71static inline u32 falcon_falcon_irqstat_r(void)
72{
73 return 0x00000008U;
74}
75static inline u32 falcon_falcon_irqstat_halt_true_f(void)
76{
77 return 0x10U;
78}
79static inline u32 falcon_falcon_irqstat_exterr_true_f(void)
80{
81 return 0x20U;
82}
83static inline u32 falcon_falcon_irqstat_swgen0_true_f(void)
84{
85 return 0x40U;
86}
87static inline u32 falcon_falcon_irqmode_r(void)
88{
89 return 0x0000000cU;
90}
91static inline u32 falcon_falcon_irqmset_r(void)
92{
93 return 0x00000010U;
94}
95static inline u32 falcon_falcon_irqmset_gptmr_f(u32 v)
96{
97 return (v & 0x1U) << 0U;
98}
99static inline u32 falcon_falcon_irqmset_wdtmr_f(u32 v)
100{
101 return (v & 0x1U) << 1U;
102}
103static inline u32 falcon_falcon_irqmset_mthd_f(u32 v)
104{
105 return (v & 0x1U) << 2U;
106}
107static inline u32 falcon_falcon_irqmset_ctxsw_f(u32 v)
108{
109 return (v & 0x1U) << 3U;
110}
111static inline u32 falcon_falcon_irqmset_halt_f(u32 v)
112{
113 return (v & 0x1U) << 4U;
114}
115static inline u32 falcon_falcon_irqmset_exterr_f(u32 v)
116{
117 return (v & 0x1U) << 5U;
118}
119static inline u32 falcon_falcon_irqmset_swgen0_f(u32 v)
120{
121 return (v & 0x1U) << 6U;
122}
123static inline u32 falcon_falcon_irqmset_swgen1_f(u32 v)
124{
125 return (v & 0x1U) << 7U;
126}
127static inline u32 falcon_falcon_irqmclr_r(void)
128{
129 return 0x00000014U;
130}
131static inline u32 falcon_falcon_irqmclr_gptmr_f(u32 v)
132{
133 return (v & 0x1U) << 0U;
134}
135static inline u32 falcon_falcon_irqmclr_wdtmr_f(u32 v)
136{
137 return (v & 0x1U) << 1U;
138}
139static inline u32 falcon_falcon_irqmclr_mthd_f(u32 v)
140{
141 return (v & 0x1U) << 2U;
142}
143static inline u32 falcon_falcon_irqmclr_ctxsw_f(u32 v)
144{
145 return (v & 0x1U) << 3U;
146}
147static inline u32 falcon_falcon_irqmclr_halt_f(u32 v)
148{
149 return (v & 0x1U) << 4U;
150}
151static inline u32 falcon_falcon_irqmclr_exterr_f(u32 v)
152{
153 return (v & 0x1U) << 5U;
154}
155static inline u32 falcon_falcon_irqmclr_swgen0_f(u32 v)
156{
157 return (v & 0x1U) << 6U;
158}
159static inline u32 falcon_falcon_irqmclr_swgen1_f(u32 v)
160{
161 return (v & 0x1U) << 7U;
162}
163static inline u32 falcon_falcon_irqmclr_ext_f(u32 v)
164{
165 return (v & 0xffU) << 8U;
166}
167static inline u32 falcon_falcon_irqmask_r(void)
168{
169 return 0x00000018U;
170}
171static inline u32 falcon_falcon_irqdest_r(void)
172{
173 return 0x0000001cU;
174}
175static inline u32 falcon_falcon_irqdest_host_gptmr_f(u32 v)
176{
177 return (v & 0x1U) << 0U;
178}
179static inline u32 falcon_falcon_irqdest_host_wdtmr_f(u32 v)
180{
181 return (v & 0x1U) << 1U;
182}
183static inline u32 falcon_falcon_irqdest_host_mthd_f(u32 v)
184{
185 return (v & 0x1U) << 2U;
186}
187static inline u32 falcon_falcon_irqdest_host_ctxsw_f(u32 v)
188{
189 return (v & 0x1U) << 3U;
190}
191static inline u32 falcon_falcon_irqdest_host_halt_f(u32 v)
192{
193 return (v & 0x1U) << 4U;
194}
195static inline u32 falcon_falcon_irqdest_host_exterr_f(u32 v)
196{
197 return (v & 0x1U) << 5U;
198}
199static inline u32 falcon_falcon_irqdest_host_swgen0_f(u32 v)
200{
201 return (v & 0x1U) << 6U;
202}
203static inline u32 falcon_falcon_irqdest_host_swgen1_f(u32 v)
204{
205 return (v & 0x1U) << 7U;
206}
207static inline u32 falcon_falcon_irqdest_host_ext_f(u32 v)
208{
209 return (v & 0xffU) << 8U;
210}
211static inline u32 falcon_falcon_irqdest_target_gptmr_f(u32 v)
212{
213 return (v & 0x1U) << 16U;
214}
215static inline u32 falcon_falcon_irqdest_target_wdtmr_f(u32 v)
216{
217 return (v & 0x1U) << 17U;
218}
219static inline u32 falcon_falcon_irqdest_target_mthd_f(u32 v)
220{
221 return (v & 0x1U) << 18U;
222}
223static inline u32 falcon_falcon_irqdest_target_ctxsw_f(u32 v)
224{
225 return (v & 0x1U) << 19U;
226}
227static inline u32 falcon_falcon_irqdest_target_halt_f(u32 v)
228{
229 return (v & 0x1U) << 20U;
230}
231static inline u32 falcon_falcon_irqdest_target_exterr_f(u32 v)
232{
233 return (v & 0x1U) << 21U;
234}
235static inline u32 falcon_falcon_irqdest_target_swgen0_f(u32 v)
236{
237 return (v & 0x1U) << 22U;
238}
239static inline u32 falcon_falcon_irqdest_target_swgen1_f(u32 v)
240{
241 return (v & 0x1U) << 23U;
242}
243static inline u32 falcon_falcon_irqdest_target_ext_f(u32 v)
244{
245 return (v & 0xffU) << 24U;
246}
247static inline u32 falcon_falcon_curctx_r(void)
248{
249 return 0x00000050U;
250}
251static inline u32 falcon_falcon_nxtctx_r(void)
252{
253 return 0x00000054U;
254}
255static inline u32 falcon_falcon_mailbox0_r(void)
256{
257 return 0x00000040U;
258}
259static inline u32 falcon_falcon_mailbox1_r(void)
260{
261 return 0x00000044U;
262}
263static inline u32 falcon_falcon_itfen_r(void)
264{
265 return 0x00000048U;
266}
267static inline u32 falcon_falcon_itfen_ctxen_enable_f(void)
268{
269 return 0x1U;
270}
271static inline u32 falcon_falcon_idlestate_r(void)
272{
273 return 0x0000004cU;
274}
275static inline u32 falcon_falcon_idlestate_falcon_busy_v(u32 r)
276{
277 return (r >> 0U) & 0x1U;
278}
279static inline u32 falcon_falcon_idlestate_ext_busy_v(u32 r)
280{
281 return (r >> 1U) & 0x7fffU;
282}
283static inline u32 falcon_falcon_os_r(void)
284{
285 return 0x00000080U;
286}
287static inline u32 falcon_falcon_engctl_r(void)
288{
289 return 0x000000a4U;
290}
291static inline u32 falcon_falcon_cpuctl_r(void)
292{
293 return 0x00000100U;
294}
295static inline u32 falcon_falcon_cpuctl_startcpu_f(u32 v)
296{
297 return (v & 0x1U) << 1U;
298}
299static inline u32 falcon_falcon_cpuctl_sreset_f(u32 v)
300{
301 return (v & 0x1U) << 2U;
302}
303static inline u32 falcon_falcon_cpuctl_hreset_f(u32 v)
304{
305 return (v & 0x1U) << 3U;
306}
307static inline u32 falcon_falcon_cpuctl_halt_intr_f(u32 v)
308{
309 return (v & 0x1U) << 4U;
310}
311static inline u32 falcon_falcon_cpuctl_halt_intr_m(void)
312{
313 return 0x1U << 4U;
314}
315static inline u32 falcon_falcon_cpuctl_halt_intr_v(u32 r)
316{
317 return (r >> 4U) & 0x1U;
318}
319static inline u32 falcon_falcon_cpuctl_stopped_m(void)
320{
321 return 0x1U << 5U;
322}
323static inline u32 falcon_falcon_imemc_r(u32 i)
324{
325 return 0x00000180U + i*16U;
326}
327static inline u32 falcon_falcon_imemc_offs_f(u32 v)
328{
329 return (v & 0x3fU) << 2U;
330}
331static inline u32 falcon_falcon_imemc_blk_f(u32 v)
332{
333 return (v & 0xffU) << 8U;
334}
335static inline u32 falcon_falcon_imemc_aincw_f(u32 v)
336{
337 return (v & 0x1U) << 24U;
338}
339static inline u32 falcon_falcon_imemc_secure_f(u32 v)
340{
341 return (v & 0x1U) << 28U;
342}
343static inline u32 falcon_falcon_imemd_r(u32 i)
344{
345 return 0x00000184U + i*16U;
346}
347static inline u32 falcon_falcon_imemt_r(u32 i)
348{
349 return 0x00000188U + i*16U;
350}
351static inline u32 falcon_falcon_bootvec_r(void)
352{
353 return 0x00000104U;
354}
355static inline u32 falcon_falcon_bootvec_vec_f(u32 v)
356{
357 return (v & 0xffffffffU) << 0U;
358}
359static inline u32 falcon_falcon_dmactl_r(void)
360{
361 return 0x0000010cU;
362}
363static inline u32 falcon_falcon_dmactl_dmem_scrubbing_m(void)
364{
365 return 0x1U << 1U;
366}
367static inline u32 falcon_falcon_dmactl_imem_scrubbing_m(void)
368{
369 return 0x1U << 2U;
370}
371static inline u32 falcon_falcon_dmactl_require_ctx_f(u32 v)
372{
373 return (v & 0x1U) << 0U;
374}
375static inline u32 falcon_falcon_hwcfg_r(void)
376{
377 return 0x00000108U;
378}
379static inline u32 falcon_falcon_hwcfg_imem_size_v(u32 r)
380{
381 return (r >> 0U) & 0x1ffU;
382}
383static inline u32 falcon_falcon_hwcfg_dmem_size_v(u32 r)
384{
385 return (r >> 9U) & 0x1ffU;
386}
387static inline u32 falcon_falcon_dmatrfbase_r(void)
388{
389 return 0x00000110U;
390}
391static inline u32 falcon_falcon_dmatrfmoffs_r(void)
392{
393 return 0x00000114U;
394}
395static inline u32 falcon_falcon_dmatrfcmd_r(void)
396{
397 return 0x00000118U;
398}
399static inline u32 falcon_falcon_dmatrfcmd_imem_f(u32 v)
400{
401 return (v & 0x1U) << 4U;
402}
403static inline u32 falcon_falcon_dmatrfcmd_write_f(u32 v)
404{
405 return (v & 0x1U) << 5U;
406}
407static inline u32 falcon_falcon_dmatrfcmd_size_f(u32 v)
408{
409 return (v & 0x7U) << 8U;
410}
411static inline u32 falcon_falcon_dmatrfcmd_ctxdma_f(u32 v)
412{
413 return (v & 0x7U) << 12U;
414}
415static inline u32 falcon_falcon_dmatrffboffs_r(void)
416{
417 return 0x0000011cU;
418}
419static inline u32 falcon_falcon_imstat_r(void)
420{
421 return 0x00000144U;
422}
423static inline u32 falcon_falcon_traceidx_r(void)
424{
425 return 0x00000148U;
426}
427static inline u32 falcon_falcon_traceidx_maxidx_v(u32 r)
428{
429 return (r >> 16U) & 0xffU;
430}
431static inline u32 falcon_falcon_traceidx_idx_v(u32 r)
432{
433 return (r >> 0U) & 0xffU;
434}
435static inline u32 falcon_falcon_tracepc_r(void)
436{
437 return 0x0000014cU;
438}
439static inline u32 falcon_falcon_tracepc_pc_v(u32 r)
440{
441 return (r >> 0U) & 0xffffffU;
442}
443static inline u32 falcon_falcon_exterraddr_r(void)
444{
445 return 0x00000168U;
446}
447static inline u32 falcon_falcon_exterrstat_r(void)
448{
449 return 0x0000016cU;
450}
451static inline u32 falcon_falcon_exterrstat_valid_m(void)
452{
453 return 0x1U << 31U;
454}
455static inline u32 falcon_falcon_exterrstat_valid_v(u32 r)
456{
457 return (r >> 31U) & 0x1U;
458}
459static inline u32 falcon_falcon_exterrstat_valid_true_v(void)
460{
461 return 0x00000001U;
462}
463static inline u32 falcon_falcon_icd_cmd_r(void)
464{
465 return 0x00000200U;
466}
467static inline u32 falcon_falcon_icd_cmd_opc_s(void)
468{
469 return 4U;
470}
471static inline u32 falcon_falcon_icd_cmd_opc_f(u32 v)
472{
473 return (v & 0xfU) << 0U;
474}
475static inline u32 falcon_falcon_icd_cmd_opc_m(void)
476{
477 return 0xfU << 0U;
478}
479static inline u32 falcon_falcon_icd_cmd_opc_v(u32 r)
480{
481 return (r >> 0U) & 0xfU;
482}
483static inline u32 falcon_falcon_icd_cmd_opc_rreg_f(void)
484{
485 return 0x8U;
486}
487static inline u32 falcon_falcon_icd_cmd_opc_rstat_f(void)
488{
489 return 0xeU;
490}
491static inline u32 falcon_falcon_icd_cmd_idx_f(u32 v)
492{
493 return (v & 0x1fU) << 8U;
494}
495static inline u32 falcon_falcon_icd_rdata_r(void)
496{
497 return 0x0000020cU;
498}
499static inline u32 falcon_falcon_dmemc_r(u32 i)
500{
501 return 0x000001c0U + i*8U;
502}
503static inline u32 falcon_falcon_dmemc_offs_f(u32 v)
504{
505 return (v & 0x3fU) << 2U;
506}
507static inline u32 falcon_falcon_dmemc_offs_m(void)
508{
509 return 0x3fU << 2U;
510}
511static inline u32 falcon_falcon_dmemc_blk_f(u32 v)
512{
513 return (v & 0xffU) << 8U;
514}
515static inline u32 falcon_falcon_dmemc_blk_m(void)
516{
517 return 0xffU << 8U;
518}
519static inline u32 falcon_falcon_dmemc_aincw_f(u32 v)
520{
521 return (v & 0x1U) << 24U;
522}
523static inline u32 falcon_falcon_dmemc_aincr_f(u32 v)
524{
525 return (v & 0x1U) << 25U;
526}
527static inline u32 falcon_falcon_dmemd_r(u32 i)
528{
529 return 0x000001c4U + i*8U;
530}
531static inline u32 falcon_falcon_debug1_r(void)
532{
533 return 0x00000090U;
534}
535static inline u32 falcon_falcon_debug1_ctxsw_mode_s(void)
536{
537 return 1U;
538}
539static inline u32 falcon_falcon_debug1_ctxsw_mode_f(u32 v)
540{
541 return (v & 0x1U) << 16U;
542}
543static inline u32 falcon_falcon_debug1_ctxsw_mode_m(void)
544{
545 return 0x1U << 16U;
546}
547static inline u32 falcon_falcon_debug1_ctxsw_mode_v(u32 r)
548{
549 return (r >> 16U) & 0x1U;
550}
551static inline u32 falcon_falcon_debug1_ctxsw_mode_init_f(void)
552{
553 return 0x0U;
554}
555static inline u32 falcon_falcon_debuginfo_r(void)
556{
557 return 0x00000094U;
558}
559#endif
diff --git a/include/gk20a/hw_fb_gk20a.h b/include/gk20a/hw_fb_gk20a.h
deleted file mode 100644
index 42df4f5..0000000
--- a/include/gk20a/hw_fb_gk20a.h
+++ /dev/null
@@ -1,263 +0,0 @@
1/*
2 * Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22/*
23 * Function naming determines intended use:
24 *
25 * <x>_r(void) : Returns the offset for register <x>.
26 *
27 * <x>_o(void) : Returns the offset for element <x>.
28 *
29 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
30 *
31 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
32 *
33 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
34 * and masked to place it at field <y> of register <x>. This value
35 * can be |'d with others to produce a full register value for
36 * register <x>.
37 *
38 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
39 * value can be ~'d and then &'d to clear the value of field <y> for
40 * register <x>.
41 *
42 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
43 * to place it at field <y> of register <x>. This value can be |'d
44 * with others to produce a full register value for <x>.
45 *
46 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
47 * <x> value 'r' after being shifted to place its LSB at bit 0.
48 * This value is suitable for direct comparison with other unshifted
49 * values appropriate for use in field <y> of register <x>.
50 *
51 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
52 * field <y> of register <x>. This value is suitable for direct
53 * comparison with unshifted values appropriate for use in field <y>
54 * of register <x>.
55 */
56#ifndef _hw_fb_gk20a_h_
57#define _hw_fb_gk20a_h_
58
59static inline u32 fb_mmu_ctrl_r(void)
60{
61 return 0x00100c80U;
62}
63static inline u32 fb_mmu_ctrl_vm_pg_size_f(u32 v)
64{
65 return (v & 0x1U) << 0U;
66}
67static inline u32 fb_mmu_ctrl_vm_pg_size_128kb_f(void)
68{
69 return 0x0U;
70}
71static inline u32 fb_mmu_ctrl_vm_pg_size_64kb_f(void)
72{
73 return 0x1U;
74}
75static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r)
76{
77 return (r >> 15U) & 0x1U;
78}
79static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void)
80{
81 return 0x0U;
82}
83static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r)
84{
85 return (r >> 16U) & 0xffU;
86}
87static inline u32 fb_mmu_invalidate_pdb_r(void)
88{
89 return 0x00100cb8U;
90}
91static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void)
92{
93 return 0x0U;
94}
95static inline u32 fb_mmu_invalidate_pdb_aperture_sys_mem_f(void)
96{
97 return 0x2U;
98}
99static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v)
100{
101 return (v & 0xfffffffU) << 4U;
102}
103static inline u32 fb_mmu_invalidate_r(void)
104{
105 return 0x00100cbcU;
106}
107static inline u32 fb_mmu_invalidate_all_va_true_f(void)
108{
109 return 0x1U;
110}
111static inline u32 fb_mmu_invalidate_all_pdb_true_f(void)
112{
113 return 0x2U;
114}
115static inline u32 fb_mmu_invalidate_trigger_s(void)
116{
117 return 1U;
118}
119static inline u32 fb_mmu_invalidate_trigger_f(u32 v)
120{
121 return (v & 0x1U) << 31U;
122}
123static inline u32 fb_mmu_invalidate_trigger_m(void)
124{
125 return 0x1U << 31U;
126}
127static inline u32 fb_mmu_invalidate_trigger_v(u32 r)
128{
129 return (r >> 31U) & 0x1U;
130}
131static inline u32 fb_mmu_invalidate_trigger_true_f(void)
132{
133 return 0x80000000U;
134}
135static inline u32 fb_mmu_debug_wr_r(void)
136{
137 return 0x00100cc8U;
138}
139static inline u32 fb_mmu_debug_wr_aperture_s(void)
140{
141 return 2U;
142}
143static inline u32 fb_mmu_debug_wr_aperture_f(u32 v)
144{
145 return (v & 0x3U) << 0U;
146}
147static inline u32 fb_mmu_debug_wr_aperture_m(void)
148{
149 return 0x3U << 0U;
150}
151static inline u32 fb_mmu_debug_wr_aperture_v(u32 r)
152{
153 return (r >> 0U) & 0x3U;
154}
155static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void)
156{
157 return 0x0U;
158}
159static inline u32 fb_mmu_debug_wr_aperture_sys_mem_coh_f(void)
160{
161 return 0x2U;
162}
163static inline u32 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(void)
164{
165 return 0x3U;
166}
167static inline u32 fb_mmu_debug_wr_vol_false_f(void)
168{
169 return 0x0U;
170}
171static inline u32 fb_mmu_debug_wr_vol_true_v(void)
172{
173 return 0x00000001U;
174}
175static inline u32 fb_mmu_debug_wr_vol_true_f(void)
176{
177 return 0x4U;
178}
179static inline u32 fb_mmu_debug_wr_addr_f(u32 v)
180{
181 return (v & 0xfffffffU) << 4U;
182}
183static inline u32 fb_mmu_debug_wr_addr_alignment_v(void)
184{
185 return 0x0000000cU;
186}
187static inline u32 fb_mmu_debug_rd_r(void)
188{
189 return 0x00100cccU;
190}
191static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void)
192{
193 return 0x0U;
194}
195static inline u32 fb_mmu_debug_rd_aperture_sys_mem_coh_f(void)
196{
197 return 0x2U;
198}
199static inline u32 fb_mmu_debug_rd_aperture_sys_mem_ncoh_f(void)
200{
201 return 0x3U;
202}
203static inline u32 fb_mmu_debug_rd_vol_false_f(void)
204{
205 return 0x0U;
206}
207static inline u32 fb_mmu_debug_rd_addr_f(u32 v)
208{
209 return (v & 0xfffffffU) << 4U;
210}
211static inline u32 fb_mmu_debug_rd_addr_alignment_v(void)
212{
213 return 0x0000000cU;
214}
215static inline u32 fb_mmu_debug_ctrl_r(void)
216{
217 return 0x00100cc4U;
218}
219static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r)
220{
221 return (r >> 16U) & 0x1U;
222}
223static inline u32 fb_mmu_debug_ctrl_debug_m(void)
224{
225 return 0x1U << 16U;
226}
227static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void)
228{
229 return 0x00000001U;
230}
231static inline u32 fb_mmu_debug_ctrl_debug_enabled_f(void)
232{
233 return 0x10000U;
234}
235static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void)
236{
237 return 0x00000000U;
238}
239static inline u32 fb_mmu_debug_ctrl_debug_disabled_f(void)
240{
241 return 0x0U;
242}
243static inline u32 fb_mmu_vpr_info_r(void)
244{
245 return 0x00100cd0U;
246}
247static inline u32 fb_mmu_vpr_info_fetch_v(u32 r)
248{
249 return (r >> 2U) & 0x1U;
250}
251static inline u32 fb_mmu_vpr_info_fetch_false_v(void)
252{
253 return 0x00000000U;
254}
255static inline u32 fb_mmu_vpr_info_fetch_true_v(void)
256{
257 return 0x00000001U;
258}
259static inline u32 fb_niso_flush_sysmem_addr_r(void)
260{
261 return 0x00100c10U;
262}
263#endif
diff --git a/include/gk20a/hw_fifo_gk20a.h b/include/gk20a/hw_fifo_gk20a.h
deleted file mode 100644
index e61e386..0000000
--- a/include/gk20a/hw_fifo_gk20a.h
+++ /dev/null
@@ -1,619 +0,0 @@
1/*
2 * Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22/*
23 * Function naming determines intended use:
24 *
25 * <x>_r(void) : Returns the offset for register <x>.
26 *
27 * <x>_o(void) : Returns the offset for element <x>.
28 *
29 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
30 *
31 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
32 *
33 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
34 * and masked to place it at field <y> of register <x>. This value
35 * can be |'d with others to produce a full register value for
36 * register <x>.
37 *
38 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
39 * value can be ~'d and then &'d to clear the value of field <y> for
40 * register <x>.
41 *
42 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
43 * to place it at field <y> of register <x>. This value can be |'d
44 * with others to produce a full register value for <x>.
45 *
46 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
47 * <x> value 'r' after being shifted to place its LSB at bit 0.
48 * This value is suitable for direct comparison with other unshifted
49 * values appropriate for use in field <y> of register <x>.
50 *
51 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
52 * field <y> of register <x>. This value is suitable for direct
53 * comparison with unshifted values appropriate for use in field <y>
54 * of register <x>.
55 */
56#ifndef _hw_fifo_gk20a_h_
57#define _hw_fifo_gk20a_h_
58
59static inline u32 fifo_bar1_base_r(void)
60{
61 return 0x00002254U;
62}
63static inline u32 fifo_bar1_base_ptr_f(u32 v)
64{
65 return (v & 0xfffffffU) << 0U;
66}
67static inline u32 fifo_bar1_base_ptr_align_shift_v(void)
68{
69 return 0x0000000cU;
70}
71static inline u32 fifo_bar1_base_valid_false_f(void)
72{
73 return 0x0U;
74}
75static inline u32 fifo_bar1_base_valid_true_f(void)
76{
77 return 0x10000000U;
78}
79static inline u32 fifo_runlist_base_r(void)
80{
81 return 0x00002270U;
82}
83static inline u32 fifo_runlist_base_ptr_f(u32 v)
84{
85 return (v & 0xfffffffU) << 0U;
86}
87static inline u32 fifo_runlist_base_target_vid_mem_f(void)
88{
89 return 0x0U;
90}
91static inline u32 fifo_runlist_base_target_sys_mem_coh_f(void)
92{
93 return 0x20000000U;
94}
95static inline u32 fifo_runlist_base_target_sys_mem_ncoh_f(void)
96{
97 return 0x30000000U;
98}
99static inline u32 fifo_runlist_r(void)
100{
101 return 0x00002274U;
102}
103static inline u32 fifo_runlist_engine_f(u32 v)
104{
105 return (v & 0xfU) << 20U;
106}
107static inline u32 fifo_eng_runlist_base_r(u32 i)
108{
109 return 0x00002280U + i*8U;
110}
111static inline u32 fifo_eng_runlist_base__size_1_v(void)
112{
113 return 0x00000001U;
114}
115static inline u32 fifo_eng_runlist_r(u32 i)
116{
117 return 0x00002284U + i*8U;
118}
119static inline u32 fifo_eng_runlist__size_1_v(void)
120{
121 return 0x00000001U;
122}
123static inline u32 fifo_eng_runlist_length_f(u32 v)
124{
125 return (v & 0xffffU) << 0U;
126}
127static inline u32 fifo_eng_runlist_length_max_v(void)
128{
129 return 0x0000ffffU;
130}
131static inline u32 fifo_eng_runlist_pending_true_f(void)
132{
133 return 0x100000U;
134}
135static inline u32 fifo_runlist_timeslice_r(u32 i)
136{
137 return 0x00002310U + i*4U;
138}
139static inline u32 fifo_runlist_timeslice_timeout_128_f(void)
140{
141 return 0x80U;
142}
143static inline u32 fifo_runlist_timeslice_timescale_3_f(void)
144{
145 return 0x3000U;
146}
147static inline u32 fifo_runlist_timeslice_enable_true_f(void)
148{
149 return 0x10000000U;
150}
151static inline u32 fifo_eng_timeout_r(void)
152{
153 return 0x00002a0cU;
154}
155static inline u32 fifo_eng_timeout_period_max_f(void)
156{
157 return 0x7fffffffU;
158}
159static inline u32 fifo_eng_timeout_detection_enabled_f(void)
160{
161 return 0x80000000U;
162}
163static inline u32 fifo_eng_timeout_detection_disabled_f(void)
164{
165 return 0x0U;
166}
167static inline u32 fifo_pb_timeslice_r(u32 i)
168{
169 return 0x00002350U + i*4U;
170}
171static inline u32 fifo_pb_timeslice_timeout_16_f(void)
172{
173 return 0x10U;
174}
175static inline u32 fifo_pb_timeslice_timescale_0_f(void)
176{
177 return 0x0U;
178}
179static inline u32 fifo_pb_timeslice_enable_true_f(void)
180{
181 return 0x10000000U;
182}
183static inline u32 fifo_pbdma_map_r(u32 i)
184{
185 return 0x00002390U + i*4U;
186}
187static inline u32 fifo_intr_0_r(void)
188{
189 return 0x00002100U;
190}
191static inline u32 fifo_intr_0_bind_error_pending_f(void)
192{
193 return 0x1U;
194}
195static inline u32 fifo_intr_0_bind_error_reset_f(void)
196{
197 return 0x1U;
198}
199static inline u32 fifo_intr_0_pio_error_pending_f(void)
200{
201 return 0x10U;
202}
203static inline u32 fifo_intr_0_pio_error_reset_f(void)
204{
205 return 0x10U;
206}
207static inline u32 fifo_intr_0_sched_error_pending_f(void)
208{
209 return 0x100U;
210}
211static inline u32 fifo_intr_0_sched_error_reset_f(void)
212{
213 return 0x100U;
214}
215static inline u32 fifo_intr_0_chsw_error_pending_f(void)
216{
217 return 0x10000U;
218}
219static inline u32 fifo_intr_0_chsw_error_reset_f(void)
220{
221 return 0x10000U;
222}
223static inline u32 fifo_intr_0_fb_flush_timeout_pending_f(void)
224{
225 return 0x800000U;
226}
227static inline u32 fifo_intr_0_fb_flush_timeout_reset_f(void)
228{
229 return 0x800000U;
230}
231static inline u32 fifo_intr_0_lb_error_pending_f(void)
232{
233 return 0x1000000U;
234}
235static inline u32 fifo_intr_0_lb_error_reset_f(void)
236{
237 return 0x1000000U;
238}
239static inline u32 fifo_intr_0_dropped_mmu_fault_pending_f(void)
240{
241 return 0x8000000U;
242}
243static inline u32 fifo_intr_0_dropped_mmu_fault_reset_f(void)
244{
245 return 0x8000000U;
246}
247static inline u32 fifo_intr_0_mmu_fault_pending_f(void)
248{
249 return 0x10000000U;
250}
251static inline u32 fifo_intr_0_pbdma_intr_pending_f(void)
252{
253 return 0x20000000U;
254}
255static inline u32 fifo_intr_0_runlist_event_pending_f(void)
256{
257 return 0x40000000U;
258}
259static inline u32 fifo_intr_0_channel_intr_pending_f(void)
260{
261 return 0x80000000U;
262}
263static inline u32 fifo_intr_en_0_r(void)
264{
265 return 0x00002140U;
266}
267static inline u32 fifo_intr_en_0_sched_error_f(u32 v)
268{
269 return (v & 0x1U) << 8U;
270}
271static inline u32 fifo_intr_en_0_sched_error_m(void)
272{
273 return 0x1U << 8U;
274}
275static inline u32 fifo_intr_en_0_mmu_fault_f(u32 v)
276{
277 return (v & 0x1U) << 28U;
278}
279static inline u32 fifo_intr_en_0_mmu_fault_m(void)
280{
281 return 0x1U << 28U;
282}
283static inline u32 fifo_intr_en_1_r(void)
284{
285 return 0x00002528U;
286}
287static inline u32 fifo_intr_bind_error_r(void)
288{
289 return 0x0000252cU;
290}
291static inline u32 fifo_intr_sched_error_r(void)
292{
293 return 0x0000254cU;
294}
295static inline u32 fifo_intr_sched_error_code_f(u32 v)
296{
297 return (v & 0xffU) << 0U;
298}
299static inline u32 fifo_intr_sched_error_code_ctxsw_timeout_v(void)
300{
301 return 0x0000000aU;
302}
303static inline u32 fifo_intr_chsw_error_r(void)
304{
305 return 0x0000256cU;
306}
307static inline u32 fifo_intr_mmu_fault_id_r(void)
308{
309 return 0x0000259cU;
310}
311static inline u32 fifo_intr_mmu_fault_eng_id_graphics_v(void)
312{
313 return 0x00000000U;
314}
315static inline u32 fifo_intr_mmu_fault_eng_id_graphics_f(void)
316{
317 return 0x0U;
318}
319static inline u32 fifo_intr_mmu_fault_inst_r(u32 i)
320{
321 return 0x00002800U + i*16U;
322}
323static inline u32 fifo_intr_mmu_fault_inst_ptr_v(u32 r)
324{
325 return (r >> 0U) & 0xfffffffU;
326}
327static inline u32 fifo_intr_mmu_fault_inst_ptr_align_shift_v(void)
328{
329 return 0x0000000cU;
330}
331static inline u32 fifo_intr_mmu_fault_lo_r(u32 i)
332{
333 return 0x00002804U + i*16U;
334}
335static inline u32 fifo_intr_mmu_fault_hi_r(u32 i)
336{
337 return 0x00002808U + i*16U;
338}
339static inline u32 fifo_intr_mmu_fault_info_r(u32 i)
340{
341 return 0x0000280cU + i*16U;
342}
343static inline u32 fifo_intr_mmu_fault_info_type_v(u32 r)
344{
345 return (r >> 0U) & 0xfU;
346}
347static inline u32 fifo_intr_mmu_fault_info_write_v(u32 r)
348{
349 return (r >> 7U) & 0x1U;
350}
351static inline u32 fifo_intr_mmu_fault_info_engine_subid_v(u32 r)
352{
353 return (r >> 6U) & 0x1U;
354}
355static inline u32 fifo_intr_mmu_fault_info_engine_subid_gpc_v(void)
356{
357 return 0x00000000U;
358}
359static inline u32 fifo_intr_mmu_fault_info_engine_subid_hub_v(void)
360{
361 return 0x00000001U;
362}
363static inline u32 fifo_intr_mmu_fault_info_client_v(u32 r)
364{
365 return (r >> 8U) & 0x1fU;
366}
367static inline u32 fifo_intr_pbdma_id_r(void)
368{
369 return 0x000025a0U;
370}
371static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i)
372{
373 return (v & 0x1U) << (0U + i*1U);
374}
375static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i)
376{
377 return (r >> (0U + i*1U)) & 0x1U;
378}
379static inline u32 fifo_intr_pbdma_id_status__size_1_v(void)
380{
381 return 0x00000001U;
382}
383static inline u32 fifo_intr_runlist_r(void)
384{
385 return 0x00002a00U;
386}
387static inline u32 fifo_fb_timeout_r(void)
388{
389 return 0x00002a04U;
390}
391static inline u32 fifo_fb_timeout_period_m(void)
392{
393 return 0x3fffffffU << 0U;
394}
395static inline u32 fifo_fb_timeout_period_max_f(void)
396{
397 return 0x3fffffffU;
398}
399static inline u32 fifo_pb_timeout_r(void)
400{
401 return 0x00002a08U;
402}
403static inline u32 fifo_pb_timeout_detection_enabled_f(void)
404{
405 return 0x80000000U;
406}
407static inline u32 fifo_error_sched_disable_r(void)
408{
409 return 0x0000262cU;
410}
411static inline u32 fifo_sched_disable_r(void)
412{
413 return 0x00002630U;
414}
415static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i)
416{
417 return (v & 0x1U) << (0U + i*1U);
418}
419static inline u32 fifo_sched_disable_runlist_m(u32 i)
420{
421 return 0x1U << (0U + i*1U);
422}
423static inline u32 fifo_sched_disable_true_v(void)
424{
425 return 0x00000001U;
426}
427static inline u32 fifo_preempt_r(void)
428{
429 return 0x00002634U;
430}
431static inline u32 fifo_preempt_pending_true_f(void)
432{
433 return 0x100000U;
434}
435static inline u32 fifo_preempt_type_channel_f(void)
436{
437 return 0x0U;
438}
439static inline u32 fifo_preempt_type_tsg_f(void)
440{
441 return 0x1000000U;
442}
443static inline u32 fifo_preempt_chid_f(u32 v)
444{
445 return (v & 0xfffU) << 0U;
446}
447static inline u32 fifo_preempt_id_f(u32 v)
448{
449 return (v & 0xfffU) << 0U;
450}
451static inline u32 fifo_trigger_mmu_fault_r(u32 i)
452{
453 return 0x00002a30U + i*4U;
454}
455static inline u32 fifo_trigger_mmu_fault_id_f(u32 v)
456{
457 return (v & 0x1fU) << 0U;
458}
459static inline u32 fifo_trigger_mmu_fault_enable_f(u32 v)
460{
461 return (v & 0x1U) << 8U;
462}
463static inline u32 fifo_engine_status_r(u32 i)
464{
465 return 0x00002640U + i*8U;
466}
467static inline u32 fifo_engine_status__size_1_v(void)
468{
469 return 0x00000002U;
470}
471static inline u32 fifo_engine_status_id_v(u32 r)
472{
473 return (r >> 0U) & 0xfffU;
474}
475static inline u32 fifo_engine_status_id_type_v(u32 r)
476{
477 return (r >> 12U) & 0x1U;
478}
479static inline u32 fifo_engine_status_id_type_chid_v(void)
480{
481 return 0x00000000U;
482}
483static inline u32 fifo_engine_status_id_type_tsgid_v(void)
484{
485 return 0x00000001U;
486}
487static inline u32 fifo_engine_status_ctx_status_v(u32 r)
488{
489 return (r >> 13U) & 0x7U;
490}
491static inline u32 fifo_engine_status_ctx_status_invalid_v(void)
492{
493 return 0x00000000U;
494}
495static inline u32 fifo_engine_status_ctx_status_valid_v(void)
496{
497 return 0x00000001U;
498}
499static inline u32 fifo_engine_status_ctx_status_ctxsw_load_v(void)
500{
501 return 0x00000005U;
502}
503static inline u32 fifo_engine_status_ctx_status_ctxsw_save_v(void)
504{
505 return 0x00000006U;
506}
507static inline u32 fifo_engine_status_ctx_status_ctxsw_switch_v(void)
508{
509 return 0x00000007U;
510}
511static inline u32 fifo_engine_status_next_id_v(u32 r)
512{
513 return (r >> 16U) & 0xfffU;
514}
515static inline u32 fifo_engine_status_next_id_type_v(u32 r)
516{
517 return (r >> 28U) & 0x1U;
518}
519static inline u32 fifo_engine_status_next_id_type_chid_v(void)
520{
521 return 0x00000000U;
522}
523static inline u32 fifo_engine_status_faulted_v(u32 r)
524{
525 return (r >> 30U) & 0x1U;
526}
527static inline u32 fifo_engine_status_faulted_true_v(void)
528{
529 return 0x00000001U;
530}
531static inline u32 fifo_engine_status_engine_v(u32 r)
532{
533 return (r >> 31U) & 0x1U;
534}
535static inline u32 fifo_engine_status_engine_idle_v(void)
536{
537 return 0x00000000U;
538}
539static inline u32 fifo_engine_status_engine_busy_v(void)
540{
541 return 0x00000001U;
542}
543static inline u32 fifo_engine_status_ctxsw_v(u32 r)
544{
545 return (r >> 15U) & 0x1U;
546}
547static inline u32 fifo_engine_status_ctxsw_in_progress_v(void)
548{
549 return 0x00000001U;
550}
551static inline u32 fifo_engine_status_ctxsw_in_progress_f(void)
552{
553 return 0x8000U;
554}
555static inline u32 fifo_pbdma_status_r(u32 i)
556{
557 return 0x00003080U + i*4U;
558}
559static inline u32 fifo_pbdma_status__size_1_v(void)
560{
561 return 0x00000001U;
562}
563static inline u32 fifo_pbdma_status_id_v(u32 r)
564{
565 return (r >> 0U) & 0xfffU;
566}
567static inline u32 fifo_pbdma_status_id_type_v(u32 r)
568{
569 return (r >> 12U) & 0x1U;
570}
571static inline u32 fifo_pbdma_status_id_type_chid_v(void)
572{
573 return 0x00000000U;
574}
575static inline u32 fifo_pbdma_status_id_type_tsgid_v(void)
576{
577 return 0x00000001U;
578}
579static inline u32 fifo_pbdma_status_chan_status_v(u32 r)
580{
581 return (r >> 13U) & 0x7U;
582}
583static inline u32 fifo_pbdma_status_chan_status_valid_v(void)
584{
585 return 0x00000001U;
586}
587static inline u32 fifo_pbdma_status_chan_status_chsw_load_v(void)
588{
589 return 0x00000005U;
590}
591static inline u32 fifo_pbdma_status_chan_status_chsw_save_v(void)
592{
593 return 0x00000006U;
594}
595static inline u32 fifo_pbdma_status_chan_status_chsw_switch_v(void)
596{
597 return 0x00000007U;
598}
599static inline u32 fifo_pbdma_status_next_id_v(u32 r)
600{
601 return (r >> 16U) & 0xfffU;
602}
603static inline u32 fifo_pbdma_status_next_id_type_v(u32 r)
604{
605 return (r >> 28U) & 0x1U;
606}
607static inline u32 fifo_pbdma_status_next_id_type_chid_v(void)
608{
609 return 0x00000000U;
610}
611static inline u32 fifo_pbdma_status_chsw_v(u32 r)
612{
613 return (r >> 15U) & 0x1U;
614}
615static inline u32 fifo_pbdma_status_chsw_in_progress_v(void)
616{
617 return 0x00000001U;
618}
619#endif
diff --git a/include/gk20a/hw_flush_gk20a.h b/include/gk20a/hw_flush_gk20a.h
deleted file mode 100644
index d270b5f..0000000
--- a/include/gk20a/hw_flush_gk20a.h
+++ /dev/null
@@ -1,187 +0,0 @@
1/*
2 * Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22/*
23 * Function naming determines intended use:
24 *
25 * <x>_r(void) : Returns the offset for register <x>.
26 *
27 * <x>_o(void) : Returns the offset for element <x>.
28 *
29 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
30 *
31 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
32 *
33 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
34 * and masked to place it at field <y> of register <x>. This value
35 * can be |'d with others to produce a full register value for
36 * register <x>.
37 *
38 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
39 * value can be ~'d and then &'d to clear the value of field <y> for
40 * register <x>.
41 *
42 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
43 * to place it at field <y> of register <x>. This value can be |'d
44 * with others to produce a full register value for <x>.
45 *
46 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
47 * <x> value 'r' after being shifted to place its LSB at bit 0.
48 * This value is suitable for direct comparison with other unshifted
49 * values appropriate for use in field <y> of register <x>.
50 *
51 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
52 * field <y> of register <x>. This value is suitable for direct
53 * comparison with unshifted values appropriate for use in field <y>
54 * of register <x>.
55 */
56#ifndef _hw_flush_gk20a_h_
57#define _hw_flush_gk20a_h_
58
59static inline u32 flush_l2_system_invalidate_r(void)
60{
61 return 0x00070004U;
62}
63static inline u32 flush_l2_system_invalidate_pending_v(u32 r)
64{
65 return (r >> 0U) & 0x1U;
66}
67static inline u32 flush_l2_system_invalidate_pending_busy_v(void)
68{
69 return 0x00000001U;
70}
71static inline u32 flush_l2_system_invalidate_pending_busy_f(void)
72{
73 return 0x1U;
74}
75static inline u32 flush_l2_system_invalidate_outstanding_v(u32 r)
76{
77 return (r >> 1U) & 0x1U;
78}
79static inline u32 flush_l2_system_invalidate_outstanding_true_v(void)
80{
81 return 0x00000001U;
82}
83static inline u32 flush_l2_flush_dirty_r(void)
84{
85 return 0x00070010U;
86}
87static inline u32 flush_l2_flush_dirty_pending_v(u32 r)
88{
89 return (r >> 0U) & 0x1U;
90}
91static inline u32 flush_l2_flush_dirty_pending_empty_v(void)
92{
93 return 0x00000000U;
94}
95static inline u32 flush_l2_flush_dirty_pending_empty_f(void)
96{
97 return 0x0U;
98}
99static inline u32 flush_l2_flush_dirty_pending_busy_v(void)
100{
101 return 0x00000001U;
102}
103static inline u32 flush_l2_flush_dirty_pending_busy_f(void)
104{
105 return 0x1U;
106}
107static inline u32 flush_l2_flush_dirty_outstanding_v(u32 r)
108{
109 return (r >> 1U) & 0x1U;
110}
111static inline u32 flush_l2_flush_dirty_outstanding_false_v(void)
112{
113 return 0x00000000U;
114}
115static inline u32 flush_l2_flush_dirty_outstanding_false_f(void)
116{
117 return 0x0U;
118}
119static inline u32 flush_l2_flush_dirty_outstanding_true_v(void)
120{
121 return 0x00000001U;
122}
123static inline u32 flush_l2_clean_comptags_r(void)
124{
125 return 0x0007000cU;
126}
127static inline u32 flush_l2_clean_comptags_pending_v(u32 r)
128{
129 return (r >> 0U) & 0x1U;
130}
131static inline u32 flush_l2_clean_comptags_pending_empty_v(void)
132{
133 return 0x00000000U;
134}
135static inline u32 flush_l2_clean_comptags_pending_empty_f(void)
136{
137 return 0x0U;
138}
139static inline u32 flush_l2_clean_comptags_pending_busy_v(void)
140{
141 return 0x00000001U;
142}
143static inline u32 flush_l2_clean_comptags_pending_busy_f(void)
144{
145 return 0x1U;
146}
147static inline u32 flush_l2_clean_comptags_outstanding_v(u32 r)
148{
149 return (r >> 1U) & 0x1U;
150}
151static inline u32 flush_l2_clean_comptags_outstanding_false_v(void)
152{
153 return 0x00000000U;
154}
155static inline u32 flush_l2_clean_comptags_outstanding_false_f(void)
156{
157 return 0x0U;
158}
159static inline u32 flush_l2_clean_comptags_outstanding_true_v(void)
160{
161 return 0x00000001U;
162}
163static inline u32 flush_fb_flush_r(void)
164{
165 return 0x00070000U;
166}
167static inline u32 flush_fb_flush_pending_v(u32 r)
168{
169 return (r >> 0U) & 0x1U;
170}
171static inline u32 flush_fb_flush_pending_busy_v(void)
172{
173 return 0x00000001U;
174}
175static inline u32 flush_fb_flush_pending_busy_f(void)
176{
177 return 0x1U;
178}
179static inline u32 flush_fb_flush_outstanding_v(u32 r)
180{
181 return (r >> 1U) & 0x1U;
182}
183static inline u32 flush_fb_flush_outstanding_true_v(void)
184{
185 return 0x00000001U;
186}
187#endif
diff --git a/include/gk20a/hw_gmmu_gk20a.h b/include/gk20a/hw_gmmu_gk20a.h
deleted file mode 100644
index a788d1d..0000000
--- a/include/gk20a/hw_gmmu_gk20a.h
+++ /dev/null
@@ -1,283 +0,0 @@
1/*
2 * Copyright (c) 2012-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22/*
23 * Function naming determines intended use:
24 *
25 * <x>_r(void) : Returns the offset for register <x>.
26 *
27 * <x>_o(void) : Returns the offset for element <x>.
28 *
29 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
30 *
31 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
32 *
33 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
34 * and masked to place it at field <y> of register <x>. This value
35 * can be |'d with others to produce a full register value for
36 * register <x>.
37 *
38 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
39 * value can be ~'d and then &'d to clear the value of field <y> for
40 * register <x>.
41 *
42 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
43 * to place it at field <y> of register <x>. This value can be |'d
44 * with others to produce a full register value for <x>.
45 *
46 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
47 * <x> value 'r' after being shifted to place its LSB at bit 0.
48 * This value is suitable for direct comparison with other unshifted
49 * values appropriate for use in field <y> of register <x>.
50 *
51 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
52 * field <y> of register <x>. This value is suitable for direct
53 * comparison with unshifted values appropriate for use in field <y>
54 * of register <x>.
55 */
56#ifndef _hw_gmmu_gk20a_h_
57#define _hw_gmmu_gk20a_h_
58
59static inline u32 gmmu_pde_aperture_big_w(void)
60{
61 return 0U;
62}
63static inline u32 gmmu_pde_aperture_big_invalid_f(void)
64{
65 return 0x0U;
66}
67static inline u32 gmmu_pde_aperture_big_video_memory_f(void)
68{
69 return 0x1U;
70}
71static inline u32 gmmu_pde_aperture_big_sys_mem_coh_f(void)
72{
73 return 0x2U;
74}
75static inline u32 gmmu_pde_aperture_big_sys_mem_ncoh_f(void)
76{
77 return 0x3U;
78}
79static inline u32 gmmu_pde_size_w(void)
80{
81 return 0U;
82}
83static inline u32 gmmu_pde_size_full_f(void)
84{
85 return 0x0U;
86}
87static inline u32 gmmu_pde_address_big_sys_f(u32 v)
88{
89 return (v & 0xfffffffU) << 4U;
90}
91static inline u32 gmmu_pde_address_big_sys_w(void)
92{
93 return 0U;
94}
95static inline u32 gmmu_pde_aperture_small_w(void)
96{
97 return 1U;
98}
99static inline u32 gmmu_pde_aperture_small_invalid_f(void)
100{
101 return 0x0U;
102}
103static inline u32 gmmu_pde_aperture_small_video_memory_f(void)
104{
105 return 0x1U;
106}
107static inline u32 gmmu_pde_aperture_small_sys_mem_coh_f(void)
108{
109 return 0x2U;
110}
111static inline u32 gmmu_pde_aperture_small_sys_mem_ncoh_f(void)
112{
113 return 0x3U;
114}
115static inline u32 gmmu_pde_vol_small_w(void)
116{
117 return 1U;
118}
119static inline u32 gmmu_pde_vol_small_true_f(void)
120{
121 return 0x4U;
122}
123static inline u32 gmmu_pde_vol_small_false_f(void)
124{
125 return 0x0U;
126}
127static inline u32 gmmu_pde_vol_big_w(void)
128{
129 return 1U;
130}
131static inline u32 gmmu_pde_vol_big_true_f(void)
132{
133 return 0x8U;
134}
135static inline u32 gmmu_pde_vol_big_false_f(void)
136{
137 return 0x0U;
138}
139static inline u32 gmmu_pde_address_small_sys_f(u32 v)
140{
141 return (v & 0xfffffffU) << 4U;
142}
143static inline u32 gmmu_pde_address_small_sys_w(void)
144{
145 return 1U;
146}
147static inline u32 gmmu_pde_address_shift_v(void)
148{
149 return 0x0000000cU;
150}
151static inline u32 gmmu_pde__size_v(void)
152{
153 return 0x00000008U;
154}
155static inline u32 gmmu_pte__size_v(void)
156{
157 return 0x00000008U;
158}
159static inline u32 gmmu_pte_valid_w(void)
160{
161 return 0U;
162}
163static inline u32 gmmu_pte_valid_true_f(void)
164{
165 return 0x1U;
166}
167static inline u32 gmmu_pte_valid_false_f(void)
168{
169 return 0x0U;
170}
171static inline u32 gmmu_pte_privilege_w(void)
172{
173 return 0U;
174}
175static inline u32 gmmu_pte_privilege_true_f(void)
176{
177 return 0x2U;
178}
179static inline u32 gmmu_pte_privilege_false_f(void)
180{
181 return 0x0U;
182}
183static inline u32 gmmu_pte_address_sys_f(u32 v)
184{
185 return (v & 0xfffffffU) << 4U;
186}
187static inline u32 gmmu_pte_address_sys_w(void)
188{
189 return 0U;
190}
191static inline u32 gmmu_pte_address_vid_f(u32 v)
192{
193 return (v & 0x1ffffffU) << 4U;
194}
195static inline u32 gmmu_pte_address_vid_w(void)
196{
197 return 0U;
198}
199static inline u32 gmmu_pte_vol_w(void)
200{
201 return 1U;
202}
203static inline u32 gmmu_pte_vol_true_f(void)
204{
205 return 0x1U;
206}
207static inline u32 gmmu_pte_vol_false_f(void)
208{
209 return 0x0U;
210}
211static inline u32 gmmu_pte_aperture_w(void)
212{
213 return 1U;
214}
215static inline u32 gmmu_pte_aperture_video_memory_f(void)
216{
217 return 0x0U;
218}
219static inline u32 gmmu_pte_aperture_sys_mem_coh_f(void)
220{
221 return 0x4U;
222}
223static inline u32 gmmu_pte_aperture_sys_mem_ncoh_f(void)
224{
225 return 0x6U;
226}
227static inline u32 gmmu_pte_read_only_w(void)
228{
229 return 0U;
230}
231static inline u32 gmmu_pte_read_only_true_f(void)
232{
233 return 0x4U;
234}
235static inline u32 gmmu_pte_write_disable_w(void)
236{
237 return 1U;
238}
239static inline u32 gmmu_pte_write_disable_true_f(void)
240{
241 return 0x80000000U;
242}
243static inline u32 gmmu_pte_read_disable_w(void)
244{
245 return 1U;
246}
247static inline u32 gmmu_pte_read_disable_true_f(void)
248{
249 return 0x40000000U;
250}
251static inline u32 gmmu_pte_comptagline_s(void)
252{
253 return 17U;
254}
255static inline u32 gmmu_pte_comptagline_f(u32 v)
256{
257 return (v & 0x1ffffU) << 12U;
258}
259static inline u32 gmmu_pte_comptagline_w(void)
260{
261 return 1U;
262}
263static inline u32 gmmu_pte_address_shift_v(void)
264{
265 return 0x0000000cU;
266}
267static inline u32 gmmu_pte_kind_f(u32 v)
268{
269 return (v & 0xffU) << 4U;
270}
271static inline u32 gmmu_pte_kind_w(void)
272{
273 return 1U;
274}
275static inline u32 gmmu_pte_kind_invalid_v(void)
276{
277 return 0x000000ffU;
278}
279static inline u32 gmmu_pte_kind_pitch_v(void)
280{
281 return 0x00000000U;
282}
283#endif
diff --git a/include/gk20a/hw_gr_gk20a.h b/include/gk20a/hw_gr_gk20a.h
deleted file mode 100644
index 826108f..0000000
--- a/include/gk20a/hw_gr_gk20a.h
+++ /dev/null
@@ -1,3807 +0,0 @@
1/*
2 * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22/*
23 * Function naming determines intended use:
24 *
25 * <x>_r(void) : Returns the offset for register <x>.
26 *
27 * <x>_o(void) : Returns the offset for element <x>.
28 *
29 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
30 *
31 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
32 *
33 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
34 * and masked to place it at field <y> of register <x>. This value
35 * can be |'d with others to produce a full register value for
36 * register <x>.
37 *
38 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
39 * value can be ~'d and then &'d to clear the value of field <y> for
40 * register <x>.
41 *
42 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
43 * to place it at field <y> of register <x>. This value can be |'d
44 * with others to produce a full register value for <x>.
45 *
46 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
47 * <x> value 'r' after being shifted to place its LSB at bit 0.
48 * This value is suitable for direct comparison with other unshifted
49 * values appropriate for use in field <y> of register <x>.
50 *
51 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
52 * field <y> of register <x>. This value is suitable for direct
53 * comparison with unshifted values appropriate for use in field <y>
54 * of register <x>.
55 */
56#ifndef _hw_gr_gk20a_h_
57#define _hw_gr_gk20a_h_
58
59static inline u32 gr_intr_r(void)
60{
61 return 0x00400100U;
62}
63static inline u32 gr_intr_notify_pending_f(void)
64{
65 return 0x1U;
66}
67static inline u32 gr_intr_notify_reset_f(void)
68{
69 return 0x1U;
70}
71static inline u32 gr_intr_semaphore_pending_f(void)
72{
73 return 0x2U;
74}
75static inline u32 gr_intr_semaphore_reset_f(void)
76{
77 return 0x2U;
78}
79static inline u32 gr_intr_semaphore_timeout_not_pending_f(void)
80{
81 return 0x0U;
82}
83static inline u32 gr_intr_semaphore_timeout_pending_f(void)
84{
85 return 0x4U;
86}
87static inline u32 gr_intr_semaphore_timeout_reset_f(void)
88{
89 return 0x4U;
90}
91static inline u32 gr_intr_illegal_method_pending_f(void)
92{
93 return 0x10U;
94}
95static inline u32 gr_intr_illegal_method_reset_f(void)
96{
97 return 0x10U;
98}
99static inline u32 gr_intr_illegal_notify_pending_f(void)
100{
101 return 0x40U;
102}
103static inline u32 gr_intr_illegal_notify_reset_f(void)
104{
105 return 0x40U;
106}
107static inline u32 gr_intr_firmware_method_f(u32 v)
108{
109 return (v & 0x1U) << 8U;
110}
111static inline u32 gr_intr_firmware_method_pending_f(void)
112{
113 return 0x100U;
114}
115static inline u32 gr_intr_firmware_method_reset_f(void)
116{
117 return 0x100U;
118}
119static inline u32 gr_intr_illegal_class_pending_f(void)
120{
121 return 0x20U;
122}
123static inline u32 gr_intr_illegal_class_reset_f(void)
124{
125 return 0x20U;
126}
127static inline u32 gr_intr_fecs_error_pending_f(void)
128{
129 return 0x80000U;
130}
131static inline u32 gr_intr_fecs_error_reset_f(void)
132{
133 return 0x80000U;
134}
135static inline u32 gr_intr_class_error_pending_f(void)
136{
137 return 0x100000U;
138}
139static inline u32 gr_intr_class_error_reset_f(void)
140{
141 return 0x100000U;
142}
143static inline u32 gr_intr_exception_pending_f(void)
144{
145 return 0x200000U;
146}
147static inline u32 gr_intr_exception_reset_f(void)
148{
149 return 0x200000U;
150}
151static inline u32 gr_fecs_intr_r(void)
152{
153 return 0x00400144U;
154}
155static inline u32 gr_class_error_r(void)
156{
157 return 0x00400110U;
158}
159static inline u32 gr_class_error_code_v(u32 r)
160{
161 return (r >> 0U) & 0xffffU;
162}
163static inline u32 gr_intr_nonstall_r(void)
164{
165 return 0x00400120U;
166}
167static inline u32 gr_intr_nonstall_trap_pending_f(void)
168{
169 return 0x2U;
170}
171static inline u32 gr_intr_en_r(void)
172{
173 return 0x0040013cU;
174}
175static inline u32 gr_exception_r(void)
176{
177 return 0x00400108U;
178}
179static inline u32 gr_exception_fe_m(void)
180{
181 return 0x1U << 0U;
182}
183static inline u32 gr_exception_gpc_m(void)
184{
185 return 0x1U << 24U;
186}
187static inline u32 gr_exception_memfmt_m(void)
188{
189 return 0x1U << 1U;
190}
191static inline u32 gr_exception_ds_m(void)
192{
193 return 0x1U << 4U;
194}
195static inline u32 gr_exception_sked_m(void)
196{
197 return 0x1U << 8U;
198}
199static inline u32 gr_exception_pd_m(void)
200{
201 return 0x1U << 2U;
202}
203static inline u32 gr_exception_scc_m(void)
204{
205 return 0x1U << 3U;
206}
207static inline u32 gr_exception_ssync_m(void)
208{
209 return 0x1U << 5U;
210}
211static inline u32 gr_exception_mme_m(void)
212{
213 return 0x1U << 7U;
214}
215static inline u32 gr_exception1_r(void)
216{
217 return 0x00400118U;
218}
219static inline u32 gr_exception1_gpc_0_pending_f(void)
220{
221 return 0x1U;
222}
223static inline u32 gr_exception2_r(void)
224{
225 return 0x0040011cU;
226}
227static inline u32 gr_exception_en_r(void)
228{
229 return 0x00400138U;
230}
231static inline u32 gr_exception_en_fe_m(void)
232{
233 return 0x1U << 0U;
234}
235static inline u32 gr_exception1_en_r(void)
236{
237 return 0x00400130U;
238}
239static inline u32 gr_exception2_en_r(void)
240{
241 return 0x00400134U;
242}
243static inline u32 gr_gpfifo_ctl_r(void)
244{
245 return 0x00400500U;
246}
247static inline u32 gr_gpfifo_ctl_access_f(u32 v)
248{
249 return (v & 0x1U) << 0U;
250}
251static inline u32 gr_gpfifo_ctl_access_disabled_f(void)
252{
253 return 0x0U;
254}
255static inline u32 gr_gpfifo_ctl_access_enabled_f(void)
256{
257 return 0x1U;
258}
259static inline u32 gr_gpfifo_ctl_semaphore_access_f(u32 v)
260{
261 return (v & 0x1U) << 16U;
262}
263static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_v(void)
264{
265 return 0x00000001U;
266}
267static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_f(void)
268{
269 return 0x10000U;
270}
271static inline u32 gr_gpfifo_status_r(void)
272{
273 return 0x00400504U;
274}
275static inline u32 gr_trapped_addr_r(void)
276{
277 return 0x00400704U;
278}
279static inline u32 gr_trapped_addr_mthd_v(u32 r)
280{
281 return (r >> 2U) & 0xfffU;
282}
283static inline u32 gr_trapped_addr_subch_v(u32 r)
284{
285 return (r >> 16U) & 0x7U;
286}
287static inline u32 gr_trapped_addr_mme_generated_v(u32 r)
288{
289 return (r >> 20U) & 0x1U;
290}
291static inline u32 gr_trapped_addr_datahigh_v(u32 r)
292{
293 return (r >> 24U) & 0x1U;
294}
295static inline u32 gr_trapped_addr_priv_v(u32 r)
296{
297 return (r >> 28U) & 0x1U;
298}
299static inline u32 gr_trapped_addr_status_v(u32 r)
300{
301 return (r >> 31U) & 0x1U;
302}
303static inline u32 gr_trapped_data_lo_r(void)
304{
305 return 0x00400708U;
306}
307static inline u32 gr_trapped_data_hi_r(void)
308{
309 return 0x0040070cU;
310}
311static inline u32 gr_trapped_data_mme_r(void)
312{
313 return 0x00400710U;
314}
315static inline u32 gr_trapped_data_mme_pc_v(u32 r)
316{
317 return (r >> 0U) & 0x7ffU;
318}
319static inline u32 gr_status_r(void)
320{
321 return 0x00400700U;
322}
323static inline u32 gr_status_fe_method_upper_v(u32 r)
324{
325 return (r >> 1U) & 0x1U;
326}
327static inline u32 gr_status_fe_method_lower_v(u32 r)
328{
329 return (r >> 2U) & 0x1U;
330}
331static inline u32 gr_status_fe_method_lower_idle_v(void)
332{
333 return 0x00000000U;
334}
335static inline u32 gr_status_fe_gi_v(u32 r)
336{
337 return (r >> 21U) & 0x1U;
338}
339static inline u32 gr_status_mask_r(void)
340{
341 return 0x00400610U;
342}
343static inline u32 gr_status_1_r(void)
344{
345 return 0x00400604U;
346}
347static inline u32 gr_status_2_r(void)
348{
349 return 0x00400608U;
350}
351static inline u32 gr_engine_status_r(void)
352{
353 return 0x0040060cU;
354}
355static inline u32 gr_engine_status_value_busy_f(void)
356{
357 return 0x1U;
358}
359static inline u32 gr_pri_be0_becs_be_exception_r(void)
360{
361 return 0x00410204U;
362}
363static inline u32 gr_pri_be0_becs_be_exception_en_r(void)
364{
365 return 0x00410208U;
366}
367static inline u32 gr_pri_gpc0_gpccs_gpc_exception_r(void)
368{
369 return 0x00502c90U;
370}
371static inline u32 gr_pri_gpc0_gpccs_gpc_exception_en_r(void)
372{
373 return 0x00502c94U;
374}
375static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_r(void)
376{
377 return 0x00504508U;
378}
379static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r(void)
380{
381 return 0x0050450cU;
382}
383static inline u32 gr_activity_0_r(void)
384{
385 return 0x00400380U;
386}
387static inline u32 gr_activity_1_r(void)
388{
389 return 0x00400384U;
390}
391static inline u32 gr_activity_2_r(void)
392{
393 return 0x00400388U;
394}
395static inline u32 gr_activity_4_r(void)
396{
397 return 0x00400390U;
398}
399static inline u32 gr_pri_gpc0_gcc_dbg_r(void)
400{
401 return 0x00501000U;
402}
403static inline u32 gr_pri_gpcs_gcc_dbg_r(void)
404{
405 return 0x00419000U;
406}
407static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void)
408{
409 return 0x1U << 1U;
410}
411static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void)
412{
413 return 0x005046a4U;
414}
415static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void)
416{
417 return 0x00419ea4U;
418}
419static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void)
420{
421 return 0x1U << 0U;
422}
423static inline u32 gr_pri_sked_activity_r(void)
424{
425 return 0x00407054U;
426}
427static inline u32 gr_pri_gpc0_gpccs_gpc_activity0_r(void)
428{
429 return 0x00502c80U;
430}
431static inline u32 gr_pri_gpc0_gpccs_gpc_activity1_r(void)
432{
433 return 0x00502c84U;
434}
435static inline u32 gr_pri_gpc0_gpccs_gpc_activity2_r(void)
436{
437 return 0x00502c88U;
438}
439static inline u32 gr_pri_gpc0_gpccs_gpc_activity3_r(void)
440{
441 return 0x00502c8cU;
442}
443static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r(void)
444{
445 return 0x00504500U;
446}
447static inline u32 gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r(void)
448{
449 return 0x00501d00U;
450}
451static inline u32 gr_pri_gpcs_gpccs_gpc_activity_0_r(void)
452{
453 return 0x0041ac80U;
454}
455static inline u32 gr_pri_gpcs_gpccs_gpc_activity_1_r(void)
456{
457 return 0x0041ac84U;
458}
459static inline u32 gr_pri_gpcs_gpccs_gpc_activity_2_r(void)
460{
461 return 0x0041ac88U;
462}
463static inline u32 gr_pri_gpcs_gpccs_gpc_activity_3_r(void)
464{
465 return 0x0041ac8cU;
466}
467static inline u32 gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r(void)
468{
469 return 0x0041c500U;
470}
471static inline u32 gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r(void)
472{
473 return 0x00419d00U;
474}
475static inline u32 gr_pri_be0_becs_be_activity0_r(void)
476{
477 return 0x00410200U;
478}
479static inline u32 gr_pri_bes_becs_be_activity0_r(void)
480{
481 return 0x00408a00U;
482}
483static inline u32 gr_pri_ds_mpipe_status_r(void)
484{
485 return 0x00405858U;
486}
487static inline u32 gr_pri_fe_go_idle_on_status_r(void)
488{
489 return 0x00404150U;
490}
491static inline u32 gr_pri_fe_go_idle_check_r(void)
492{
493 return 0x00404158U;
494}
495static inline u32 gr_pri_fe_go_idle_info_r(void)
496{
497 return 0x00404194U;
498}
499static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void)
500{
501 return 0x00504238U;
502}
503static inline u32 gr_pri_be0_crop_status1_r(void)
504{
505 return 0x00410134U;
506}
507static inline u32 gr_pri_bes_crop_status1_r(void)
508{
509 return 0x00408934U;
510}
511static inline u32 gr_pri_be0_zrop_status_r(void)
512{
513 return 0x00410048U;
514}
515static inline u32 gr_pri_be0_zrop_status2_r(void)
516{
517 return 0x0041004cU;
518}
519static inline u32 gr_pri_bes_zrop_status_r(void)
520{
521 return 0x00408848U;
522}
523static inline u32 gr_pri_bes_zrop_status2_r(void)
524{
525 return 0x0040884cU;
526}
527static inline u32 gr_pipe_bundle_address_r(void)
528{
529 return 0x00400200U;
530}
531static inline u32 gr_pipe_bundle_address_value_v(u32 r)
532{
533 return (r >> 0U) & 0xffffU;
534}
535static inline u32 gr_pipe_bundle_data_r(void)
536{
537 return 0x00400204U;
538}
539static inline u32 gr_pipe_bundle_config_r(void)
540{
541 return 0x00400208U;
542}
543static inline u32 gr_pipe_bundle_config_override_pipe_mode_disabled_f(void)
544{
545 return 0x0U;
546}
547static inline u32 gr_pipe_bundle_config_override_pipe_mode_enabled_f(void)
548{
549 return 0x80000000U;
550}
551static inline u32 gr_fe_hww_esr_r(void)
552{
553 return 0x00404000U;
554}
555static inline u32 gr_fe_hww_esr_reset_active_f(void)
556{
557 return 0x40000000U;
558}
559static inline u32 gr_fe_hww_esr_en_enable_f(void)
560{
561 return 0x80000000U;
562}
563static inline u32 gr_fe_hww_esr_info_r(void)
564{
565 return 0x004041b0U;
566}
567static inline u32 gr_fe_go_idle_timeout_r(void)
568{
569 return 0x00404154U;
570}
571static inline u32 gr_fe_go_idle_timeout_count_f(u32 v)
572{
573 return (v & 0xffffffffU) << 0U;
574}
575static inline u32 gr_fe_go_idle_timeout_count_disabled_f(void)
576{
577 return 0x0U;
578}
579static inline u32 gr_fe_go_idle_timeout_count_prod_f(void)
580{
581 return 0x800U;
582}
583static inline u32 gr_fe_object_table_r(u32 i)
584{
585 return 0x00404200U + i*4U;
586}
587static inline u32 gr_fe_object_table_nvclass_v(u32 r)
588{
589 return (r >> 0U) & 0xffffU;
590}
591static inline u32 gr_pri_mme_shadow_raw_index_r(void)
592{
593 return 0x00404488U;
594}
595static inline u32 gr_pri_mme_shadow_raw_index_write_trigger_f(void)
596{
597 return 0x80000000U;
598}
599static inline u32 gr_pri_mme_shadow_raw_data_r(void)
600{
601 return 0x0040448cU;
602}
603static inline u32 gr_mme_hww_esr_r(void)
604{
605 return 0x00404490U;
606}
607static inline u32 gr_mme_hww_esr_reset_active_f(void)
608{
609 return 0x40000000U;
610}
611static inline u32 gr_mme_hww_esr_en_enable_f(void)
612{
613 return 0x80000000U;
614}
615static inline u32 gr_mme_hww_esr_info_r(void)
616{
617 return 0x00404494U;
618}
619static inline u32 gr_memfmt_hww_esr_r(void)
620{
621 return 0x00404600U;
622}
623static inline u32 gr_memfmt_hww_esr_reset_active_f(void)
624{
625 return 0x40000000U;
626}
627static inline u32 gr_memfmt_hww_esr_en_enable_f(void)
628{
629 return 0x80000000U;
630}
631static inline u32 gr_fecs_cpuctl_r(void)
632{
633 return 0x00409100U;
634}
635static inline u32 gr_fecs_cpuctl_startcpu_f(u32 v)
636{
637 return (v & 0x1U) << 1U;
638}
639static inline u32 gr_fecs_dmactl_r(void)
640{
641 return 0x0040910cU;
642}
643static inline u32 gr_fecs_dmactl_require_ctx_f(u32 v)
644{
645 return (v & 0x1U) << 0U;
646}
647static inline u32 gr_fecs_dmactl_dmem_scrubbing_m(void)
648{
649 return 0x1U << 1U;
650}
651static inline u32 gr_fecs_dmactl_imem_scrubbing_m(void)
652{
653 return 0x1U << 2U;
654}
655static inline u32 gr_fecs_os_r(void)
656{
657 return 0x00409080U;
658}
659static inline u32 gr_fecs_idlestate_r(void)
660{
661 return 0x0040904cU;
662}
663static inline u32 gr_fecs_mailbox0_r(void)
664{
665 return 0x00409040U;
666}
667static inline u32 gr_fecs_mailbox1_r(void)
668{
669 return 0x00409044U;
670}
671static inline u32 gr_fecs_irqstat_r(void)
672{
673 return 0x00409008U;
674}
675static inline u32 gr_fecs_irqmode_r(void)
676{
677 return 0x0040900cU;
678}
679static inline u32 gr_fecs_irqmask_r(void)
680{
681 return 0x00409018U;
682}
683static inline u32 gr_fecs_irqdest_r(void)
684{
685 return 0x0040901cU;
686}
687static inline u32 gr_fecs_curctx_r(void)
688{
689 return 0x00409050U;
690}
691static inline u32 gr_fecs_nxtctx_r(void)
692{
693 return 0x00409054U;
694}
695static inline u32 gr_fecs_engctl_r(void)
696{
697 return 0x004090a4U;
698}
699static inline u32 gr_fecs_debug1_r(void)
700{
701 return 0x00409090U;
702}
703static inline u32 gr_fecs_debuginfo_r(void)
704{
705 return 0x00409094U;
706}
707static inline u32 gr_fecs_icd_cmd_r(void)
708{
709 return 0x00409200U;
710}
711static inline u32 gr_fecs_icd_cmd_opc_s(void)
712{
713 return 4U;
714}
715static inline u32 gr_fecs_icd_cmd_opc_f(u32 v)
716{
717 return (v & 0xfU) << 0U;
718}
719static inline u32 gr_fecs_icd_cmd_opc_m(void)
720{
721 return 0xfU << 0U;
722}
723static inline u32 gr_fecs_icd_cmd_opc_v(u32 r)
724{
725 return (r >> 0U) & 0xfU;
726}
727static inline u32 gr_fecs_icd_cmd_opc_rreg_f(void)
728{
729 return 0x8U;
730}
731static inline u32 gr_fecs_icd_cmd_opc_rstat_f(void)
732{
733 return 0xeU;
734}
735static inline u32 gr_fecs_icd_cmd_idx_f(u32 v)
736{
737 return (v & 0x1fU) << 8U;
738}
739static inline u32 gr_fecs_icd_rdata_r(void)
740{
741 return 0x0040920cU;
742}
743static inline u32 gr_fecs_imemc_r(u32 i)
744{
745 return 0x00409180U + i*16U;
746}
747static inline u32 gr_fecs_imemc_offs_f(u32 v)
748{
749 return (v & 0x3fU) << 2U;
750}
751static inline u32 gr_fecs_imemc_blk_f(u32 v)
752{
753 return (v & 0xffU) << 8U;
754}
755static inline u32 gr_fecs_imemc_aincw_f(u32 v)
756{
757 return (v & 0x1U) << 24U;
758}
759static inline u32 gr_fecs_imemd_r(u32 i)
760{
761 return 0x00409184U + i*16U;
762}
763static inline u32 gr_fecs_imemt_r(u32 i)
764{
765 return 0x00409188U + i*16U;
766}
767static inline u32 gr_fecs_imemt_tag_f(u32 v)
768{
769 return (v & 0xffffU) << 0U;
770}
771static inline u32 gr_fecs_dmemc_r(u32 i)
772{
773 return 0x004091c0U + i*8U;
774}
775static inline u32 gr_fecs_dmemc_offs_s(void)
776{
777 return 6U;
778}
779static inline u32 gr_fecs_dmemc_offs_f(u32 v)
780{
781 return (v & 0x3fU) << 2U;
782}
783static inline u32 gr_fecs_dmemc_offs_m(void)
784{
785 return 0x3fU << 2U;
786}
787static inline u32 gr_fecs_dmemc_offs_v(u32 r)
788{
789 return (r >> 2U) & 0x3fU;
790}
791static inline u32 gr_fecs_dmemc_blk_f(u32 v)
792{
793 return (v & 0xffU) << 8U;
794}
795static inline u32 gr_fecs_dmemc_aincw_f(u32 v)
796{
797 return (v & 0x1U) << 24U;
798}
799static inline u32 gr_fecs_dmemd_r(u32 i)
800{
801 return 0x004091c4U + i*8U;
802}
803static inline u32 gr_fecs_dmatrfbase_r(void)
804{
805 return 0x00409110U;
806}
807static inline u32 gr_fecs_dmatrfmoffs_r(void)
808{
809 return 0x00409114U;
810}
811static inline u32 gr_fecs_dmatrffboffs_r(void)
812{
813 return 0x0040911cU;
814}
815static inline u32 gr_fecs_dmatrfcmd_r(void)
816{
817 return 0x00409118U;
818}
819static inline u32 gr_fecs_dmatrfcmd_imem_f(u32 v)
820{
821 return (v & 0x1U) << 4U;
822}
823static inline u32 gr_fecs_dmatrfcmd_write_f(u32 v)
824{
825 return (v & 0x1U) << 5U;
826}
827static inline u32 gr_fecs_dmatrfcmd_size_f(u32 v)
828{
829 return (v & 0x7U) << 8U;
830}
831static inline u32 gr_fecs_dmatrfcmd_ctxdma_f(u32 v)
832{
833 return (v & 0x7U) << 12U;
834}
835static inline u32 gr_fecs_bootvec_r(void)
836{
837 return 0x00409104U;
838}
839static inline u32 gr_fecs_bootvec_vec_f(u32 v)
840{
841 return (v & 0xffffffffU) << 0U;
842}
843static inline u32 gr_fecs_falcon_hwcfg_r(void)
844{
845 return 0x00409108U;
846}
847static inline u32 gr_gpcs_gpccs_falcon_hwcfg_r(void)
848{
849 return 0x0041a108U;
850}
851static inline u32 gr_fecs_falcon_rm_r(void)
852{
853 return 0x00409084U;
854}
855static inline u32 gr_fecs_current_ctx_r(void)
856{
857 return 0x00409b00U;
858}
859static inline u32 gr_fecs_current_ctx_ptr_f(u32 v)
860{
861 return (v & 0xfffffffU) << 0U;
862}
863static inline u32 gr_fecs_current_ctx_ptr_v(u32 r)
864{
865 return (r >> 0U) & 0xfffffffU;
866}
867static inline u32 gr_fecs_current_ctx_target_s(void)
868{
869 return 2U;
870}
871static inline u32 gr_fecs_current_ctx_target_f(u32 v)
872{
873 return (v & 0x3U) << 28U;
874}
875static inline u32 gr_fecs_current_ctx_target_m(void)
876{
877 return 0x3U << 28U;
878}
879static inline u32 gr_fecs_current_ctx_target_v(u32 r)
880{
881 return (r >> 28U) & 0x3U;
882}
883static inline u32 gr_fecs_current_ctx_target_vid_mem_f(void)
884{
885 return 0x0U;
886}
887static inline u32 gr_fecs_current_ctx_target_sys_mem_coh_f(void)
888{
889 return 0x20000000U;
890}
891static inline u32 gr_fecs_current_ctx_target_sys_mem_ncoh_f(void)
892{
893 return 0x30000000U;
894}
895static inline u32 gr_fecs_current_ctx_valid_s(void)
896{
897 return 1U;
898}
899static inline u32 gr_fecs_current_ctx_valid_f(u32 v)
900{
901 return (v & 0x1U) << 31U;
902}
903static inline u32 gr_fecs_current_ctx_valid_m(void)
904{
905 return 0x1U << 31U;
906}
907static inline u32 gr_fecs_current_ctx_valid_v(u32 r)
908{
909 return (r >> 31U) & 0x1U;
910}
911static inline u32 gr_fecs_current_ctx_valid_false_f(void)
912{
913 return 0x0U;
914}
915static inline u32 gr_fecs_method_data_r(void)
916{
917 return 0x00409500U;
918}
919static inline u32 gr_fecs_method_push_r(void)
920{
921 return 0x00409504U;
922}
923static inline u32 gr_fecs_method_push_adr_f(u32 v)
924{
925 return (v & 0xfffU) << 0U;
926}
927static inline u32 gr_fecs_method_push_adr_bind_pointer_v(void)
928{
929 return 0x00000003U;
930}
931static inline u32 gr_fecs_method_push_adr_bind_pointer_f(void)
932{
933 return 0x3U;
934}
935static inline u32 gr_fecs_method_push_adr_discover_image_size_v(void)
936{
937 return 0x00000010U;
938}
939static inline u32 gr_fecs_method_push_adr_wfi_golden_save_v(void)
940{
941 return 0x00000009U;
942}
943static inline u32 gr_fecs_method_push_adr_restore_golden_v(void)
944{
945 return 0x00000015U;
946}
947static inline u32 gr_fecs_method_push_adr_discover_zcull_image_size_v(void)
948{
949 return 0x00000016U;
950}
951static inline u32 gr_fecs_method_push_adr_discover_pm_image_size_v(void)
952{
953 return 0x00000025U;
954}
955static inline u32 gr_fecs_method_push_adr_discover_reglist_image_size_v(void)
956{
957 return 0x00000030U;
958}
959static inline u32 gr_fecs_method_push_adr_set_reglist_bind_instance_v(void)
960{
961 return 0x00000031U;
962}
963static inline u32 gr_fecs_method_push_adr_set_reglist_virtual_address_v(void)
964{
965 return 0x00000032U;
966}
967static inline u32 gr_fecs_method_push_adr_stop_ctxsw_v(void)
968{
969 return 0x00000038U;
970}
971static inline u32 gr_fecs_method_push_adr_start_ctxsw_v(void)
972{
973 return 0x00000039U;
974}
975static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void)
976{
977 return 0x21U;
978}
979static inline u32 gr_fecs_method_push_adr_halt_pipeline_v(void)
980{
981 return 0x00000004U;
982}
983static inline u32 gr_fecs_host_int_status_r(void)
984{
985 return 0x00409c18U;
986}
987static inline u32 gr_fecs_host_int_status_fault_during_ctxsw_f(u32 v)
988{
989 return (v & 0x1U) << 16U;
990}
991static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v)
992{
993 return (v & 0x1U) << 17U;
994}
995static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v)
996{
997 return (v & 0x1U) << 18U;
998}
999static inline u32 gr_fecs_host_int_status_watchdog_active_f(void)
1000{
1001 return 0x80000U;
1002}
1003static inline u32 gr_fecs_host_int_status_ctxsw_intr_f(u32 v)
1004{
1005 return (v & 0xffffU) << 0U;
1006}
1007static inline u32 gr_fecs_host_int_clear_r(void)
1008{
1009 return 0x00409c20U;
1010}
1011static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_f(u32 v)
1012{
1013 return (v & 0x1U) << 1U;
1014}
1015static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_clear_f(void)
1016{
1017 return 0x2U;
1018}
1019static inline u32 gr_fecs_host_int_enable_r(void)
1020{
1021 return 0x00409c24U;
1022}
1023static inline u32 gr_fecs_host_int_enable_ctxsw_intr1_enable_f(void)
1024{
1025 return 0x2U;
1026}
1027static inline u32 gr_fecs_host_int_enable_fault_during_ctxsw_enable_f(void)
1028{
1029 return 0x10000U;
1030}
1031static inline u32 gr_fecs_host_int_enable_umimp_firmware_method_enable_f(void)
1032{
1033 return 0x20000U;
1034}
1035static inline u32 gr_fecs_host_int_enable_umimp_illegal_method_enable_f(void)
1036{
1037 return 0x40000U;
1038}
1039static inline u32 gr_fecs_host_int_enable_watchdog_enable_f(void)
1040{
1041 return 0x80000U;
1042}
1043static inline u32 gr_fecs_ctxsw_reset_ctl_r(void)
1044{
1045 return 0x00409614U;
1046}
1047static inline u32 gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f(void)
1048{
1049 return 0x0U;
1050}
1051static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f(void)
1052{
1053 return 0x0U;
1054}
1055static inline u32 gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f(void)
1056{
1057 return 0x0U;
1058}
1059static inline u32 gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f(void)
1060{
1061 return 0x10U;
1062}
1063static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f(void)
1064{
1065 return 0x20U;
1066}
1067static inline u32 gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f(void)
1068{
1069 return 0x40U;
1070}
1071static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f(void)
1072{
1073 return 0x0U;
1074}
1075static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f(void)
1076{
1077 return 0x100U;
1078}
1079static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f(void)
1080{
1081 return 0x0U;
1082}
1083static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f(void)
1084{
1085 return 0x200U;
1086}
1087static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_s(void)
1088{
1089 return 1U;
1090}
1091static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_f(u32 v)
1092{
1093 return (v & 0x1U) << 10U;
1094}
1095static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_m(void)
1096{
1097 return 0x1U << 10U;
1098}
1099static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_v(u32 r)
1100{
1101 return (r >> 10U) & 0x1U;
1102}
1103static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f(void)
1104{
1105 return 0x0U;
1106}
1107static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f(void)
1108{
1109 return 0x400U;
1110}
1111static inline u32 gr_fecs_ctx_state_store_major_rev_id_r(void)
1112{
1113 return 0x0040960cU;
1114}
1115static inline u32 gr_fecs_ctxsw_mailbox_r(u32 i)
1116{
1117 return 0x00409800U + i*4U;
1118}
1119static inline u32 gr_fecs_ctxsw_mailbox__size_1_v(void)
1120{
1121 return 0x00000008U;
1122}
1123static inline u32 gr_fecs_ctxsw_mailbox_value_f(u32 v)
1124{
1125 return (v & 0xffffffffU) << 0U;
1126}
1127static inline u32 gr_fecs_ctxsw_mailbox_value_pass_v(void)
1128{
1129 return 0x00000001U;
1130}
1131static inline u32 gr_fecs_ctxsw_mailbox_value_fail_v(void)
1132{
1133 return 0x00000002U;
1134}
1135static inline u32 gr_fecs_ctxsw_mailbox_set_r(u32 i)
1136{
1137 return 0x00409820U + i*4U;
1138}
1139static inline u32 gr_fecs_ctxsw_mailbox_set_value_f(u32 v)
1140{
1141 return (v & 0xffffffffU) << 0U;
1142}
1143static inline u32 gr_fecs_ctxsw_mailbox_clear_r(u32 i)
1144{
1145 return 0x00409840U + i*4U;
1146}
1147static inline u32 gr_fecs_ctxsw_mailbox_clear_value_f(u32 v)
1148{
1149 return (v & 0xffffffffU) << 0U;
1150}
1151static inline u32 gr_fecs_fs_r(void)
1152{
1153 return 0x00409604U;
1154}
1155static inline u32 gr_fecs_fs_num_available_gpcs_s(void)
1156{
1157 return 5U;
1158}
1159static inline u32 gr_fecs_fs_num_available_gpcs_f(u32 v)
1160{
1161 return (v & 0x1fU) << 0U;
1162}
1163static inline u32 gr_fecs_fs_num_available_gpcs_m(void)
1164{
1165 return 0x1fU << 0U;
1166}
1167static inline u32 gr_fecs_fs_num_available_gpcs_v(u32 r)
1168{
1169 return (r >> 0U) & 0x1fU;
1170}
1171static inline u32 gr_fecs_fs_num_available_fbps_s(void)
1172{
1173 return 5U;
1174}
1175static inline u32 gr_fecs_fs_num_available_fbps_f(u32 v)
1176{
1177 return (v & 0x1fU) << 16U;
1178}
1179static inline u32 gr_fecs_fs_num_available_fbps_m(void)
1180{
1181 return 0x1fU << 16U;
1182}
1183static inline u32 gr_fecs_fs_num_available_fbps_v(u32 r)
1184{
1185 return (r >> 16U) & 0x1fU;
1186}
1187static inline u32 gr_fecs_cfg_r(void)
1188{
1189 return 0x00409620U;
1190}
1191static inline u32 gr_fecs_cfg_imem_sz_v(u32 r)
1192{
1193 return (r >> 0U) & 0xffU;
1194}
1195static inline u32 gr_fecs_rc_lanes_r(void)
1196{
1197 return 0x00409880U;
1198}
1199static inline u32 gr_fecs_rc_lanes_num_chains_s(void)
1200{
1201 return 6U;
1202}
1203static inline u32 gr_fecs_rc_lanes_num_chains_f(u32 v)
1204{
1205 return (v & 0x3fU) << 0U;
1206}
1207static inline u32 gr_fecs_rc_lanes_num_chains_m(void)
1208{
1209 return 0x3fU << 0U;
1210}
1211static inline u32 gr_fecs_rc_lanes_num_chains_v(u32 r)
1212{
1213 return (r >> 0U) & 0x3fU;
1214}
1215static inline u32 gr_fecs_ctxsw_status_1_r(void)
1216{
1217 return 0x00409400U;
1218}
1219static inline u32 gr_fecs_ctxsw_status_1_arb_busy_s(void)
1220{
1221 return 1U;
1222}
1223static inline u32 gr_fecs_ctxsw_status_1_arb_busy_f(u32 v)
1224{
1225 return (v & 0x1U) << 12U;
1226}
1227static inline u32 gr_fecs_ctxsw_status_1_arb_busy_m(void)
1228{
1229 return 0x1U << 12U;
1230}
1231static inline u32 gr_fecs_ctxsw_status_1_arb_busy_v(u32 r)
1232{
1233 return (r >> 12U) & 0x1U;
1234}
1235static inline u32 gr_fecs_arb_ctx_adr_r(void)
1236{
1237 return 0x00409a24U;
1238}
1239static inline u32 gr_fecs_new_ctx_r(void)
1240{
1241 return 0x00409b04U;
1242}
1243static inline u32 gr_fecs_new_ctx_ptr_s(void)
1244{
1245 return 28U;
1246}
1247static inline u32 gr_fecs_new_ctx_ptr_f(u32 v)
1248{
1249 return (v & 0xfffffffU) << 0U;
1250}
1251static inline u32 gr_fecs_new_ctx_ptr_m(void)
1252{
1253 return 0xfffffffU << 0U;
1254}
1255static inline u32 gr_fecs_new_ctx_ptr_v(u32 r)
1256{
1257 return (r >> 0U) & 0xfffffffU;
1258}
1259static inline u32 gr_fecs_new_ctx_target_s(void)
1260{
1261 return 2U;
1262}
1263static inline u32 gr_fecs_new_ctx_target_f(u32 v)
1264{
1265 return (v & 0x3U) << 28U;
1266}
1267static inline u32 gr_fecs_new_ctx_target_m(void)
1268{
1269 return 0x3U << 28U;
1270}
1271static inline u32 gr_fecs_new_ctx_target_v(u32 r)
1272{
1273 return (r >> 28U) & 0x3U;
1274}
1275static inline u32 gr_fecs_new_ctx_target_vid_mem_f(void)
1276{
1277 return 0x0U;
1278}
1279static inline u32 gr_fecs_new_ctx_target_sys_mem_ncoh_f(void)
1280{
1281 return 0x30000000U;
1282}
1283static inline u32 gr_fecs_new_ctx_target_sys_mem_coh_f(void)
1284{
1285 return 0x20000000U;
1286}
1287static inline u32 gr_fecs_new_ctx_valid_s(void)
1288{
1289 return 1U;
1290}
1291static inline u32 gr_fecs_new_ctx_valid_f(u32 v)
1292{
1293 return (v & 0x1U) << 31U;
1294}
1295static inline u32 gr_fecs_new_ctx_valid_m(void)
1296{
1297 return 0x1U << 31U;
1298}
1299static inline u32 gr_fecs_new_ctx_valid_v(u32 r)
1300{
1301 return (r >> 31U) & 0x1U;
1302}
1303static inline u32 gr_fecs_arb_ctx_ptr_r(void)
1304{
1305 return 0x00409a0cU;
1306}
1307static inline u32 gr_fecs_arb_ctx_ptr_ptr_s(void)
1308{
1309 return 28U;
1310}
1311static inline u32 gr_fecs_arb_ctx_ptr_ptr_f(u32 v)
1312{
1313 return (v & 0xfffffffU) << 0U;
1314}
1315static inline u32 gr_fecs_arb_ctx_ptr_ptr_m(void)
1316{
1317 return 0xfffffffU << 0U;
1318}
1319static inline u32 gr_fecs_arb_ctx_ptr_ptr_v(u32 r)
1320{
1321 return (r >> 0U) & 0xfffffffU;
1322}
1323static inline u32 gr_fecs_arb_ctx_ptr_target_s(void)
1324{
1325 return 2U;
1326}
1327static inline u32 gr_fecs_arb_ctx_ptr_target_f(u32 v)
1328{
1329 return (v & 0x3U) << 28U;
1330}
1331static inline u32 gr_fecs_arb_ctx_ptr_target_m(void)
1332{
1333 return 0x3U << 28U;
1334}
1335static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r)
1336{
1337 return (r >> 28U) & 0x3U;
1338}
1339static inline u32 gr_fecs_arb_ctx_ptr_target_vid_mem_f(void)
1340{
1341 return 0x0U;
1342}
1343static inline u32 gr_fecs_arb_ctx_ptr_target_sys_mem_ncoh_f(void)
1344{
1345 return 0x30000000U;
1346}
1347static inline u32 gr_fecs_arb_ctx_ptr_target_sys_mem_coh_f(void)
1348{
1349 return 0x20000000U;
1350}
1351static inline u32 gr_fecs_arb_ctx_cmd_r(void)
1352{
1353 return 0x00409a10U;
1354}
1355static inline u32 gr_fecs_arb_ctx_cmd_cmd_s(void)
1356{
1357 return 5U;
1358}
1359static inline u32 gr_fecs_arb_ctx_cmd_cmd_f(u32 v)
1360{
1361 return (v & 0x1fU) << 0U;
1362}
1363static inline u32 gr_fecs_arb_ctx_cmd_cmd_m(void)
1364{
1365 return 0x1fU << 0U;
1366}
1367static inline u32 gr_fecs_arb_ctx_cmd_cmd_v(u32 r)
1368{
1369 return (r >> 0U) & 0x1fU;
1370}
1371static inline u32 gr_fecs_ctxsw_status_fe_0_r(void)
1372{
1373 return 0x00409c00U;
1374}
1375static inline u32 gr_gpc0_gpccs_ctxsw_status_gpc_0_r(void)
1376{
1377 return 0x00502c04U;
1378}
1379static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void)
1380{
1381 return 0x00502400U;
1382}
1383static inline u32 gr_fecs_ctxsw_idlestate_r(void)
1384{
1385 return 0x00409420U;
1386}
1387static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void)
1388{
1389 return 0x00502420U;
1390}
1391static inline u32 gr_rstr2d_gpc_map0_r(void)
1392{
1393 return 0x0040780cU;
1394}
1395static inline u32 gr_rstr2d_gpc_map1_r(void)
1396{
1397 return 0x00407810U;
1398}
1399static inline u32 gr_rstr2d_gpc_map2_r(void)
1400{
1401 return 0x00407814U;
1402}
1403static inline u32 gr_rstr2d_gpc_map3_r(void)
1404{
1405 return 0x00407818U;
1406}
1407static inline u32 gr_rstr2d_gpc_map4_r(void)
1408{
1409 return 0x0040781cU;
1410}
1411static inline u32 gr_rstr2d_gpc_map5_r(void)
1412{
1413 return 0x00407820U;
1414}
1415static inline u32 gr_rstr2d_map_table_cfg_r(void)
1416{
1417 return 0x004078bcU;
1418}
1419static inline u32 gr_rstr2d_map_table_cfg_row_offset_f(u32 v)
1420{
1421 return (v & 0xffU) << 0U;
1422}
1423static inline u32 gr_rstr2d_map_table_cfg_num_entries_f(u32 v)
1424{
1425 return (v & 0xffU) << 8U;
1426}
1427static inline u32 gr_pd_hww_esr_r(void)
1428{
1429 return 0x00406018U;
1430}
1431static inline u32 gr_pd_hww_esr_reset_active_f(void)
1432{
1433 return 0x40000000U;
1434}
1435static inline u32 gr_pd_hww_esr_en_enable_f(void)
1436{
1437 return 0x80000000U;
1438}
1439static inline u32 gr_pd_num_tpc_per_gpc_r(u32 i)
1440{
1441 return 0x00406028U + i*4U;
1442}
1443static inline u32 gr_pd_num_tpc_per_gpc__size_1_v(void)
1444{
1445 return 0x00000004U;
1446}
1447static inline u32 gr_pd_num_tpc_per_gpc_count0_f(u32 v)
1448{
1449 return (v & 0xfU) << 0U;
1450}
1451static inline u32 gr_pd_num_tpc_per_gpc_count1_f(u32 v)
1452{
1453 return (v & 0xfU) << 4U;
1454}
1455static inline u32 gr_pd_num_tpc_per_gpc_count2_f(u32 v)
1456{
1457 return (v & 0xfU) << 8U;
1458}
1459static inline u32 gr_pd_num_tpc_per_gpc_count3_f(u32 v)
1460{
1461 return (v & 0xfU) << 12U;
1462}
1463static inline u32 gr_pd_num_tpc_per_gpc_count4_f(u32 v)
1464{
1465 return (v & 0xfU) << 16U;
1466}
1467static inline u32 gr_pd_num_tpc_per_gpc_count5_f(u32 v)
1468{
1469 return (v & 0xfU) << 20U;
1470}
1471static inline u32 gr_pd_num_tpc_per_gpc_count6_f(u32 v)
1472{
1473 return (v & 0xfU) << 24U;
1474}
1475static inline u32 gr_pd_num_tpc_per_gpc_count7_f(u32 v)
1476{
1477 return (v & 0xfU) << 28U;
1478}
1479static inline u32 gr_pd_ab_dist_cfg0_r(void)
1480{
1481 return 0x004064c0U;
1482}
1483static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_en_f(void)
1484{
1485 return 0x80000000U;
1486}
1487static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_dis_f(void)
1488{
1489 return 0x0U;
1490}
1491static inline u32 gr_pd_ab_dist_cfg1_r(void)
1492{
1493 return 0x004064c4U;
1494}
1495static inline u32 gr_pd_ab_dist_cfg1_max_batches_init_f(void)
1496{
1497 return 0xffffU;
1498}
1499static inline u32 gr_pd_ab_dist_cfg1_max_output_f(u32 v)
1500{
1501 return (v & 0x7ffU) << 16U;
1502}
1503static inline u32 gr_pd_ab_dist_cfg1_max_output_granularity_v(void)
1504{
1505 return 0x00000080U;
1506}
1507static inline u32 gr_pd_ab_dist_cfg2_r(void)
1508{
1509 return 0x004064c8U;
1510}
1511static inline u32 gr_pd_ab_dist_cfg2_token_limit_f(u32 v)
1512{
1513 return (v & 0xfffU) << 0U;
1514}
1515static inline u32 gr_pd_ab_dist_cfg2_token_limit_init_v(void)
1516{
1517 return 0x00000100U;
1518}
1519static inline u32 gr_pd_ab_dist_cfg2_state_limit_f(u32 v)
1520{
1521 return (v & 0xfffU) << 16U;
1522}
1523static inline u32 gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(void)
1524{
1525 return 0x00000020U;
1526}
1527static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void)
1528{
1529 return 0x00000062U;
1530}
1531static inline u32 gr_pd_pagepool_r(void)
1532{
1533 return 0x004064ccU;
1534}
1535static inline u32 gr_pd_pagepool_total_pages_f(u32 v)
1536{
1537 return (v & 0xffU) << 0U;
1538}
1539static inline u32 gr_pd_pagepool_valid_true_f(void)
1540{
1541 return 0x80000000U;
1542}
1543static inline u32 gr_pd_dist_skip_table_r(u32 i)
1544{
1545 return 0x004064d0U + i*4U;
1546}
1547static inline u32 gr_pd_dist_skip_table__size_1_v(void)
1548{
1549 return 0x00000008U;
1550}
1551static inline u32 gr_pd_dist_skip_table_gpc_4n0_mask_f(u32 v)
1552{
1553 return (v & 0xffU) << 0U;
1554}
1555static inline u32 gr_pd_dist_skip_table_gpc_4n1_mask_f(u32 v)
1556{
1557 return (v & 0xffU) << 8U;
1558}
1559static inline u32 gr_pd_dist_skip_table_gpc_4n2_mask_f(u32 v)
1560{
1561 return (v & 0xffU) << 16U;
1562}
1563static inline u32 gr_pd_dist_skip_table_gpc_4n3_mask_f(u32 v)
1564{
1565 return (v & 0xffU) << 24U;
1566}
1567static inline u32 gr_pd_alpha_ratio_table_r(u32 i)
1568{
1569 return 0x00406800U + i*4U;
1570}
1571static inline u32 gr_pd_alpha_ratio_table__size_1_v(void)
1572{
1573 return 0x00000100U;
1574}
1575static inline u32 gr_pd_alpha_ratio_table_gpc_4n0_mask_f(u32 v)
1576{
1577 return (v & 0xffU) << 0U;
1578}
1579static inline u32 gr_pd_alpha_ratio_table_gpc_4n1_mask_f(u32 v)
1580{
1581 return (v & 0xffU) << 8U;
1582}
1583static inline u32 gr_pd_alpha_ratio_table_gpc_4n2_mask_f(u32 v)
1584{
1585 return (v & 0xffU) << 16U;
1586}
1587static inline u32 gr_pd_alpha_ratio_table_gpc_4n3_mask_f(u32 v)
1588{
1589 return (v & 0xffU) << 24U;
1590}
1591static inline u32 gr_pd_beta_ratio_table_r(u32 i)
1592{
1593 return 0x00406c00U + i*4U;
1594}
1595static inline u32 gr_pd_beta_ratio_table__size_1_v(void)
1596{
1597 return 0x00000100U;
1598}
1599static inline u32 gr_pd_beta_ratio_table_gpc_4n0_mask_f(u32 v)
1600{
1601 return (v & 0xffU) << 0U;
1602}
1603static inline u32 gr_pd_beta_ratio_table_gpc_4n1_mask_f(u32 v)
1604{
1605 return (v & 0xffU) << 8U;
1606}
1607static inline u32 gr_pd_beta_ratio_table_gpc_4n2_mask_f(u32 v)
1608{
1609 return (v & 0xffU) << 16U;
1610}
1611static inline u32 gr_pd_beta_ratio_table_gpc_4n3_mask_f(u32 v)
1612{
1613 return (v & 0xffU) << 24U;
1614}
1615static inline u32 gr_ds_debug_r(void)
1616{
1617 return 0x00405800U;
1618}
1619static inline u32 gr_ds_debug_timeslice_mode_disable_f(void)
1620{
1621 return 0x0U;
1622}
1623static inline u32 gr_ds_debug_timeslice_mode_enable_f(void)
1624{
1625 return 0x8000000U;
1626}
1627static inline u32 gr_ds_zbc_color_r_r(void)
1628{
1629 return 0x00405804U;
1630}
1631static inline u32 gr_ds_zbc_color_r_val_f(u32 v)
1632{
1633 return (v & 0xffffffffU) << 0U;
1634}
1635static inline u32 gr_ds_zbc_color_g_r(void)
1636{
1637 return 0x00405808U;
1638}
1639static inline u32 gr_ds_zbc_color_g_val_f(u32 v)
1640{
1641 return (v & 0xffffffffU) << 0U;
1642}
1643static inline u32 gr_ds_zbc_color_b_r(void)
1644{
1645 return 0x0040580cU;
1646}
1647static inline u32 gr_ds_zbc_color_b_val_f(u32 v)
1648{
1649 return (v & 0xffffffffU) << 0U;
1650}
1651static inline u32 gr_ds_zbc_color_a_r(void)
1652{
1653 return 0x00405810U;
1654}
1655static inline u32 gr_ds_zbc_color_a_val_f(u32 v)
1656{
1657 return (v & 0xffffffffU) << 0U;
1658}
1659static inline u32 gr_ds_zbc_color_fmt_r(void)
1660{
1661 return 0x00405814U;
1662}
1663static inline u32 gr_ds_zbc_color_fmt_val_f(u32 v)
1664{
1665 return (v & 0x7fU) << 0U;
1666}
1667static inline u32 gr_ds_zbc_color_fmt_val_invalid_f(void)
1668{
1669 return 0x0U;
1670}
1671static inline u32 gr_ds_zbc_color_fmt_val_zero_v(void)
1672{
1673 return 0x00000001U;
1674}
1675static inline u32 gr_ds_zbc_color_fmt_val_unorm_one_v(void)
1676{
1677 return 0x00000002U;
1678}
1679static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void)
1680{
1681 return 0x00000004U;
1682}
1683static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void)
1684{
1685 return 0x00000028U;
1686}
1687static inline u32 gr_ds_zbc_z_r(void)
1688{
1689 return 0x00405818U;
1690}
1691static inline u32 gr_ds_zbc_z_val_s(void)
1692{
1693 return 32U;
1694}
1695static inline u32 gr_ds_zbc_z_val_f(u32 v)
1696{
1697 return (v & 0xffffffffU) << 0U;
1698}
1699static inline u32 gr_ds_zbc_z_val_m(void)
1700{
1701 return 0xffffffffU << 0U;
1702}
1703static inline u32 gr_ds_zbc_z_val_v(u32 r)
1704{
1705 return (r >> 0U) & 0xffffffffU;
1706}
1707static inline u32 gr_ds_zbc_z_val__init_v(void)
1708{
1709 return 0x00000000U;
1710}
1711static inline u32 gr_ds_zbc_z_val__init_f(void)
1712{
1713 return 0x0U;
1714}
1715static inline u32 gr_ds_zbc_z_fmt_r(void)
1716{
1717 return 0x0040581cU;
1718}
1719static inline u32 gr_ds_zbc_z_fmt_val_f(u32 v)
1720{
1721 return (v & 0x1U) << 0U;
1722}
1723static inline u32 gr_ds_zbc_z_fmt_val_invalid_f(void)
1724{
1725 return 0x0U;
1726}
1727static inline u32 gr_ds_zbc_z_fmt_val_fp32_v(void)
1728{
1729 return 0x00000001U;
1730}
1731static inline u32 gr_ds_zbc_tbl_index_r(void)
1732{
1733 return 0x00405820U;
1734}
1735static inline u32 gr_ds_zbc_tbl_index_val_f(u32 v)
1736{
1737 return (v & 0xfU) << 0U;
1738}
1739static inline u32 gr_ds_zbc_tbl_ld_r(void)
1740{
1741 return 0x00405824U;
1742}
1743static inline u32 gr_ds_zbc_tbl_ld_select_c_f(void)
1744{
1745 return 0x0U;
1746}
1747static inline u32 gr_ds_zbc_tbl_ld_select_z_f(void)
1748{
1749 return 0x1U;
1750}
1751static inline u32 gr_ds_zbc_tbl_ld_action_write_f(void)
1752{
1753 return 0x0U;
1754}
1755static inline u32 gr_ds_zbc_tbl_ld_trigger_active_f(void)
1756{
1757 return 0x4U;
1758}
1759static inline u32 gr_ds_tga_constraintlogic_r(void)
1760{
1761 return 0x00405830U;
1762}
1763static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v)
1764{
1765 return (v & 0xfffU) << 16U;
1766}
1767static inline u32 gr_ds_tga_constraintlogic_alpha_cbsize_f(u32 v)
1768{
1769 return (v & 0xfffU) << 0U;
1770}
1771static inline u32 gr_ds_hww_esr_r(void)
1772{
1773 return 0x00405840U;
1774}
1775static inline u32 gr_ds_hww_esr_reset_s(void)
1776{
1777 return 1U;
1778}
1779static inline u32 gr_ds_hww_esr_reset_f(u32 v)
1780{
1781 return (v & 0x1U) << 30U;
1782}
1783static inline u32 gr_ds_hww_esr_reset_m(void)
1784{
1785 return 0x1U << 30U;
1786}
1787static inline u32 gr_ds_hww_esr_reset_v(u32 r)
1788{
1789 return (r >> 30U) & 0x1U;
1790}
1791static inline u32 gr_ds_hww_esr_reset_task_v(void)
1792{
1793 return 0x00000001U;
1794}
1795static inline u32 gr_ds_hww_esr_reset_task_f(void)
1796{
1797 return 0x40000000U;
1798}
1799static inline u32 gr_ds_hww_esr_en_enabled_f(void)
1800{
1801 return 0x80000000U;
1802}
1803static inline u32 gr_ds_hww_report_mask_r(void)
1804{
1805 return 0x00405844U;
1806}
1807static inline u32 gr_ds_hww_report_mask_sph0_err_report_f(void)
1808{
1809 return 0x1U;
1810}
1811static inline u32 gr_ds_hww_report_mask_sph1_err_report_f(void)
1812{
1813 return 0x2U;
1814}
1815static inline u32 gr_ds_hww_report_mask_sph2_err_report_f(void)
1816{
1817 return 0x4U;
1818}
1819static inline u32 gr_ds_hww_report_mask_sph3_err_report_f(void)
1820{
1821 return 0x8U;
1822}
1823static inline u32 gr_ds_hww_report_mask_sph4_err_report_f(void)
1824{
1825 return 0x10U;
1826}
1827static inline u32 gr_ds_hww_report_mask_sph5_err_report_f(void)
1828{
1829 return 0x20U;
1830}
1831static inline u32 gr_ds_hww_report_mask_sph6_err_report_f(void)
1832{
1833 return 0x40U;
1834}
1835static inline u32 gr_ds_hww_report_mask_sph7_err_report_f(void)
1836{
1837 return 0x80U;
1838}
1839static inline u32 gr_ds_hww_report_mask_sph8_err_report_f(void)
1840{
1841 return 0x100U;
1842}
1843static inline u32 gr_ds_hww_report_mask_sph9_err_report_f(void)
1844{
1845 return 0x200U;
1846}
1847static inline u32 gr_ds_hww_report_mask_sph10_err_report_f(void)
1848{
1849 return 0x400U;
1850}
1851static inline u32 gr_ds_hww_report_mask_sph11_err_report_f(void)
1852{
1853 return 0x800U;
1854}
1855static inline u32 gr_ds_hww_report_mask_sph12_err_report_f(void)
1856{
1857 return 0x1000U;
1858}
1859static inline u32 gr_ds_hww_report_mask_sph13_err_report_f(void)
1860{
1861 return 0x2000U;
1862}
1863static inline u32 gr_ds_hww_report_mask_sph14_err_report_f(void)
1864{
1865 return 0x4000U;
1866}
1867static inline u32 gr_ds_hww_report_mask_sph15_err_report_f(void)
1868{
1869 return 0x8000U;
1870}
1871static inline u32 gr_ds_hww_report_mask_sph16_err_report_f(void)
1872{
1873 return 0x10000U;
1874}
1875static inline u32 gr_ds_hww_report_mask_sph17_err_report_f(void)
1876{
1877 return 0x20000U;
1878}
1879static inline u32 gr_ds_hww_report_mask_sph18_err_report_f(void)
1880{
1881 return 0x40000U;
1882}
1883static inline u32 gr_ds_hww_report_mask_sph19_err_report_f(void)
1884{
1885 return 0x80000U;
1886}
1887static inline u32 gr_ds_hww_report_mask_sph20_err_report_f(void)
1888{
1889 return 0x100000U;
1890}
1891static inline u32 gr_ds_hww_report_mask_sph21_err_report_f(void)
1892{
1893 return 0x200000U;
1894}
1895static inline u32 gr_ds_hww_report_mask_sph22_err_report_f(void)
1896{
1897 return 0x400000U;
1898}
1899static inline u32 gr_ds_hww_report_mask_sph23_err_report_f(void)
1900{
1901 return 0x800000U;
1902}
1903static inline u32 gr_ds_num_tpc_per_gpc_r(u32 i)
1904{
1905 return 0x00405870U + i*4U;
1906}
1907static inline u32 gr_scc_bundle_cb_base_r(void)
1908{
1909 return 0x00408004U;
1910}
1911static inline u32 gr_scc_bundle_cb_base_addr_39_8_f(u32 v)
1912{
1913 return (v & 0xffffffffU) << 0U;
1914}
1915static inline u32 gr_scc_bundle_cb_base_addr_39_8_align_bits_v(void)
1916{
1917 return 0x00000008U;
1918}
1919static inline u32 gr_scc_bundle_cb_size_r(void)
1920{
1921 return 0x00408008U;
1922}
1923static inline u32 gr_scc_bundle_cb_size_div_256b_f(u32 v)
1924{
1925 return (v & 0x7ffU) << 0U;
1926}
1927static inline u32 gr_scc_bundle_cb_size_div_256b__prod_v(void)
1928{
1929 return 0x00000018U;
1930}
1931static inline u32 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(void)
1932{
1933 return 0x00000100U;
1934}
1935static inline u32 gr_scc_bundle_cb_size_valid_false_v(void)
1936{
1937 return 0x00000000U;
1938}
1939static inline u32 gr_scc_bundle_cb_size_valid_false_f(void)
1940{
1941 return 0x0U;
1942}
1943static inline u32 gr_scc_bundle_cb_size_valid_true_f(void)
1944{
1945 return 0x80000000U;
1946}
1947static inline u32 gr_scc_pagepool_base_r(void)
1948{
1949 return 0x0040800cU;
1950}
1951static inline u32 gr_scc_pagepool_base_addr_39_8_f(u32 v)
1952{
1953 return (v & 0xffffffffU) << 0U;
1954}
1955static inline u32 gr_scc_pagepool_base_addr_39_8_align_bits_v(void)
1956{
1957 return 0x00000008U;
1958}
1959static inline u32 gr_scc_pagepool_r(void)
1960{
1961 return 0x00408010U;
1962}
1963static inline u32 gr_scc_pagepool_total_pages_f(u32 v)
1964{
1965 return (v & 0xffU) << 0U;
1966}
1967static inline u32 gr_scc_pagepool_total_pages_hwmax_v(void)
1968{
1969 return 0x00000000U;
1970}
1971static inline u32 gr_scc_pagepool_total_pages_hwmax_value_v(void)
1972{
1973 return 0x00000080U;
1974}
1975static inline u32 gr_scc_pagepool_total_pages_byte_granularity_v(void)
1976{
1977 return 0x00000100U;
1978}
1979static inline u32 gr_scc_pagepool_max_valid_pages_s(void)
1980{
1981 return 8U;
1982}
1983static inline u32 gr_scc_pagepool_max_valid_pages_f(u32 v)
1984{
1985 return (v & 0xffU) << 8U;
1986}
1987static inline u32 gr_scc_pagepool_max_valid_pages_m(void)
1988{
1989 return 0xffU << 8U;
1990}
1991static inline u32 gr_scc_pagepool_max_valid_pages_v(u32 r)
1992{
1993 return (r >> 8U) & 0xffU;
1994}
1995static inline u32 gr_scc_pagepool_valid_true_f(void)
1996{
1997 return 0x80000000U;
1998}
1999static inline u32 gr_scc_init_r(void)
2000{
2001 return 0x0040802cU;
2002}
2003static inline u32 gr_scc_init_ram_trigger_f(void)
2004{
2005 return 0x1U;
2006}
2007static inline u32 gr_scc_hww_esr_r(void)
2008{
2009 return 0x00408030U;
2010}
2011static inline u32 gr_scc_hww_esr_reset_active_f(void)
2012{
2013 return 0x40000000U;
2014}
2015static inline u32 gr_scc_hww_esr_en_enable_f(void)
2016{
2017 return 0x80000000U;
2018}
2019static inline u32 gr_sked_hww_esr_r(void)
2020{
2021 return 0x00407020U;
2022}
2023static inline u32 gr_sked_hww_esr_reset_active_f(void)
2024{
2025 return 0x40000000U;
2026}
2027static inline u32 gr_cwd_fs_r(void)
2028{
2029 return 0x00405b00U;
2030}
2031static inline u32 gr_cwd_fs_num_gpcs_f(u32 v)
2032{
2033 return (v & 0xffU) << 0U;
2034}
2035static inline u32 gr_cwd_fs_num_tpcs_f(u32 v)
2036{
2037 return (v & 0xffU) << 8U;
2038}
2039static inline u32 gr_gpc0_fs_gpc_r(void)
2040{
2041 return 0x00502608U;
2042}
2043static inline u32 gr_gpc0_fs_gpc_num_available_tpcs_v(u32 r)
2044{
2045 return (r >> 0U) & 0x1fU;
2046}
2047static inline u32 gr_gpc0_fs_gpc_num_available_zculls_v(u32 r)
2048{
2049 return (r >> 16U) & 0x1fU;
2050}
2051static inline u32 gr_gpc0_cfg_r(void)
2052{
2053 return 0x00502620U;
2054}
2055static inline u32 gr_gpc0_cfg_imem_sz_v(u32 r)
2056{
2057 return (r >> 0U) & 0xffU;
2058}
2059static inline u32 gr_gpccs_rc_lanes_r(void)
2060{
2061 return 0x00502880U;
2062}
2063static inline u32 gr_gpccs_rc_lanes_num_chains_s(void)
2064{
2065 return 6U;
2066}
2067static inline u32 gr_gpccs_rc_lanes_num_chains_f(u32 v)
2068{
2069 return (v & 0x3fU) << 0U;
2070}
2071static inline u32 gr_gpccs_rc_lanes_num_chains_m(void)
2072{
2073 return 0x3fU << 0U;
2074}
2075static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r)
2076{
2077 return (r >> 0U) & 0x3fU;
2078}
2079static inline u32 gr_gpccs_rc_lane_size_r(u32 i)
2080{
2081 return 0x00502910U + i*0U;
2082}
2083static inline u32 gr_gpccs_rc_lane_size__size_1_v(void)
2084{
2085 return 0x00000010U;
2086}
2087static inline u32 gr_gpccs_rc_lane_size_v_s(void)
2088{
2089 return 24U;
2090}
2091static inline u32 gr_gpccs_rc_lane_size_v_f(u32 v)
2092{
2093 return (v & 0xffffffU) << 0U;
2094}
2095static inline u32 gr_gpccs_rc_lane_size_v_m(void)
2096{
2097 return 0xffffffU << 0U;
2098}
2099static inline u32 gr_gpccs_rc_lane_size_v_v(u32 r)
2100{
2101 return (r >> 0U) & 0xffffffU;
2102}
2103static inline u32 gr_gpccs_rc_lane_size_v_0_v(void)
2104{
2105 return 0x00000000U;
2106}
2107static inline u32 gr_gpccs_rc_lane_size_v_0_f(void)
2108{
2109 return 0x0U;
2110}
2111static inline u32 gr_gpc0_zcull_fs_r(void)
2112{
2113 return 0x00500910U;
2114}
2115static inline u32 gr_gpc0_zcull_fs_num_sms_f(u32 v)
2116{
2117 return (v & 0x1ffU) << 0U;
2118}
2119static inline u32 gr_gpc0_zcull_fs_num_active_banks_f(u32 v)
2120{
2121 return (v & 0xfU) << 16U;
2122}
2123static inline u32 gr_gpc0_zcull_ram_addr_r(void)
2124{
2125 return 0x00500914U;
2126}
2127static inline u32 gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(u32 v)
2128{
2129 return (v & 0xfU) << 0U;
2130}
2131static inline u32 gr_gpc0_zcull_ram_addr_row_offset_f(u32 v)
2132{
2133 return (v & 0xfU) << 8U;
2134}
2135static inline u32 gr_gpc0_zcull_sm_num_rcp_r(void)
2136{
2137 return 0x00500918U;
2138}
2139static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative_f(u32 v)
2140{
2141 return (v & 0xffffffU) << 0U;
2142}
2143static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative__max_v(void)
2144{
2145 return 0x00800000U;
2146}
2147static inline u32 gr_gpc0_zcull_total_ram_size_r(void)
2148{
2149 return 0x00500920U;
2150}
2151static inline u32 gr_gpc0_zcull_total_ram_size_num_aliquots_f(u32 v)
2152{
2153 return (v & 0xffffU) << 0U;
2154}
2155static inline u32 gr_gpc0_zcull_zcsize_r(u32 i)
2156{
2157 return 0x00500a04U + i*32U;
2158}
2159static inline u32 gr_gpc0_zcull_zcsize_height_subregion__multiple_v(void)
2160{
2161 return 0x00000040U;
2162}
2163static inline u32 gr_gpc0_zcull_zcsize_width_subregion__multiple_v(void)
2164{
2165 return 0x00000010U;
2166}
2167static inline u32 gr_gpc0_gpm_pd_active_tpcs_r(void)
2168{
2169 return 0x00500c08U;
2170}
2171static inline u32 gr_gpc0_gpm_pd_active_tpcs_num_f(u32 v)
2172{
2173 return (v & 0x7U) << 0U;
2174}
2175static inline u32 gr_gpc0_gpm_pd_sm_id_r(u32 i)
2176{
2177 return 0x00500c10U + i*4U;
2178}
2179static inline u32 gr_gpc0_gpm_pd_sm_id_id_f(u32 v)
2180{
2181 return (v & 0xffU) << 0U;
2182}
2183static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_r(u32 i)
2184{
2185 return 0x00500c30U + i*4U;
2186}
2187static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(u32 r)
2188{
2189 return (r >> 0U) & 0xffU;
2190}
2191static inline u32 gr_gpc0_gpm_sd_active_tpcs_r(void)
2192{
2193 return 0x00500c8cU;
2194}
2195static inline u32 gr_gpc0_gpm_sd_active_tpcs_num_f(u32 v)
2196{
2197 return (v & 0x7U) << 0U;
2198}
2199static inline u32 gr_gpc0_tpc0_pe_cfg_smid_r(void)
2200{
2201 return 0x00504088U;
2202}
2203static inline u32 gr_gpc0_tpc0_pe_cfg_smid_value_f(u32 v)
2204{
2205 return (v & 0xffffU) << 0U;
2206}
2207static inline u32 gr_gpc0_tpc0_l1c_cfg_smid_r(void)
2208{
2209 return 0x005044e8U;
2210}
2211static inline u32 gr_gpc0_tpc0_l1c_cfg_smid_value_f(u32 v)
2212{
2213 return (v & 0xffffU) << 0U;
2214}
2215static inline u32 gr_gpc0_tpc0_sm_cfg_r(void)
2216{
2217 return 0x00504698U;
2218}
2219static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_f(u32 v)
2220{
2221 return (v & 0xffffU) << 0U;
2222}
2223static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_v(u32 r)
2224{
2225 return (r >> 0U) & 0xffffU;
2226}
2227static inline u32 gr_gpc0_tpc0_sm_arch_r(void)
2228{
2229 return 0x0050469cU;
2230}
2231static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r)
2232{
2233 return (r >> 0U) & 0xffU;
2234}
2235static inline u32 gr_gpc0_tpc0_sm_arch_spa_version_v(u32 r)
2236{
2237 return (r >> 8U) & 0xfU;
2238}
2239static inline u32 gr_gpc0_tpc0_sm_arch_spa_version_smkepler_lp_v(void)
2240{
2241 return 0x0000000cU;
2242}
2243static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void)
2244{
2245 return 0x00503018U;
2246}
2247static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_m(void)
2248{
2249 return 0x1U << 0U;
2250}
2251static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f(void)
2252{
2253 return 0x1U;
2254}
2255static inline u32 gr_gpc0_ppc0_cbm_cfg_r(void)
2256{
2257 return 0x005030c0U;
2258}
2259static inline u32 gr_gpc0_ppc0_cbm_cfg_start_offset_f(u32 v)
2260{
2261 return (v & 0xffffU) << 0U;
2262}
2263static inline u32 gr_gpc0_ppc0_cbm_cfg_start_offset_m(void)
2264{
2265 return 0xffffU << 0U;
2266}
2267static inline u32 gr_gpc0_ppc0_cbm_cfg_start_offset_v(u32 r)
2268{
2269 return (r >> 0U) & 0xffffU;
2270}
2271static inline u32 gr_gpc0_ppc0_cbm_cfg_size_f(u32 v)
2272{
2273 return (v & 0xfffU) << 16U;
2274}
2275static inline u32 gr_gpc0_ppc0_cbm_cfg_size_m(void)
2276{
2277 return 0xfffU << 16U;
2278}
2279static inline u32 gr_gpc0_ppc0_cbm_cfg_size_v(u32 r)
2280{
2281 return (r >> 16U) & 0xfffU;
2282}
2283static inline u32 gr_gpc0_ppc0_cbm_cfg_size_default_v(void)
2284{
2285 return 0x00000240U;
2286}
2287static inline u32 gr_gpc0_ppc0_cbm_cfg_size_granularity_v(void)
2288{
2289 return 0x00000020U;
2290}
2291static inline u32 gr_gpc0_ppc0_cbm_cfg_timeslice_mode_f(u32 v)
2292{
2293 return (v & 0x1U) << 28U;
2294}
2295static inline u32 gr_gpc0_ppc0_cbm_cfg2_r(void)
2296{
2297 return 0x005030e4U;
2298}
2299static inline u32 gr_gpc0_ppc0_cbm_cfg2_start_offset_f(u32 v)
2300{
2301 return (v & 0xffffU) << 0U;
2302}
2303static inline u32 gr_gpc0_ppc0_cbm_cfg2_size_f(u32 v)
2304{
2305 return (v & 0xfffU) << 16U;
2306}
2307static inline u32 gr_gpc0_ppc0_cbm_cfg2_size_m(void)
2308{
2309 return 0xfffU << 16U;
2310}
2311static inline u32 gr_gpc0_ppc0_cbm_cfg2_size_v(u32 r)
2312{
2313 return (r >> 16U) & 0xfffU;
2314}
2315static inline u32 gr_gpc0_ppc0_cbm_cfg2_size_default_v(void)
2316{
2317 return 0x00000648U;
2318}
2319static inline u32 gr_gpc0_ppc0_cbm_cfg2_size_granularity_v(void)
2320{
2321 return 0x00000020U;
2322}
2323static inline u32 gr_gpccs_falcon_addr_r(void)
2324{
2325 return 0x0041a0acU;
2326}
2327static inline u32 gr_gpccs_falcon_addr_lsb_s(void)
2328{
2329 return 6U;
2330}
2331static inline u32 gr_gpccs_falcon_addr_lsb_f(u32 v)
2332{
2333 return (v & 0x3fU) << 0U;
2334}
2335static inline u32 gr_gpccs_falcon_addr_lsb_m(void)
2336{
2337 return 0x3fU << 0U;
2338}
2339static inline u32 gr_gpccs_falcon_addr_lsb_v(u32 r)
2340{
2341 return (r >> 0U) & 0x3fU;
2342}
2343static inline u32 gr_gpccs_falcon_addr_lsb_init_v(void)
2344{
2345 return 0x00000000U;
2346}
2347static inline u32 gr_gpccs_falcon_addr_lsb_init_f(void)
2348{
2349 return 0x0U;
2350}
2351static inline u32 gr_gpccs_falcon_addr_msb_s(void)
2352{
2353 return 6U;
2354}
2355static inline u32 gr_gpccs_falcon_addr_msb_f(u32 v)
2356{
2357 return (v & 0x3fU) << 6U;
2358}
2359static inline u32 gr_gpccs_falcon_addr_msb_m(void)
2360{
2361 return 0x3fU << 6U;
2362}
2363static inline u32 gr_gpccs_falcon_addr_msb_v(u32 r)
2364{
2365 return (r >> 6U) & 0x3fU;
2366}
2367static inline u32 gr_gpccs_falcon_addr_msb_init_v(void)
2368{
2369 return 0x00000000U;
2370}
2371static inline u32 gr_gpccs_falcon_addr_msb_init_f(void)
2372{
2373 return 0x0U;
2374}
2375static inline u32 gr_gpccs_falcon_addr_ext_s(void)
2376{
2377 return 12U;
2378}
2379static inline u32 gr_gpccs_falcon_addr_ext_f(u32 v)
2380{
2381 return (v & 0xfffU) << 0U;
2382}
2383static inline u32 gr_gpccs_falcon_addr_ext_m(void)
2384{
2385 return 0xfffU << 0U;
2386}
2387static inline u32 gr_gpccs_falcon_addr_ext_v(u32 r)
2388{
2389 return (r >> 0U) & 0xfffU;
2390}
2391static inline u32 gr_gpccs_cpuctl_r(void)
2392{
2393 return 0x0041a100U;
2394}
2395static inline u32 gr_gpccs_cpuctl_startcpu_f(u32 v)
2396{
2397 return (v & 0x1U) << 1U;
2398}
2399static inline u32 gr_gpccs_dmactl_r(void)
2400{
2401 return 0x0041a10cU;
2402}
2403static inline u32 gr_gpccs_dmactl_require_ctx_f(u32 v)
2404{
2405 return (v & 0x1U) << 0U;
2406}
2407static inline u32 gr_gpccs_dmactl_dmem_scrubbing_m(void)
2408{
2409 return 0x1U << 1U;
2410}
2411static inline u32 gr_gpccs_dmactl_imem_scrubbing_m(void)
2412{
2413 return 0x1U << 2U;
2414}
2415static inline u32 gr_gpccs_imemc_r(u32 i)
2416{
2417 return 0x0041a180U + i*16U;
2418}
2419static inline u32 gr_gpccs_imemc_offs_f(u32 v)
2420{
2421 return (v & 0x3fU) << 2U;
2422}
2423static inline u32 gr_gpccs_imemc_blk_f(u32 v)
2424{
2425 return (v & 0xffU) << 8U;
2426}
2427static inline u32 gr_gpccs_imemc_aincw_f(u32 v)
2428{
2429 return (v & 0x1U) << 24U;
2430}
2431static inline u32 gr_gpccs_imemd_r(u32 i)
2432{
2433 return 0x0041a184U + i*16U;
2434}
2435static inline u32 gr_gpccs_imemt_r(u32 i)
2436{
2437 return 0x0041a188U + i*16U;
2438}
2439static inline u32 gr_gpccs_imemt__size_1_v(void)
2440{
2441 return 0x00000004U;
2442}
2443static inline u32 gr_gpccs_imemt_tag_f(u32 v)
2444{
2445 return (v & 0xffffU) << 0U;
2446}
2447static inline u32 gr_gpccs_dmemc_r(u32 i)
2448{
2449 return 0x0041a1c0U + i*8U;
2450}
2451static inline u32 gr_gpccs_dmemc_offs_f(u32 v)
2452{
2453 return (v & 0x3fU) << 2U;
2454}
2455static inline u32 gr_gpccs_dmemc_blk_f(u32 v)
2456{
2457 return (v & 0xffU) << 8U;
2458}
2459static inline u32 gr_gpccs_dmemc_aincw_f(u32 v)
2460{
2461 return (v & 0x1U) << 24U;
2462}
2463static inline u32 gr_gpccs_dmemd_r(u32 i)
2464{
2465 return 0x0041a1c4U + i*8U;
2466}
2467static inline u32 gr_gpccs_ctxsw_mailbox_r(u32 i)
2468{
2469 return 0x0041a800U + i*4U;
2470}
2471static inline u32 gr_gpccs_ctxsw_mailbox_value_f(u32 v)
2472{
2473 return (v & 0xffffffffU) << 0U;
2474}
2475static inline u32 gr_gpcs_setup_bundle_cb_base_r(void)
2476{
2477 return 0x00418808U;
2478}
2479static inline u32 gr_gpcs_setup_bundle_cb_base_addr_39_8_s(void)
2480{
2481 return 32U;
2482}
2483static inline u32 gr_gpcs_setup_bundle_cb_base_addr_39_8_f(u32 v)
2484{
2485 return (v & 0xffffffffU) << 0U;
2486}
2487static inline u32 gr_gpcs_setup_bundle_cb_base_addr_39_8_m(void)
2488{
2489 return 0xffffffffU << 0U;
2490}
2491static inline u32 gr_gpcs_setup_bundle_cb_base_addr_39_8_v(u32 r)
2492{
2493 return (r >> 0U) & 0xffffffffU;
2494}
2495static inline u32 gr_gpcs_setup_bundle_cb_base_addr_39_8_init_v(void)
2496{
2497 return 0x00000000U;
2498}
2499static inline u32 gr_gpcs_setup_bundle_cb_base_addr_39_8_init_f(void)
2500{
2501 return 0x0U;
2502}
2503static inline u32 gr_gpcs_setup_bundle_cb_size_r(void)
2504{
2505 return 0x0041880cU;
2506}
2507static inline u32 gr_gpcs_setup_bundle_cb_size_div_256b_s(void)
2508{
2509 return 11U;
2510}
2511static inline u32 gr_gpcs_setup_bundle_cb_size_div_256b_f(u32 v)
2512{
2513 return (v & 0x7ffU) << 0U;
2514}
2515static inline u32 gr_gpcs_setup_bundle_cb_size_div_256b_m(void)
2516{
2517 return 0x7ffU << 0U;
2518}
2519static inline u32 gr_gpcs_setup_bundle_cb_size_div_256b_v(u32 r)
2520{
2521 return (r >> 0U) & 0x7ffU;
2522}
2523static inline u32 gr_gpcs_setup_bundle_cb_size_div_256b_init_v(void)
2524{
2525 return 0x00000000U;
2526}
2527static inline u32 gr_gpcs_setup_bundle_cb_size_div_256b_init_f(void)
2528{
2529 return 0x0U;
2530}
2531static inline u32 gr_gpcs_setup_bundle_cb_size_div_256b__prod_v(void)
2532{
2533 return 0x00000018U;
2534}
2535static inline u32 gr_gpcs_setup_bundle_cb_size_div_256b__prod_f(void)
2536{
2537 return 0x18U;
2538}
2539static inline u32 gr_gpcs_setup_bundle_cb_size_valid_s(void)
2540{
2541 return 1U;
2542}
2543static inline u32 gr_gpcs_setup_bundle_cb_size_valid_f(u32 v)
2544{
2545 return (v & 0x1U) << 31U;
2546}
2547static inline u32 gr_gpcs_setup_bundle_cb_size_valid_m(void)
2548{
2549 return 0x1U << 31U;
2550}
2551static inline u32 gr_gpcs_setup_bundle_cb_size_valid_v(u32 r)
2552{
2553 return (r >> 31U) & 0x1U;
2554}
2555static inline u32 gr_gpcs_setup_bundle_cb_size_valid_false_v(void)
2556{
2557 return 0x00000000U;
2558}
2559static inline u32 gr_gpcs_setup_bundle_cb_size_valid_false_f(void)
2560{
2561 return 0x0U;
2562}
2563static inline u32 gr_gpcs_setup_bundle_cb_size_valid_true_v(void)
2564{
2565 return 0x00000001U;
2566}
2567static inline u32 gr_gpcs_setup_bundle_cb_size_valid_true_f(void)
2568{
2569 return 0x80000000U;
2570}
2571static inline u32 gr_gpcs_setup_attrib_cb_base_r(void)
2572{
2573 return 0x00418810U;
2574}
2575static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_f(u32 v)
2576{
2577 return (v & 0xfffffffU) << 0U;
2578}
2579static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v(void)
2580{
2581 return 0x0000000cU;
2582}
2583static inline u32 gr_gpcs_setup_attrib_cb_base_valid_true_f(void)
2584{
2585 return 0x80000000U;
2586}
2587static inline u32 gr_crstr_gpc_map0_r(void)
2588{
2589 return 0x00418b08U;
2590}
2591static inline u32 gr_crstr_gpc_map0_tile0_f(u32 v)
2592{
2593 return (v & 0x7U) << 0U;
2594}
2595static inline u32 gr_crstr_gpc_map0_tile1_f(u32 v)
2596{
2597 return (v & 0x7U) << 5U;
2598}
2599static inline u32 gr_crstr_gpc_map0_tile2_f(u32 v)
2600{
2601 return (v & 0x7U) << 10U;
2602}
2603static inline u32 gr_crstr_gpc_map0_tile3_f(u32 v)
2604{
2605 return (v & 0x7U) << 15U;
2606}
2607static inline u32 gr_crstr_gpc_map0_tile4_f(u32 v)
2608{
2609 return (v & 0x7U) << 20U;
2610}
2611static inline u32 gr_crstr_gpc_map0_tile5_f(u32 v)
2612{
2613 return (v & 0x7U) << 25U;
2614}
2615static inline u32 gr_crstr_gpc_map1_r(void)
2616{
2617 return 0x00418b0cU;
2618}
2619static inline u32 gr_crstr_gpc_map1_tile6_f(u32 v)
2620{
2621 return (v & 0x7U) << 0U;
2622}
2623static inline u32 gr_crstr_gpc_map1_tile7_f(u32 v)
2624{
2625 return (v & 0x7U) << 5U;
2626}
2627static inline u32 gr_crstr_gpc_map1_tile8_f(u32 v)
2628{
2629 return (v & 0x7U) << 10U;
2630}
2631static inline u32 gr_crstr_gpc_map1_tile9_f(u32 v)
2632{
2633 return (v & 0x7U) << 15U;
2634}
2635static inline u32 gr_crstr_gpc_map1_tile10_f(u32 v)
2636{
2637 return (v & 0x7U) << 20U;
2638}
2639static inline u32 gr_crstr_gpc_map1_tile11_f(u32 v)
2640{
2641 return (v & 0x7U) << 25U;
2642}
2643static inline u32 gr_crstr_gpc_map2_r(void)
2644{
2645 return 0x00418b10U;
2646}
2647static inline u32 gr_crstr_gpc_map2_tile12_f(u32 v)
2648{
2649 return (v & 0x7U) << 0U;
2650}
2651static inline u32 gr_crstr_gpc_map2_tile13_f(u32 v)
2652{
2653 return (v & 0x7U) << 5U;
2654}
2655static inline u32 gr_crstr_gpc_map2_tile14_f(u32 v)
2656{
2657 return (v & 0x7U) << 10U;
2658}
2659static inline u32 gr_crstr_gpc_map2_tile15_f(u32 v)
2660{
2661 return (v & 0x7U) << 15U;
2662}
2663static inline u32 gr_crstr_gpc_map2_tile16_f(u32 v)
2664{
2665 return (v & 0x7U) << 20U;
2666}
2667static inline u32 gr_crstr_gpc_map2_tile17_f(u32 v)
2668{
2669 return (v & 0x7U) << 25U;
2670}
2671static inline u32 gr_crstr_gpc_map3_r(void)
2672{
2673 return 0x00418b14U;
2674}
2675static inline u32 gr_crstr_gpc_map3_tile18_f(u32 v)
2676{
2677 return (v & 0x7U) << 0U;
2678}
2679static inline u32 gr_crstr_gpc_map3_tile19_f(u32 v)
2680{
2681 return (v & 0x7U) << 5U;
2682}
2683static inline u32 gr_crstr_gpc_map3_tile20_f(u32 v)
2684{
2685 return (v & 0x7U) << 10U;
2686}
2687static inline u32 gr_crstr_gpc_map3_tile21_f(u32 v)
2688{
2689 return (v & 0x7U) << 15U;
2690}
2691static inline u32 gr_crstr_gpc_map3_tile22_f(u32 v)
2692{
2693 return (v & 0x7U) << 20U;
2694}
2695static inline u32 gr_crstr_gpc_map3_tile23_f(u32 v)
2696{
2697 return (v & 0x7U) << 25U;
2698}
2699static inline u32 gr_crstr_gpc_map4_r(void)
2700{
2701 return 0x00418b18U;
2702}
2703static inline u32 gr_crstr_gpc_map4_tile24_f(u32 v)
2704{
2705 return (v & 0x7U) << 0U;
2706}
2707static inline u32 gr_crstr_gpc_map4_tile25_f(u32 v)
2708{
2709 return (v & 0x7U) << 5U;
2710}
2711static inline u32 gr_crstr_gpc_map4_tile26_f(u32 v)
2712{
2713 return (v & 0x7U) << 10U;
2714}
2715static inline u32 gr_crstr_gpc_map4_tile27_f(u32 v)
2716{
2717 return (v & 0x7U) << 15U;
2718}
2719static inline u32 gr_crstr_gpc_map4_tile28_f(u32 v)
2720{
2721 return (v & 0x7U) << 20U;
2722}
2723static inline u32 gr_crstr_gpc_map4_tile29_f(u32 v)
2724{
2725 return (v & 0x7U) << 25U;
2726}
2727static inline u32 gr_crstr_gpc_map5_r(void)
2728{
2729 return 0x00418b1cU;
2730}
2731static inline u32 gr_crstr_gpc_map5_tile30_f(u32 v)
2732{
2733 return (v & 0x7U) << 0U;
2734}
2735static inline u32 gr_crstr_gpc_map5_tile31_f(u32 v)
2736{
2737 return (v & 0x7U) << 5U;
2738}
2739static inline u32 gr_crstr_gpc_map5_tile32_f(u32 v)
2740{
2741 return (v & 0x7U) << 10U;
2742}
2743static inline u32 gr_crstr_gpc_map5_tile33_f(u32 v)
2744{
2745 return (v & 0x7U) << 15U;
2746}
2747static inline u32 gr_crstr_gpc_map5_tile34_f(u32 v)
2748{
2749 return (v & 0x7U) << 20U;
2750}
2751static inline u32 gr_crstr_gpc_map5_tile35_f(u32 v)
2752{
2753 return (v & 0x7U) << 25U;
2754}
2755static inline u32 gr_crstr_map_table_cfg_r(void)
2756{
2757 return 0x00418bb8U;
2758}
2759static inline u32 gr_crstr_map_table_cfg_row_offset_f(u32 v)
2760{
2761 return (v & 0xffU) << 0U;
2762}
2763static inline u32 gr_crstr_map_table_cfg_num_entries_f(u32 v)
2764{
2765 return (v & 0xffU) << 8U;
2766}
2767static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_r(void)
2768{
2769 return 0x00418980U;
2770}
2771static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_0_f(u32 v)
2772{
2773 return (v & 0x7U) << 0U;
2774}
2775static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_1_f(u32 v)
2776{
2777 return (v & 0x7U) << 4U;
2778}
2779static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_2_f(u32 v)
2780{
2781 return (v & 0x7U) << 8U;
2782}
2783static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_3_f(u32 v)
2784{
2785 return (v & 0x7U) << 12U;
2786}
2787static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_4_f(u32 v)
2788{
2789 return (v & 0x7U) << 16U;
2790}
2791static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_5_f(u32 v)
2792{
2793 return (v & 0x7U) << 20U;
2794}
2795static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_6_f(u32 v)
2796{
2797 return (v & 0x7U) << 24U;
2798}
2799static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_7_f(u32 v)
2800{
2801 return (v & 0x7U) << 28U;
2802}
2803static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_r(void)
2804{
2805 return 0x00418984U;
2806}
2807static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_8_f(u32 v)
2808{
2809 return (v & 0x7U) << 0U;
2810}
2811static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_9_f(u32 v)
2812{
2813 return (v & 0x7U) << 4U;
2814}
2815static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_10_f(u32 v)
2816{
2817 return (v & 0x7U) << 8U;
2818}
2819static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_11_f(u32 v)
2820{
2821 return (v & 0x7U) << 12U;
2822}
2823static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_12_f(u32 v)
2824{
2825 return (v & 0x7U) << 16U;
2826}
2827static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_13_f(u32 v)
2828{
2829 return (v & 0x7U) << 20U;
2830}
2831static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_14_f(u32 v)
2832{
2833 return (v & 0x7U) << 24U;
2834}
2835static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_15_f(u32 v)
2836{
2837 return (v & 0x7U) << 28U;
2838}
2839static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_r(void)
2840{
2841 return 0x00418988U;
2842}
2843static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_16_f(u32 v)
2844{
2845 return (v & 0x7U) << 0U;
2846}
2847static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_17_f(u32 v)
2848{
2849 return (v & 0x7U) << 4U;
2850}
2851static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_18_f(u32 v)
2852{
2853 return (v & 0x7U) << 8U;
2854}
2855static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_19_f(u32 v)
2856{
2857 return (v & 0x7U) << 12U;
2858}
2859static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_20_f(u32 v)
2860{
2861 return (v & 0x7U) << 16U;
2862}
2863static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_21_f(u32 v)
2864{
2865 return (v & 0x7U) << 20U;
2866}
2867static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_22_f(u32 v)
2868{
2869 return (v & 0x7U) << 24U;
2870}
2871static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_s(void)
2872{
2873 return 3U;
2874}
2875static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_f(u32 v)
2876{
2877 return (v & 0x7U) << 28U;
2878}
2879static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_m(void)
2880{
2881 return 0x7U << 28U;
2882}
2883static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_v(u32 r)
2884{
2885 return (r >> 28U) & 0x7U;
2886}
2887static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_r(void)
2888{
2889 return 0x0041898cU;
2890}
2891static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_24_f(u32 v)
2892{
2893 return (v & 0x7U) << 0U;
2894}
2895static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_25_f(u32 v)
2896{
2897 return (v & 0x7U) << 4U;
2898}
2899static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_26_f(u32 v)
2900{
2901 return (v & 0x7U) << 8U;
2902}
2903static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_27_f(u32 v)
2904{
2905 return (v & 0x7U) << 12U;
2906}
2907static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_28_f(u32 v)
2908{
2909 return (v & 0x7U) << 16U;
2910}
2911static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_29_f(u32 v)
2912{
2913 return (v & 0x7U) << 20U;
2914}
2915static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_30_f(u32 v)
2916{
2917 return (v & 0x7U) << 24U;
2918}
2919static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_31_f(u32 v)
2920{
2921 return (v & 0x7U) << 28U;
2922}
2923static inline u32 gr_gpcs_gpm_pd_cfg_r(void)
2924{
2925 return 0x00418c6cU;
2926}
2927static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_disable_f(void)
2928{
2929 return 0x0U;
2930}
2931static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_enable_f(void)
2932{
2933 return 0x1U;
2934}
2935static inline u32 gr_gpcs_gcc_pagepool_base_r(void)
2936{
2937 return 0x00419004U;
2938}
2939static inline u32 gr_gpcs_gcc_pagepool_base_addr_39_8_f(u32 v)
2940{
2941 return (v & 0xffffffffU) << 0U;
2942}
2943static inline u32 gr_gpcs_gcc_pagepool_r(void)
2944{
2945 return 0x00419008U;
2946}
2947static inline u32 gr_gpcs_gcc_pagepool_total_pages_f(u32 v)
2948{
2949 return (v & 0xffU) << 0U;
2950}
2951static inline u32 gr_gpcs_tpcs_pe_vaf_r(void)
2952{
2953 return 0x0041980cU;
2954}
2955static inline u32 gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f(void)
2956{
2957 return 0x10U;
2958}
2959static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r(void)
2960{
2961 return 0x00419848U;
2962}
2963static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(u32 v)
2964{
2965 return (v & 0xfffffffU) << 0U;
2966}
2967static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(u32 v)
2968{
2969 return (v & 0x1U) << 28U;
2970}
2971static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f(void)
2972{
2973 return 0x10000000U;
2974}
2975static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_r(void)
2976{
2977 return 0x00419c00U;
2978}
2979static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f(void)
2980{
2981 return 0x0U;
2982}
2983static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f(void)
2984{
2985 return 0x8U;
2986}
2987static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r(void)
2988{
2989 return 0x00419e44U;
2990}
2991static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_error_report_f(void)
2992{
2993 return 0x2U;
2994}
2995static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_api_stack_error_report_f(void)
2996{
2997 return 0x4U;
2998}
2999static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_ret_empty_stack_error_report_f(void)
3000{
3001 return 0x8U;
3002}
3003static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_wrap_report_f(void)
3004{
3005 return 0x10U;
3006}
3007static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_pc_report_f(void)
3008{
3009 return 0x20U;
3010}
3011static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_overflow_report_f(void)
3012{
3013 return 0x40U;
3014}
3015static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_immc_addr_report_f(void)
3016{
3017 return 0x80U;
3018}
3019static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_reg_report_f(void)
3020{
3021 return 0x100U;
3022}
3023static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void)
3024{
3025 return 0x200U;
3026}
3027static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_sph_instr_combo_report_f(void)
3028{
3029 return 0x400U;
3030}
3031static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param_report_f(void)
3032{
3033 return 0x800U;
3034}
3035static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_report_f(void)
3036{
3037 return 0x1000U;
3038}
3039static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_reg_report_f(void)
3040{
3041 return 0x2000U;
3042}
3043static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_addr_report_f(void)
3044{
3045 return 0x4000U;
3046}
3047static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_addr_report_f(void)
3048{
3049 return 0x8000U;
3050}
3051static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_addr_space_report_f(void)
3052{
3053 return 0x10000U;
3054}
3055static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param2_report_f(void)
3056{
3057 return 0x20000U;
3058}
3059static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void)
3060{
3061 return 0x40000U;
3062}
3063static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_geometry_sm_error_report_f(void)
3064{
3065 return 0x80000U;
3066}
3067static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_divergent_report_f(void)
3068{
3069 return 0x100000U;
3070}
3071static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_r(void)
3072{
3073 return 0x00419e4cU;
3074}
3075static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_sm_to_sm_fault_report_f(void)
3076{
3077 return 0x1U;
3078}
3079static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_l1_error_report_f(void)
3080{
3081 return 0x2U;
3082}
3083static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_multiple_warp_errors_report_f(void)
3084{
3085 return 0x4U;
3086}
3087static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_physical_stack_overflow_error_report_f(void)
3088{
3089 return 0x8U;
3090}
3091static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_int_report_f(void)
3092{
3093 return 0x10U;
3094}
3095static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_pause_report_f(void)
3096{
3097 return 0x20U;
3098}
3099static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_single_step_complete_report_f(void)
3100{
3101 return 0x40U;
3102}
3103static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void)
3104{
3105 return 0x00419d0cU;
3106}
3107static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f(void)
3108{
3109 return 0x2U;
3110}
3111static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f(void)
3112{
3113 return 0x1U;
3114}
3115static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void)
3116{
3117 return 0x0050450cU;
3118}
3119static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(u32 r)
3120{
3121 return (r >> 1U) & 0x1U;
3122}
3123static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void)
3124{
3125 return 0x2U;
3126}
3127static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void)
3128{
3129 return 0x0041ac94U;
3130}
3131static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v)
3132{
3133 return (v & 0xffU) << 16U;
3134}
3135static inline u32 gr_gpc0_gpccs_gpc_exception_r(void)
3136{
3137 return 0x00502c90U;
3138}
3139static inline u32 gr_gpc0_gpccs_gpc_exception_gcc_v(u32 r)
3140{
3141 return (r >> 2U) & 0x1U;
3142}
3143static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r)
3144{
3145 return (r >> 16U) & 0xffU;
3146}
3147static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v(void)
3148{
3149 return 0x00000001U;
3150}
3151static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void)
3152{
3153 return 0x00504508U;
3154}
3155static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_v(u32 r)
3156{
3157 return (r >> 0U) & 0x1U;
3158}
3159static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_pending_v(void)
3160{
3161 return 0x00000001U;
3162}
3163static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r)
3164{
3165 return (r >> 1U) & 0x1U;
3166}
3167static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void)
3168{
3169 return 0x00000001U;
3170}
3171static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_r(void)
3172{
3173 return 0x00504610U;
3174}
3175static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_m(void)
3176{
3177 return 0x1U << 0U;
3178}
3179static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_v(u32 r)
3180{
3181 return (r >> 0U) & 0x1U;
3182}
3183static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_v(void)
3184{
3185 return 0x00000001U;
3186}
3187static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_f(void)
3188{
3189 return 0x1U;
3190}
3191static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_v(void)
3192{
3193 return 0x00000000U;
3194}
3195static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_f(void)
3196{
3197 return 0x0U;
3198}
3199static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_enable_f(void)
3200{
3201 return 0x80000000U;
3202}
3203static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_disable_f(void)
3204{
3205 return 0x0U;
3206}
3207static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_enable_f(void)
3208{
3209 return 0x8U;
3210}
3211static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_disable_f(void)
3212{
3213 return 0x0U;
3214}
3215static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void)
3216{
3217 return 0x40000000U;
3218}
3219static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_m(void)
3220{
3221 return 0x1U << 1U;
3222}
3223static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_v(u32 r)
3224{
3225 return (r >> 1U) & 0x1U;
3226}
3227static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_disable_f(void)
3228{
3229 return 0x0U;
3230}
3231static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_m(void)
3232{
3233 return 0x1U << 2U;
3234}
3235static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_v(u32 r)
3236{
3237 return (r >> 2U) & 0x1U;
3238}
3239static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_disable_f(void)
3240{
3241 return 0x0U;
3242}
3243static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_warp_disable_v(void)
3244{
3245 return 0x00000000U;
3246}
3247static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_sm_disable_v(void)
3248{
3249 return 0x00000000U;
3250}
3251static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_r(void)
3252{
3253 return 0x00504614U;
3254}
3255static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_1_r(void)
3256{
3257 return 0x00504618U;
3258}
3259static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r(void)
3260{
3261 return 0x00504624U;
3262}
3263static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_1_r(void)
3264{
3265 return 0x00504628U;
3266}
3267static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r(void)
3268{
3269 return 0x00504634U;
3270}
3271static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_1_r(void)
3272{
3273 return 0x00504638U;
3274}
3275static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_r(void)
3276{
3277 return 0x00419e24U;
3278}
3279static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void)
3280{
3281 return 0x0050460cU;
3282}
3283static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_sm_in_trap_mode_v(u32 r)
3284{
3285 return (r >> 0U) & 0x1U;
3286}
3287static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_v(u32 r)
3288{
3289 return (r >> 4U) & 0x1U;
3290}
3291static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_true_v(void)
3292{
3293 return 0x00000001U;
3294}
3295static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_r(void)
3296{
3297 return 0x00419e50U;
3298}
3299static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_int_pending_f(void)
3300{
3301 return 0x10U;
3302}
3303static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_pause_pending_f(void)
3304{
3305 return 0x20U;
3306}
3307static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_single_step_complete_pending_f(void)
3308{
3309 return 0x40U;
3310}
3311static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_sm_to_sm_fault_pending_f(void)
3312{
3313 return 0x1U;
3314}
3315static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_l1_error_pending_f(void)
3316{
3317 return 0x2U;
3318}
3319static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_multiple_warp_errors_pending_f(void)
3320{
3321 return 0x4U;
3322}
3323static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void)
3324{
3325 return 0x8U;
3326}
3327static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_timeout_error_pending_f(void)
3328{
3329 return 0x80000000U;
3330}
3331static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_r(void)
3332{
3333 return 0x00504650U;
3334}
3335static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f(void)
3336{
3337 return 0x10U;
3338}
3339static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_pause_pending_f(void)
3340{
3341 return 0x20U;
3342}
3343static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f(void)
3344{
3345 return 0x40U;
3346}
3347static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_sm_to_sm_fault_pending_f(void)
3348{
3349 return 0x1U;
3350}
3351static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_l1_error_pending_f(void)
3352{
3353 return 0x2U;
3354}
3355static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_multiple_warp_errors_pending_f(void)
3356{
3357 return 0x4U;
3358}
3359static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void)
3360{
3361 return 0x8U;
3362}
3363static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_timeout_error_pending_f(void)
3364{
3365 return 0x80000000U;
3366}
3367static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_r(void)
3368{
3369 return 0x00504224U;
3370}
3371static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_intr_pending_f(void)
3372{
3373 return 0x1U;
3374}
3375static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_r(void)
3376{
3377 return 0x00504648U;
3378}
3379static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_v(u32 r)
3380{
3381 return (r >> 0U) & 0xffffU;
3382}
3383static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_v(void)
3384{
3385 return 0x00000000U;
3386}
3387static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_f(void)
3388{
3389 return 0x0U;
3390}
3391static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void)
3392{
3393 return 0x00504770U;
3394}
3395static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void)
3396{
3397 return 0x00419f70U;
3398}
3399static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void)
3400{
3401 return 0x1U << 4U;
3402}
3403static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v)
3404{
3405 return (v & 0x1U) << 4U;
3406}
3407static inline u32 gr_gpc0_tpc0_sm_debug_sfe_control_r(void)
3408{
3409 return 0x0050477cU;
3410}
3411static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void)
3412{
3413 return 0x00419f7cU;
3414}
3415static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void)
3416{
3417 return 0x1U << 0U;
3418}
3419static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v)
3420{
3421 return (v & 0x1U) << 0U;
3422}
3423static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void)
3424{
3425 return 0x0041be08U;
3426}
3427static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f(void)
3428{
3429 return 0x4U;
3430}
3431static inline u32 gr_ppcs_wwdx_map_gpc_map0_r(void)
3432{
3433 return 0x0041bf00U;
3434}
3435static inline u32 gr_ppcs_wwdx_map_gpc_map1_r(void)
3436{
3437 return 0x0041bf04U;
3438}
3439static inline u32 gr_ppcs_wwdx_map_gpc_map2_r(void)
3440{
3441 return 0x0041bf08U;
3442}
3443static inline u32 gr_ppcs_wwdx_map_gpc_map3_r(void)
3444{
3445 return 0x0041bf0cU;
3446}
3447static inline u32 gr_ppcs_wwdx_map_gpc_map4_r(void)
3448{
3449 return 0x0041bf10U;
3450}
3451static inline u32 gr_ppcs_wwdx_map_gpc_map5_r(void)
3452{
3453 return 0x0041bf14U;
3454}
3455static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void)
3456{
3457 return 0x0041bfd0U;
3458}
3459static inline u32 gr_ppcs_wwdx_map_table_cfg_row_offset_f(u32 v)
3460{
3461 return (v & 0xffU) << 0U;
3462}
3463static inline u32 gr_ppcs_wwdx_map_table_cfg_num_entries_f(u32 v)
3464{
3465 return (v & 0xffU) << 8U;
3466}
3467static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(u32 v)
3468{
3469 return (v & 0x1fU) << 16U;
3470}
3471static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(u32 v)
3472{
3473 return (v & 0x7U) << 21U;
3474}
3475static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff5_mod_value_f(u32 v)
3476{
3477 return (v & 0x1fU) << 24U;
3478}
3479static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_r(void)
3480{
3481 return 0x0041bfd4U;
3482}
3483static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(u32 v)
3484{
3485 return (v & 0xffffffU) << 0U;
3486}
3487static inline u32 gr_ppcs_wwdx_map_table_cfg2_r(void)
3488{
3489 return 0x0041bfe4U;
3490}
3491static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff6_mod_value_f(u32 v)
3492{
3493 return (v & 0x1fU) << 0U;
3494}
3495static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff7_mod_value_f(u32 v)
3496{
3497 return (v & 0x1fU) << 5U;
3498}
3499static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff8_mod_value_f(u32 v)
3500{
3501 return (v & 0x1fU) << 10U;
3502}
3503static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff9_mod_value_f(u32 v)
3504{
3505 return (v & 0x1fU) << 15U;
3506}
3507static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff10_mod_value_f(u32 v)
3508{
3509 return (v & 0x1fU) << 20U;
3510}
3511static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff11_mod_value_f(u32 v)
3512{
3513 return (v & 0x1fU) << 25U;
3514}
3515static inline u32 gr_gpcs_ppcs_cbm_cfg_r(void)
3516{
3517 return 0x0041bec0U;
3518}
3519static inline u32 gr_gpcs_ppcs_cbm_cfg_timeslice_mode_enable_v(void)
3520{
3521 return 0x00000001U;
3522}
3523static inline u32 gr_bes_zrop_settings_r(void)
3524{
3525 return 0x00408850U;
3526}
3527static inline u32 gr_bes_zrop_settings_num_active_fbps_f(u32 v)
3528{
3529 return (v & 0xfU) << 0U;
3530}
3531static inline u32 gr_bes_crop_settings_r(void)
3532{
3533 return 0x00408958U;
3534}
3535static inline u32 gr_bes_crop_settings_num_active_fbps_f(u32 v)
3536{
3537 return (v & 0xfU) << 0U;
3538}
3539static inline u32 gr_zcull_bytes_per_aliquot_per_gpu_v(void)
3540{
3541 return 0x00000020U;
3542}
3543static inline u32 gr_zcull_save_restore_header_bytes_per_gpc_v(void)
3544{
3545 return 0x00000020U;
3546}
3547static inline u32 gr_zcull_save_restore_subregion_header_bytes_per_gpc_v(void)
3548{
3549 return 0x000000c0U;
3550}
3551static inline u32 gr_zcull_subregion_qty_v(void)
3552{
3553 return 0x00000010U;
3554}
3555static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel0_r(void)
3556{
3557 return 0x00504604U;
3558}
3559static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel1_r(void)
3560{
3561 return 0x00504608U;
3562}
3563static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control0_r(void)
3564{
3565 return 0x0050465cU;
3566}
3567static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control1_r(void)
3568{
3569 return 0x00504660U;
3570}
3571static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control2_r(void)
3572{
3573 return 0x00504664U;
3574}
3575static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control3_r(void)
3576{
3577 return 0x00504668U;
3578}
3579static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control4_r(void)
3580{
3581 return 0x0050466cU;
3582}
3583static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control5_r(void)
3584{
3585 return 0x00504658U;
3586}
3587static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status_r(void)
3588{
3589 return 0x00504670U;
3590}
3591static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status1_r(void)
3592{
3593 return 0x00504694U;
3594}
3595static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_control_r(void)
3596{
3597 return 0x00504730U;
3598}
3599static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_control_r(void)
3600{
3601 return 0x00504734U;
3602}
3603static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_control_r(void)
3604{
3605 return 0x00504738U;
3606}
3607static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_control_r(void)
3608{
3609 return 0x0050473cU;
3610}
3611static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter4_control_r(void)
3612{
3613 return 0x00504740U;
3614}
3615static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter5_control_r(void)
3616{
3617 return 0x00504744U;
3618}
3619static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter6_control_r(void)
3620{
3621 return 0x00504748U;
3622}
3623static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter7_control_r(void)
3624{
3625 return 0x0050474cU;
3626}
3627static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_r(void)
3628{
3629 return 0x00504674U;
3630}
3631static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_r(void)
3632{
3633 return 0x00504678U;
3634}
3635static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_r(void)
3636{
3637 return 0x0050467cU;
3638}
3639static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_r(void)
3640{
3641 return 0x00504680U;
3642}
3643static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter4_r(void)
3644{
3645 return 0x00504684U;
3646}
3647static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter5_r(void)
3648{
3649 return 0x00504688U;
3650}
3651static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter6_r(void)
3652{
3653 return 0x0050468cU;
3654}
3655static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter7_r(void)
3656{
3657 return 0x00504690U;
3658}
3659static inline u32 gr_fe_pwr_mode_r(void)
3660{
3661 return 0x00404170U;
3662}
3663static inline u32 gr_fe_pwr_mode_mode_auto_f(void)
3664{
3665 return 0x0U;
3666}
3667static inline u32 gr_fe_pwr_mode_mode_force_on_f(void)
3668{
3669 return 0x2U;
3670}
3671static inline u32 gr_fe_pwr_mode_req_v(u32 r)
3672{
3673 return (r >> 4U) & 0x1U;
3674}
3675static inline u32 gr_fe_pwr_mode_req_send_f(void)
3676{
3677 return 0x10U;
3678}
3679static inline u32 gr_fe_pwr_mode_req_done_v(void)
3680{
3681 return 0x00000000U;
3682}
3683static inline u32 gr_gpc0_tpc0_l1c_dbg_r(void)
3684{
3685 return 0x005044b0U;
3686}
3687static inline u32 gr_gpc0_tpc0_l1c_dbg_cya15_en_f(void)
3688{
3689 return 0x8000000U;
3690}
3691static inline u32 gr_gpcs_tpcs_sm_sch_texlock_r(void)
3692{
3693 return 0x00419ec8U;
3694}
3695static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_m(void)
3696{
3697 return 0x1U << 0U;
3698}
3699static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_disable_f(void)
3700{
3701 return 0x0U;
3702}
3703static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_tile_m(void)
3704{
3705 return 0x1U << 1U;
3706}
3707static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_tile_disable_f(void)
3708{
3709 return 0x0U;
3710}
3711static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_phase_m(void)
3712{
3713 return 0x1U << 2U;
3714}
3715static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_phase_disable_f(void)
3716{
3717 return 0x0U;
3718}
3719static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_tex_m(void)
3720{
3721 return 0x1U << 3U;
3722}
3723static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_tex_disable_f(void)
3724{
3725 return 0x0U;
3726}
3727static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_timeout_m(void)
3728{
3729 return 0xffU << 4U;
3730}
3731static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_timeout_disable_f(void)
3732{
3733 return 0x0U;
3734}
3735static inline u32 gr_gpcs_tpcs_sm_sch_texlock_dot_t_unlock_m(void)
3736{
3737 return 0x1U << 16U;
3738}
3739static inline u32 gr_gpcs_tpcs_sm_sch_texlock_dot_t_unlock_disable_f(void)
3740{
3741 return 0x0U;
3742}
3743static inline u32 gr_gpcs_tpcs_sm_sch_macro_sched_r(void)
3744{
3745 return 0x00419eacU;
3746}
3747static inline u32 gr_gpcs_tpcs_sm_sch_macro_sched_lockboost_size_f(u32 v)
3748{
3749 return (v & 0x1U) << 2U;
3750}
3751static inline u32 gr_gpcs_tpcs_sm_sch_macro_sched_lockboost_size_m(void)
3752{
3753 return 0x1U << 2U;
3754}
3755static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_r(void)
3756{
3757 return 0x00419e10U;
3758}
3759static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_f(u32 v)
3760{
3761 return (v & 0x1U) << 0U;
3762}
3763static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_on_v(void)
3764{
3765 return 0x00000001U;
3766}
3767static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_m(void)
3768{
3769 return 0x1U << 31U;
3770}
3771static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_v(u32 r)
3772{
3773 return (r >> 31U) & 0x1U;
3774}
3775static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_enable_f(void)
3776{
3777 return 0x80000000U;
3778}
3779static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f(void)
3780{
3781 return 0x0U;
3782}
3783static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_m(void)
3784{
3785 return 0x1U << 3U;
3786}
3787static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_enable_f(void)
3788{
3789 return 0x8U;
3790}
3791static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_disable_f(void)
3792{
3793 return 0x0U;
3794}
3795static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void)
3796{
3797 return 0x1U << 30U;
3798}
3799static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_v(u32 r)
3800{
3801 return (r >> 30U) & 0x1U;
3802}
3803static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f(void)
3804{
3805 return 0x40000000U;
3806}
3807#endif
diff --git a/include/gk20a/hw_ltc_gk20a.h b/include/gk20a/hw_ltc_gk20a.h
deleted file mode 100644
index efe7f98..0000000
--- a/include/gk20a/hw_ltc_gk20a.h
+++ /dev/null
@@ -1,455 +0,0 @@
1/*
2 * Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22/*
23 * Function naming determines intended use:
24 *
25 * <x>_r(void) : Returns the offset for register <x>.
26 *
27 * <x>_o(void) : Returns the offset for element <x>.
28 *
29 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
30 *
31 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
32 *
33 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
34 * and masked to place it at field <y> of register <x>. This value
35 * can be |'d with others to produce a full register value for
36 * register <x>.
37 *
38 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
39 * value can be ~'d and then &'d to clear the value of field <y> for
40 * register <x>.
41 *
42 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
43 * to place it at field <y> of register <x>. This value can be |'d
44 * with others to produce a full register value for <x>.
45 *
46 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
47 * <x> value 'r' after being shifted to place its LSB at bit 0.
48 * This value is suitable for direct comparison with other unshifted
49 * values appropriate for use in field <y> of register <x>.
50 *
51 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
52 * field <y> of register <x>. This value is suitable for direct
53 * comparison with unshifted values appropriate for use in field <y>
54 * of register <x>.
55 */
56#ifndef _hw_ltc_gk20a_h_
57#define _hw_ltc_gk20a_h_
58
59static inline u32 ltc_pltcg_base_v(void)
60{
61 return 0x00140000U;
62}
63static inline u32 ltc_pltcg_extent_v(void)
64{
65 return 0x0017ffffU;
66}
67static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void)
68{
69 return 0x001410c8U;
70}
71static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void)
72{
73 return 0x00141200U;
74}
75static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void)
76{
77 return 0x0017ea00U;
78}
79static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void)
80{
81 return 0x00141104U;
82}
83static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r)
84{
85 return (r >> 0U) & 0xffffU;
86}
87static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r)
88{
89 return (r >> 16U) & 0x3U;
90}
91static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void)
92{
93 return 0x00000000U;
94}
95static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void)
96{
97 return 0x00000001U;
98}
99static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void)
100{
101 return 0x00000002U;
102}
103static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void)
104{
105 return 0x0017e8c8U;
106}
107static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void)
108{
109 return 0x1U;
110}
111static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void)
112{
113 return 0x2U;
114}
115static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r)
116{
117 return (r >> 2U) & 0x1U;
118}
119static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void)
120{
121 return 0x00000001U;
122}
123static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void)
124{
125 return 0x4U;
126}
127static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void)
128{
129 return 0x001410c8U;
130}
131static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void)
132{
133 return 0x0017e8ccU;
134}
135static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v)
136{
137 return (v & 0x1ffffU) << 0U;
138}
139static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void)
140{
141 return 0x0017e8d0U;
142}
143static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v)
144{
145 return (v & 0x1ffffU) << 0U;
146}
147static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void)
148{
149 return 0x0001ffffU;
150}
151static inline u32 ltc_ltcs_ltss_cbc_base_r(void)
152{
153 return 0x0017e8d4U;
154}
155static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void)
156{
157 return 0x0000000bU;
158}
159static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r)
160{
161 return (r >> 0U) & 0x3ffffffU;
162}
163static inline u32 ltc_ltcs_ltss_cbc_param_r(void)
164{
165 return 0x0017e8dcU;
166}
167static inline u32 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(u32 r)
168{
169 return (r >> 0U) & 0xffffU;
170}
171static inline u32 ltc_ltcs_ltss_cbc_param_cache_line_size_v(u32 r)
172{
173 return (r >> 24U) & 0xfU;
174}
175static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_fbp_v(u32 r)
176{
177 return (r >> 28U) & 0xfU;
178}
179static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void)
180{
181 return 0x0017e91cU;
182}
183static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v)
184{
185 return (v & 0x1fU) << 16U;
186}
187static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void)
188{
189 return 0x0017ea44U;
190}
191static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v)
192{
193 return (v & 0xfU) << 0U;
194}
195static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i)
196{
197 return 0x0017ea48U + i*4U;
198}
199static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void)
200{
201 return 0x00000004U;
202}
203static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void)
204{
205 return 0x0017ea58U;
206}
207static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void)
208{
209 return 32U;
210}
211static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v)
212{
213 return (v & 0xffffffffU) << 0U;
214}
215static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void)
216{
217 return 0xffffffffU << 0U;
218}
219static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r)
220{
221 return (r >> 0U) & 0xffffffffU;
222}
223static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void)
224{
225 return 0x0017e924U;
226}
227static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void)
228{
229 return 0x10000000U;
230}
231static inline u32 ltc_ltcs_ltss_g_elpg_r(void)
232{
233 return 0x0017e828U;
234}
235static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r)
236{
237 return (r >> 0U) & 0x1U;
238}
239static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void)
240{
241 return 0x00000001U;
242}
243static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void)
244{
245 return 0x1U;
246}
247static inline u32 ltc_ltc0_ltss_g_elpg_r(void)
248{
249 return 0x00140828U;
250}
251static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r)
252{
253 return (r >> 0U) & 0x1U;
254}
255static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void)
256{
257 return 0x00000001U;
258}
259static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void)
260{
261 return 0x1U;
262}
263static inline u32 ltc_ltc0_ltss_intr_r(void)
264{
265 return 0x00140820U;
266}
267static inline u32 ltc_ltcs_ltss_intr_r(void)
268{
269 return 0x0017e820U;
270}
271static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void)
272{
273 return 0x1U << 20U;
274}
275static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_m(void)
276{
277 return 0x1U << 21U;
278}
279static inline u32 ltc_ltc0_lts0_intr_r(void)
280{
281 return 0x00141020U;
282}
283static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void)
284{
285 return 0x0017e910U;
286}
287static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r)
288{
289 return (r >> 0U) & 0x1U;
290}
291static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void)
292{
293 return 0x00000001U;
294}
295static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void)
296{
297 return 0x1U;
298}
299static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r)
300{
301 return (r >> 8U) & 0xfU;
302}
303static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void)
304{
305 return 0x00000003U;
306}
307static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void)
308{
309 return 0x300U;
310}
311static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r)
312{
313 return (r >> 28U) & 0x1U;
314}
315static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void)
316{
317 return 0x00000001U;
318}
319static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void)
320{
321 return 0x10000000U;
322}
323static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r)
324{
325 return (r >> 29U) & 0x1U;
326}
327static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void)
328{
329 return 0x00000001U;
330}
331static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void)
332{
333 return 0x20000000U;
334}
335static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r)
336{
337 return (r >> 30U) & 0x1U;
338}
339static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void)
340{
341 return 0x00000001U;
342}
343static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void)
344{
345 return 0x40000000U;
346}
347static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void)
348{
349 return 0x0017e914U;
350}
351static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r)
352{
353 return (r >> 0U) & 0x1U;
354}
355static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void)
356{
357 return 0x00000001U;
358}
359static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void)
360{
361 return 0x1U;
362}
363static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r)
364{
365 return (r >> 8U) & 0xfU;
366}
367static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void)
368{
369 return 0x00000003U;
370}
371static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void)
372{
373 return 0x300U;
374}
375static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r)
376{
377 return (r >> 16U) & 0x1U;
378}
379static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void)
380{
381 return 0x00000001U;
382}
383static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void)
384{
385 return 0x10000U;
386}
387static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r)
388{
389 return (r >> 28U) & 0x1U;
390}
391static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void)
392{
393 return 0x00000001U;
394}
395static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void)
396{
397 return 0x10000000U;
398}
399static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r)
400{
401 return (r >> 29U) & 0x1U;
402}
403static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void)
404{
405 return 0x00000001U;
406}
407static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void)
408{
409 return 0x20000000U;
410}
411static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r)
412{
413 return (r >> 30U) & 0x1U;
414}
415static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void)
416{
417 return 0x00000001U;
418}
419static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void)
420{
421 return 0x40000000U;
422}
423static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void)
424{
425 return 0x00140910U;
426}
427static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r)
428{
429 return (r >> 0U) & 0x1U;
430}
431static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void)
432{
433 return 0x00000001U;
434}
435static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void)
436{
437 return 0x1U;
438}
439static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void)
440{
441 return 0x00140914U;
442}
443static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r)
444{
445 return (r >> 0U) & 0x1U;
446}
447static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void)
448{
449 return 0x00000001U;
450}
451static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void)
452{
453 return 0x1U;
454}
455#endif
diff --git a/include/gk20a/hw_mc_gk20a.h b/include/gk20a/hw_mc_gk20a.h
deleted file mode 100644
index 3ca2a29..0000000
--- a/include/gk20a/hw_mc_gk20a.h
+++ /dev/null
@@ -1,291 +0,0 @@
1/*
2 * Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22/*
23 * Function naming determines intended use:
24 *
25 * <x>_r(void) : Returns the offset for register <x>.
26 *
27 * <x>_o(void) : Returns the offset for element <x>.
28 *
29 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
30 *
31 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
32 *
33 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
34 * and masked to place it at field <y> of register <x>. This value
35 * can be |'d with others to produce a full register value for
36 * register <x>.
37 *
38 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
39 * value can be ~'d and then &'d to clear the value of field <y> for
40 * register <x>.
41 *
42 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
43 * to place it at field <y> of register <x>. This value can be |'d
44 * with others to produce a full register value for <x>.
45 *
46 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
47 * <x> value 'r' after being shifted to place its LSB at bit 0.
48 * This value is suitable for direct comparison with other unshifted
49 * values appropriate for use in field <y> of register <x>.
50 *
51 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
52 * field <y> of register <x>. This value is suitable for direct
53 * comparison with unshifted values appropriate for use in field <y>
54 * of register <x>.
55 */
56#ifndef _hw_mc_gk20a_h_
57#define _hw_mc_gk20a_h_
58
59static inline u32 mc_boot_0_r(void)
60{
61 return 0x00000000U;
62}
63static inline u32 mc_boot_0_architecture_v(u32 r)
64{
65 return (r >> 24U) & 0x1fU;
66}
67static inline u32 mc_boot_0_implementation_v(u32 r)
68{
69 return (r >> 20U) & 0xfU;
70}
71static inline u32 mc_boot_0_major_revision_v(u32 r)
72{
73 return (r >> 4U) & 0xfU;
74}
75static inline u32 mc_boot_0_minor_revision_v(u32 r)
76{
77 return (r >> 0U) & 0xfU;
78}
79static inline u32 mc_intr_0_r(void)
80{
81 return 0x00000100U;
82}
83static inline u32 mc_intr_0_pfifo_pending_f(void)
84{
85 return 0x100U;
86}
87static inline u32 mc_intr_0_pgraph_pending_f(void)
88{
89 return 0x1000U;
90}
91static inline u32 mc_intr_0_pmu_pending_f(void)
92{
93 return 0x1000000U;
94}
95static inline u32 mc_intr_0_ltc_pending_f(void)
96{
97 return 0x2000000U;
98}
99static inline u32 mc_intr_0_priv_ring_pending_f(void)
100{
101 return 0x40000000U;
102}
103static inline u32 mc_intr_0_pbus_pending_f(void)
104{
105 return 0x10000000U;
106}
107static inline u32 mc_intr_1_r(void)
108{
109 return 0x00000104U;
110}
111static inline u32 mc_intr_mask_0_r(void)
112{
113 return 0x00000640U;
114}
115static inline u32 mc_intr_mask_0_pmu_enabled_f(void)
116{
117 return 0x1000000U;
118}
119static inline u32 mc_intr_en_0_r(void)
120{
121 return 0x00000140U;
122}
123static inline u32 mc_intr_en_0_inta_disabled_f(void)
124{
125 return 0x0U;
126}
127static inline u32 mc_intr_en_0_inta_hardware_f(void)
128{
129 return 0x1U;
130}
131static inline u32 mc_intr_mask_1_r(void)
132{
133 return 0x00000644U;
134}
135static inline u32 mc_intr_mask_1_pmu_s(void)
136{
137 return 1U;
138}
139static inline u32 mc_intr_mask_1_pmu_f(u32 v)
140{
141 return (v & 0x1U) << 24U;
142}
143static inline u32 mc_intr_mask_1_pmu_m(void)
144{
145 return 0x1U << 24U;
146}
147static inline u32 mc_intr_mask_1_pmu_v(u32 r)
148{
149 return (r >> 24U) & 0x1U;
150}
151static inline u32 mc_intr_mask_1_pmu_enabled_f(void)
152{
153 return 0x1000000U;
154}
155static inline u32 mc_intr_en_1_r(void)
156{
157 return 0x00000144U;
158}
159static inline u32 mc_intr_en_1_inta_disabled_f(void)
160{
161 return 0x0U;
162}
163static inline u32 mc_intr_en_1_inta_hardware_f(void)
164{
165 return 0x1U;
166}
167static inline u32 mc_enable_r(void)
168{
169 return 0x00000200U;
170}
171static inline u32 mc_enable_xbar_enabled_f(void)
172{
173 return 0x4U;
174}
175static inline u32 mc_enable_l2_enabled_f(void)
176{
177 return 0x8U;
178}
179static inline u32 mc_enable_pmedia_s(void)
180{
181 return 1U;
182}
183static inline u32 mc_enable_pmedia_f(u32 v)
184{
185 return (v & 0x1U) << 4U;
186}
187static inline u32 mc_enable_pmedia_m(void)
188{
189 return 0x1U << 4U;
190}
191static inline u32 mc_enable_pmedia_v(u32 r)
192{
193 return (r >> 4U) & 0x1U;
194}
195static inline u32 mc_enable_priv_ring_enabled_f(void)
196{
197 return 0x20U;
198}
199static inline u32 mc_enable_ce0_m(void)
200{
201 return 0x1U << 6U;
202}
203static inline u32 mc_enable_pfifo_enabled_f(void)
204{
205 return 0x100U;
206}
207static inline u32 mc_enable_pgraph_enabled_f(void)
208{
209 return 0x1000U;
210}
211static inline u32 mc_enable_pwr_v(u32 r)
212{
213 return (r >> 13U) & 0x1U;
214}
215static inline u32 mc_enable_pwr_disabled_v(void)
216{
217 return 0x00000000U;
218}
219static inline u32 mc_enable_pwr_enabled_f(void)
220{
221 return 0x2000U;
222}
223static inline u32 mc_enable_pfb_enabled_f(void)
224{
225 return 0x100000U;
226}
227static inline u32 mc_enable_ce2_m(void)
228{
229 return 0x1U << 21U;
230}
231static inline u32 mc_enable_ce2_enabled_f(void)
232{
233 return 0x200000U;
234}
235static inline u32 mc_enable_blg_enabled_f(void)
236{
237 return 0x8000000U;
238}
239static inline u32 mc_enable_perfmon_enabled_f(void)
240{
241 return 0x10000000U;
242}
243static inline u32 mc_enable_hub_enabled_f(void)
244{
245 return 0x20000000U;
246}
247static inline u32 mc_enable_pb_r(void)
248{
249 return 0x00000204U;
250}
251static inline u32 mc_enable_pb_0_s(void)
252{
253 return 1U;
254}
255static inline u32 mc_enable_pb_0_f(u32 v)
256{
257 return (v & 0x1U) << 0U;
258}
259static inline u32 mc_enable_pb_0_m(void)
260{
261 return 0x1U << 0U;
262}
263static inline u32 mc_enable_pb_0_v(u32 r)
264{
265 return (r >> 0U) & 0x1U;
266}
267static inline u32 mc_enable_pb_0_enabled_v(void)
268{
269 return 0x00000001U;
270}
271static inline u32 mc_enable_pb_sel_f(u32 v, u32 i)
272{
273 return (v & 0x1U) << (0U + i*1U);
274}
275static inline u32 mc_elpg_enable_r(void)
276{
277 return 0x0000020cU;
278}
279static inline u32 mc_elpg_enable_xbar_enabled_f(void)
280{
281 return 0x4U;
282}
283static inline u32 mc_elpg_enable_pfb_enabled_f(void)
284{
285 return 0x100000U;
286}
287static inline u32 mc_elpg_enable_hub_enabled_f(void)
288{
289 return 0x20000000U;
290}
291#endif
diff --git a/include/gk20a/hw_pbdma_gk20a.h b/include/gk20a/hw_pbdma_gk20a.h
deleted file mode 100644
index 2c8f48d..0000000
--- a/include/gk20a/hw_pbdma_gk20a.h
+++ /dev/null
@@ -1,575 +0,0 @@
1/*
2 * Copyright (c) 2012-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22/*
23 * Function naming determines intended use:
24 *
25 * <x>_r(void) : Returns the offset for register <x>.
26 *
27 * <x>_o(void) : Returns the offset for element <x>.
28 *
29 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
30 *
31 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
32 *
33 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
34 * and masked to place it at field <y> of register <x>. This value
35 * can be |'d with others to produce a full register value for
36 * register <x>.
37 *
38 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
39 * value can be ~'d and then &'d to clear the value of field <y> for
40 * register <x>.
41 *
42 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
43 * to place it at field <y> of register <x>. This value can be |'d
44 * with others to produce a full register value for <x>.
45 *
46 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
47 * <x> value 'r' after being shifted to place its LSB at bit 0.
48 * This value is suitable for direct comparison with other unshifted
49 * values appropriate for use in field <y> of register <x>.
50 *
51 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
52 * field <y> of register <x>. This value is suitable for direct
53 * comparison with unshifted values appropriate for use in field <y>
54 * of register <x>.
55 */
56#ifndef _hw_pbdma_gk20a_h_
57#define _hw_pbdma_gk20a_h_
58
59static inline u32 pbdma_gp_entry1_r(void)
60{
61 return 0x10000004U;
62}
63static inline u32 pbdma_gp_entry1_get_hi_v(u32 r)
64{
65 return (r >> 0U) & 0xffU;
66}
67static inline u32 pbdma_gp_entry1_length_f(u32 v)
68{
69 return (v & 0x1fffffU) << 10U;
70}
71static inline u32 pbdma_gp_entry1_length_v(u32 r)
72{
73 return (r >> 10U) & 0x1fffffU;
74}
75static inline u32 pbdma_gp_base_r(u32 i)
76{
77 return 0x00040048U + i*8192U;
78}
79static inline u32 pbdma_gp_base__size_1_v(void)
80{
81 return 0x00000001U;
82}
83static inline u32 pbdma_gp_base_offset_f(u32 v)
84{
85 return (v & 0x1fffffffU) << 3U;
86}
87static inline u32 pbdma_gp_base_rsvd_s(void)
88{
89 return 3U;
90}
91static inline u32 pbdma_gp_base_hi_r(u32 i)
92{
93 return 0x0004004cU + i*8192U;
94}
95static inline u32 pbdma_gp_base_hi_offset_f(u32 v)
96{
97 return (v & 0xffU) << 0U;
98}
99static inline u32 pbdma_gp_base_hi_limit2_f(u32 v)
100{
101 return (v & 0x1fU) << 16U;
102}
103static inline u32 pbdma_gp_fetch_r(u32 i)
104{
105 return 0x00040050U + i*8192U;
106}
107static inline u32 pbdma_gp_get_r(u32 i)
108{
109 return 0x00040014U + i*8192U;
110}
111static inline u32 pbdma_gp_put_r(u32 i)
112{
113 return 0x00040000U + i*8192U;
114}
115static inline u32 pbdma_timeout_r(u32 i)
116{
117 return 0x0004012cU + i*8192U;
118}
119static inline u32 pbdma_timeout__size_1_v(void)
120{
121 return 0x00000001U;
122}
123static inline u32 pbdma_timeout_period_m(void)
124{
125 return 0xffffffffU << 0U;
126}
127static inline u32 pbdma_timeout_period_max_f(void)
128{
129 return 0xffffffffU;
130}
131static inline u32 pbdma_pb_fetch_r(u32 i)
132{
133 return 0x00040054U + i*8192U;
134}
135static inline u32 pbdma_pb_fetch_hi_r(u32 i)
136{
137 return 0x00040058U + i*8192U;
138}
139static inline u32 pbdma_get_r(u32 i)
140{
141 return 0x00040018U + i*8192U;
142}
143static inline u32 pbdma_get_hi_r(u32 i)
144{
145 return 0x0004001cU + i*8192U;
146}
147static inline u32 pbdma_put_r(u32 i)
148{
149 return 0x0004005cU + i*8192U;
150}
151static inline u32 pbdma_put_hi_r(u32 i)
152{
153 return 0x00040060U + i*8192U;
154}
155static inline u32 pbdma_formats_r(u32 i)
156{
157 return 0x0004009cU + i*8192U;
158}
159static inline u32 pbdma_formats_gp_fermi0_f(void)
160{
161 return 0x0U;
162}
163static inline u32 pbdma_formats_pb_fermi1_f(void)
164{
165 return 0x100U;
166}
167static inline u32 pbdma_formats_mp_fermi0_f(void)
168{
169 return 0x0U;
170}
171static inline u32 pbdma_pb_header_r(u32 i)
172{
173 return 0x00040084U + i*8192U;
174}
175static inline u32 pbdma_pb_header_priv_user_f(void)
176{
177 return 0x0U;
178}
179static inline u32 pbdma_pb_header_method_zero_f(void)
180{
181 return 0x0U;
182}
183static inline u32 pbdma_pb_header_subchannel_zero_f(void)
184{
185 return 0x0U;
186}
187static inline u32 pbdma_pb_header_level_main_f(void)
188{
189 return 0x0U;
190}
191static inline u32 pbdma_pb_header_first_true_f(void)
192{
193 return 0x400000U;
194}
195static inline u32 pbdma_pb_header_type_inc_f(void)
196{
197 return 0x20000000U;
198}
199static inline u32 pbdma_pb_header_type_non_inc_f(void)
200{
201 return 0x60000000U;
202}
203static inline u32 pbdma_hdr_shadow_r(u32 i)
204{
205 return 0x00040118U + i*8192U;
206}
207static inline u32 pbdma_gp_shadow_0_r(u32 i)
208{
209 return 0x00040110U + i*8192U;
210}
211static inline u32 pbdma_gp_shadow_1_r(u32 i)
212{
213 return 0x00040114U + i*8192U;
214}
215static inline u32 pbdma_subdevice_r(u32 i)
216{
217 return 0x00040094U + i*8192U;
218}
219static inline u32 pbdma_subdevice_id_f(u32 v)
220{
221 return (v & 0xfffU) << 0U;
222}
223static inline u32 pbdma_subdevice_status_active_f(void)
224{
225 return 0x10000000U;
226}
227static inline u32 pbdma_subdevice_channel_dma_enable_f(void)
228{
229 return 0x20000000U;
230}
231static inline u32 pbdma_method0_r(u32 i)
232{
233 return 0x000400c0U + i*8192U;
234}
235static inline u32 pbdma_method0_addr_f(u32 v)
236{
237 return (v & 0xfffU) << 2U;
238}
239static inline u32 pbdma_method0_addr_v(u32 r)
240{
241 return (r >> 2U) & 0xfffU;
242}
243static inline u32 pbdma_method0_subch_v(u32 r)
244{
245 return (r >> 16U) & 0x7U;
246}
247static inline u32 pbdma_method0_first_true_f(void)
248{
249 return 0x400000U;
250}
251static inline u32 pbdma_method0_valid_true_f(void)
252{
253 return 0x80000000U;
254}
255static inline u32 pbdma_method1_r(u32 i)
256{
257 return 0x000400c8U + i*8192U;
258}
259static inline u32 pbdma_method2_r(u32 i)
260{
261 return 0x000400d0U + i*8192U;
262}
263static inline u32 pbdma_method3_r(u32 i)
264{
265 return 0x000400d8U + i*8192U;
266}
267static inline u32 pbdma_data0_r(u32 i)
268{
269 return 0x000400c4U + i*8192U;
270}
271static inline u32 pbdma_target_r(u32 i)
272{
273 return 0x000400acU + i*8192U;
274}
275static inline u32 pbdma_target_engine_sw_f(void)
276{
277 return 0x1fU;
278}
279static inline u32 pbdma_acquire_r(u32 i)
280{
281 return 0x00040030U + i*8192U;
282}
283static inline u32 pbdma_acquire_retry_man_2_f(void)
284{
285 return 0x2U;
286}
287static inline u32 pbdma_acquire_retry_exp_2_f(void)
288{
289 return 0x100U;
290}
291static inline u32 pbdma_acquire_timeout_exp_f(u32 v)
292{
293 return (v & 0xfU) << 11U;
294}
295static inline u32 pbdma_acquire_timeout_exp_max_v(void)
296{
297 return 0x0000000fU;
298}
299static inline u32 pbdma_acquire_timeout_exp_max_f(void)
300{
301 return 0x7800U;
302}
303static inline u32 pbdma_acquire_timeout_man_f(u32 v)
304{
305 return (v & 0xffffU) << 15U;
306}
307static inline u32 pbdma_acquire_timeout_man_max_v(void)
308{
309 return 0x0000ffffU;
310}
311static inline u32 pbdma_acquire_timeout_man_max_f(void)
312{
313 return 0x7fff8000U;
314}
315static inline u32 pbdma_acquire_timeout_en_enable_f(void)
316{
317 return 0x80000000U;
318}
319static inline u32 pbdma_acquire_timeout_en_disable_f(void)
320{
321 return 0x0U;
322}
323static inline u32 pbdma_status_r(u32 i)
324{
325 return 0x00040100U + i*8192U;
326}
327static inline u32 pbdma_channel_r(u32 i)
328{
329 return 0x00040120U + i*8192U;
330}
331static inline u32 pbdma_signature_r(u32 i)
332{
333 return 0x00040010U + i*8192U;
334}
335static inline u32 pbdma_signature_hw_valid_f(void)
336{
337 return 0xfaceU;
338}
339static inline u32 pbdma_signature_sw_zero_f(void)
340{
341 return 0x0U;
342}
343static inline u32 pbdma_userd_r(u32 i)
344{
345 return 0x00040008U + i*8192U;
346}
347static inline u32 pbdma_userd_target_vid_mem_f(void)
348{
349 return 0x0U;
350}
351static inline u32 pbdma_userd_target_sys_mem_coh_f(void)
352{
353 return 0x2U;
354}
355static inline u32 pbdma_userd_target_sys_mem_ncoh_f(void)
356{
357 return 0x3U;
358}
359static inline u32 pbdma_userd_addr_f(u32 v)
360{
361 return (v & 0x7fffffU) << 9U;
362}
363static inline u32 pbdma_userd_hi_r(u32 i)
364{
365 return 0x0004000cU + i*8192U;
366}
367static inline u32 pbdma_userd_hi_addr_f(u32 v)
368{
369 return (v & 0xffU) << 0U;
370}
371static inline u32 pbdma_hce_ctrl_r(u32 i)
372{
373 return 0x000400e4U + i*8192U;
374}
375static inline u32 pbdma_hce_ctrl_hce_priv_mode_yes_f(void)
376{
377 return 0x20U;
378}
379static inline u32 pbdma_intr_0_r(u32 i)
380{
381 return 0x00040108U + i*8192U;
382}
383static inline u32 pbdma_intr_0_memreq_v(u32 r)
384{
385 return (r >> 0U) & 0x1U;
386}
387static inline u32 pbdma_intr_0_memreq_pending_f(void)
388{
389 return 0x1U;
390}
391static inline u32 pbdma_intr_0_memack_timeout_pending_f(void)
392{
393 return 0x2U;
394}
395static inline u32 pbdma_intr_0_memack_extra_pending_f(void)
396{
397 return 0x4U;
398}
399static inline u32 pbdma_intr_0_memdat_timeout_pending_f(void)
400{
401 return 0x8U;
402}
403static inline u32 pbdma_intr_0_memdat_extra_pending_f(void)
404{
405 return 0x10U;
406}
407static inline u32 pbdma_intr_0_memflush_pending_f(void)
408{
409 return 0x20U;
410}
411static inline u32 pbdma_intr_0_memop_pending_f(void)
412{
413 return 0x40U;
414}
415static inline u32 pbdma_intr_0_lbconnect_pending_f(void)
416{
417 return 0x80U;
418}
419static inline u32 pbdma_intr_0_lbreq_pending_f(void)
420{
421 return 0x100U;
422}
423static inline u32 pbdma_intr_0_lback_timeout_pending_f(void)
424{
425 return 0x200U;
426}
427static inline u32 pbdma_intr_0_lback_extra_pending_f(void)
428{
429 return 0x400U;
430}
431static inline u32 pbdma_intr_0_lbdat_timeout_pending_f(void)
432{
433 return 0x800U;
434}
435static inline u32 pbdma_intr_0_lbdat_extra_pending_f(void)
436{
437 return 0x1000U;
438}
439static inline u32 pbdma_intr_0_gpfifo_pending_f(void)
440{
441 return 0x2000U;
442}
443static inline u32 pbdma_intr_0_gpptr_pending_f(void)
444{
445 return 0x4000U;
446}
447static inline u32 pbdma_intr_0_gpentry_pending_f(void)
448{
449 return 0x8000U;
450}
451static inline u32 pbdma_intr_0_gpcrc_pending_f(void)
452{
453 return 0x10000U;
454}
455static inline u32 pbdma_intr_0_pbptr_pending_f(void)
456{
457 return 0x20000U;
458}
459static inline u32 pbdma_intr_0_pbentry_pending_f(void)
460{
461 return 0x40000U;
462}
463static inline u32 pbdma_intr_0_pbcrc_pending_f(void)
464{
465 return 0x80000U;
466}
467static inline u32 pbdma_intr_0_xbarconnect_pending_f(void)
468{
469 return 0x100000U;
470}
471static inline u32 pbdma_intr_0_method_pending_f(void)
472{
473 return 0x200000U;
474}
475static inline u32 pbdma_intr_0_methodcrc_pending_f(void)
476{
477 return 0x400000U;
478}
479static inline u32 pbdma_intr_0_device_pending_f(void)
480{
481 return 0x800000U;
482}
483static inline u32 pbdma_intr_0_semaphore_pending_f(void)
484{
485 return 0x2000000U;
486}
487static inline u32 pbdma_intr_0_acquire_pending_f(void)
488{
489 return 0x4000000U;
490}
491static inline u32 pbdma_intr_0_pri_pending_f(void)
492{
493 return 0x8000000U;
494}
495static inline u32 pbdma_intr_0_no_ctxsw_seg_pending_f(void)
496{
497 return 0x20000000U;
498}
499static inline u32 pbdma_intr_0_pbseg_pending_f(void)
500{
501 return 0x40000000U;
502}
503static inline u32 pbdma_intr_0_signature_pending_f(void)
504{
505 return 0x80000000U;
506}
507static inline u32 pbdma_intr_1_r(u32 i)
508{
509 return 0x00040148U + i*8192U;
510}
511static inline u32 pbdma_intr_en_0_r(u32 i)
512{
513 return 0x0004010cU + i*8192U;
514}
515static inline u32 pbdma_intr_en_0_lbreq_enabled_f(void)
516{
517 return 0x100U;
518}
519static inline u32 pbdma_intr_en_1_r(u32 i)
520{
521 return 0x0004014cU + i*8192U;
522}
523static inline u32 pbdma_intr_stall_r(u32 i)
524{
525 return 0x0004013cU + i*8192U;
526}
527static inline u32 pbdma_intr_stall_lbreq_enabled_f(void)
528{
529 return 0x100U;
530}
531static inline u32 pbdma_intr_stall_1_r(u32 i)
532{
533 return 0x00040140U + i*8192U;
534}
535static inline u32 pbdma_intr_stall_1_hce_illegal_op_enabled_f(void)
536{
537 return 0x1U;
538}
539static inline u32 pbdma_udma_nop_r(void)
540{
541 return 0x00000008U;
542}
543static inline u32 pbdma_syncpointa_r(u32 i)
544{
545 return 0x000400a4U + i*8192U;
546}
547static inline u32 pbdma_syncpointa_payload_v(u32 r)
548{
549 return (r >> 0U) & 0xffffffffU;
550}
551static inline u32 pbdma_syncpointb_r(u32 i)
552{
553 return 0x000400a8U + i*8192U;
554}
555static inline u32 pbdma_syncpointb_op_v(u32 r)
556{
557 return (r >> 0U) & 0x3U;
558}
559static inline u32 pbdma_syncpointb_op_wait_v(void)
560{
561 return 0x00000000U;
562}
563static inline u32 pbdma_syncpointb_wait_switch_v(u32 r)
564{
565 return (r >> 4U) & 0x1U;
566}
567static inline u32 pbdma_syncpointb_wait_switch_en_v(void)
568{
569 return 0x00000001U;
570}
571static inline u32 pbdma_syncpointb_syncpt_index_v(u32 r)
572{
573 return (r >> 8U) & 0xffU;
574}
575#endif
diff --git a/include/gk20a/hw_perf_gk20a.h b/include/gk20a/hw_perf_gk20a.h
deleted file mode 100644
index a93560f..0000000
--- a/include/gk20a/hw_perf_gk20a.h
+++ /dev/null
@@ -1,211 +0,0 @@
1/*
2 * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22/*
23 * Function naming determines intended use:
24 *
25 * <x>_r(void) : Returns the offset for register <x>.
26 *
27 * <x>_o(void) : Returns the offset for element <x>.
28 *
29 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
30 *
31 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
32 *
33 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
34 * and masked to place it at field <y> of register <x>. This value
35 * can be |'d with others to produce a full register value for
36 * register <x>.
37 *
38 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
39 * value can be ~'d and then &'d to clear the value of field <y> for
40 * register <x>.
41 *
42 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
43 * to place it at field <y> of register <x>. This value can be |'d
44 * with others to produce a full register value for <x>.
45 *
46 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
47 * <x> value 'r' after being shifted to place its LSB at bit 0.
48 * This value is suitable for direct comparison with other unshifted
49 * values appropriate for use in field <y> of register <x>.
50 *
51 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
52 * field <y> of register <x>. This value is suitable for direct
53 * comparison with unshifted values appropriate for use in field <y>
54 * of register <x>.
55 */
56#ifndef _hw_perf_gk20a_h_
57#define _hw_perf_gk20a_h_
58
59static inline u32 perf_pmasys_control_r(void)
60{
61 return 0x001b4000U;
62}
63static inline u32 perf_pmasys_control_membuf_status_v(u32 r)
64{
65 return (r >> 4U) & 0x1U;
66}
67static inline u32 perf_pmasys_control_membuf_status_overflowed_v(void)
68{
69 return 0x00000001U;
70}
71static inline u32 perf_pmasys_control_membuf_status_overflowed_f(void)
72{
73 return 0x10U;
74}
75static inline u32 perf_pmasys_control_membuf_clear_status_f(u32 v)
76{
77 return (v & 0x1U) << 5U;
78}
79static inline u32 perf_pmasys_control_membuf_clear_status_v(u32 r)
80{
81 return (r >> 5U) & 0x1U;
82}
83static inline u32 perf_pmasys_control_membuf_clear_status_doit_v(void)
84{
85 return 0x00000001U;
86}
87static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void)
88{
89 return 0x20U;
90}
91static inline u32 perf_pmasys_mem_block_r(void)
92{
93 return 0x001b4070U;
94}
95static inline u32 perf_pmasys_mem_block_base_f(u32 v)
96{
97 return (v & 0xfffffffU) << 0U;
98}
99static inline u32 perf_pmasys_mem_block_target_f(u32 v)
100{
101 return (v & 0x3U) << 28U;
102}
103static inline u32 perf_pmasys_mem_block_target_v(u32 r)
104{
105 return (r >> 28U) & 0x3U;
106}
107static inline u32 perf_pmasys_mem_block_target_lfb_v(void)
108{
109 return 0x00000000U;
110}
111static inline u32 perf_pmasys_mem_block_target_lfb_f(void)
112{
113 return 0x0U;
114}
115static inline u32 perf_pmasys_mem_block_target_sys_coh_v(void)
116{
117 return 0x00000002U;
118}
119static inline u32 perf_pmasys_mem_block_target_sys_coh_f(void)
120{
121 return 0x20000000U;
122}
123static inline u32 perf_pmasys_mem_block_target_sys_ncoh_v(void)
124{
125 return 0x00000003U;
126}
127static inline u32 perf_pmasys_mem_block_target_sys_ncoh_f(void)
128{
129 return 0x30000000U;
130}
131static inline u32 perf_pmasys_mem_block_valid_f(u32 v)
132{
133 return (v & 0x1U) << 31U;
134}
135static inline u32 perf_pmasys_mem_block_valid_v(u32 r)
136{
137 return (r >> 31U) & 0x1U;
138}
139static inline u32 perf_pmasys_mem_block_valid_true_v(void)
140{
141 return 0x00000001U;
142}
143static inline u32 perf_pmasys_mem_block_valid_true_f(void)
144{
145 return 0x80000000U;
146}
147static inline u32 perf_pmasys_mem_block_valid_false_v(void)
148{
149 return 0x00000000U;
150}
151static inline u32 perf_pmasys_mem_block_valid_false_f(void)
152{
153 return 0x0U;
154}
155static inline u32 perf_pmasys_outbase_r(void)
156{
157 return 0x001b4074U;
158}
159static inline u32 perf_pmasys_outbase_ptr_f(u32 v)
160{
161 return (v & 0x7ffffffU) << 5U;
162}
163static inline u32 perf_pmasys_outbaseupper_r(void)
164{
165 return 0x001b4078U;
166}
167static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v)
168{
169 return (v & 0xffU) << 0U;
170}
171static inline u32 perf_pmasys_outsize_r(void)
172{
173 return 0x001b407cU;
174}
175static inline u32 perf_pmasys_outsize_numbytes_f(u32 v)
176{
177 return (v & 0x7ffffffU) << 5U;
178}
179static inline u32 perf_pmasys_mem_bytes_r(void)
180{
181 return 0x001b4084U;
182}
183static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v)
184{
185 return (v & 0xfffffffU) << 4U;
186}
187static inline u32 perf_pmasys_mem_bump_r(void)
188{
189 return 0x001b4088U;
190}
191static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v)
192{
193 return (v & 0xfffffffU) << 4U;
194}
195static inline u32 perf_pmasys_enginestatus_r(void)
196{
197 return 0x001b40a4U;
198}
199static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v)
200{
201 return (v & 0x1U) << 4U;
202}
203static inline u32 perf_pmasys_enginestatus_rbufempty_empty_v(void)
204{
205 return 0x00000001U;
206}
207static inline u32 perf_pmasys_enginestatus_rbufempty_empty_f(void)
208{
209 return 0x10U;
210}
211#endif
diff --git a/include/gk20a/hw_pram_gk20a.h b/include/gk20a/hw_pram_gk20a.h
deleted file mode 100644
index 10923e2..0000000
--- a/include/gk20a/hw_pram_gk20a.h
+++ /dev/null
@@ -1,63 +0,0 @@
1/*
2 * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22/*
23 * Function naming determines intended use:
24 *
25 * <x>_r(void) : Returns the offset for register <x>.
26 *
27 * <x>_o(void) : Returns the offset for element <x>.
28 *
29 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
30 *
31 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
32 *
33 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
34 * and masked to place it at field <y> of register <x>. This value
35 * can be |'d with others to produce a full register value for
36 * register <x>.
37 *
38 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
39 * value can be ~'d and then &'d to clear the value of field <y> for
40 * register <x>.
41 *
42 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
43 * to place it at field <y> of register <x>. This value can be |'d
44 * with others to produce a full register value for <x>.
45 *
46 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
47 * <x> value 'r' after being shifted to place its LSB at bit 0.
48 * This value is suitable for direct comparison with other unshifted
49 * values appropriate for use in field <y> of register <x>.
50 *
51 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
52 * field <y> of register <x>. This value is suitable for direct
53 * comparison with unshifted values appropriate for use in field <y>
54 * of register <x>.
55 */
56#ifndef _hw_pram_gk20a_h_
57#define _hw_pram_gk20a_h_
58
59static inline u32 pram_data032_r(u32 i)
60{
61 return 0x00700000U + i*4U;
62}
63#endif
diff --git a/include/gk20a/hw_pri_ringmaster_gk20a.h b/include/gk20a/hw_pri_ringmaster_gk20a.h
deleted file mode 100644
index ca2775e..0000000
--- a/include/gk20a/hw_pri_ringmaster_gk20a.h
+++ /dev/null
@@ -1,159 +0,0 @@
1/*
2 * Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22/*
23 * Function naming determines intended use:
24 *
25 * <x>_r(void) : Returns the offset for register <x>.
26 *
27 * <x>_o(void) : Returns the offset for element <x>.
28 *
29 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
30 *
31 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
32 *
33 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
34 * and masked to place it at field <y> of register <x>. This value
35 * can be |'d with others to produce a full register value for
36 * register <x>.
37 *
38 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
39 * value can be ~'d and then &'d to clear the value of field <y> for
40 * register <x>.
41 *
42 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
43 * to place it at field <y> of register <x>. This value can be |'d
44 * with others to produce a full register value for <x>.
45 *
46 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
47 * <x> value 'r' after being shifted to place its LSB at bit 0.
48 * This value is suitable for direct comparison with other unshifted
49 * values appropriate for use in field <y> of register <x>.
50 *
51 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
52 * field <y> of register <x>. This value is suitable for direct
53 * comparison with unshifted values appropriate for use in field <y>
54 * of register <x>.
55 */
56#ifndef _hw_pri_ringmaster_gk20a_h_
57#define _hw_pri_ringmaster_gk20a_h_
58
59static inline u32 pri_ringmaster_command_r(void)
60{
61 return 0x0012004cU;
62}
63static inline u32 pri_ringmaster_command_cmd_m(void)
64{
65 return 0x3fU << 0U;
66}
67static inline u32 pri_ringmaster_command_cmd_v(u32 r)
68{
69 return (r >> 0U) & 0x3fU;
70}
71static inline u32 pri_ringmaster_command_cmd_no_cmd_v(void)
72{
73 return 0x00000000U;
74}
75static inline u32 pri_ringmaster_command_cmd_start_ring_f(void)
76{
77 return 0x1U;
78}
79static inline u32 pri_ringmaster_command_cmd_ack_interrupt_f(void)
80{
81 return 0x2U;
82}
83static inline u32 pri_ringmaster_command_cmd_enumerate_stations_f(void)
84{
85 return 0x3U;
86}
87static inline u32 pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f(void)
88{
89 return 0x0U;
90}
91static inline u32 pri_ringmaster_command_data_r(void)
92{
93 return 0x00120048U;
94}
95static inline u32 pri_ringmaster_start_results_r(void)
96{
97 return 0x00120050U;
98}
99static inline u32 pri_ringmaster_start_results_connectivity_v(u32 r)
100{
101 return (r >> 0U) & 0x1U;
102}
103static inline u32 pri_ringmaster_start_results_connectivity_pass_v(void)
104{
105 return 0x00000001U;
106}
107static inline u32 pri_ringmaster_intr_status0_r(void)
108{
109 return 0x00120058U;
110}
111static inline u32 pri_ringmaster_intr_status0_ring_start_conn_fault_v(u32 r)
112{
113 return (r >> 0U) & 0x1U;
114}
115static inline u32 pri_ringmaster_intr_status0_disconnect_fault_v(u32 r)
116{
117 return (r >> 1U) & 0x1U;
118}
119static inline u32 pri_ringmaster_intr_status0_overflow_fault_v(u32 r)
120{
121 return (r >> 2U) & 0x1U;
122}
123static inline u32 pri_ringmaster_intr_status0_gbl_write_error_sys_v(u32 r)
124{
125 return (r >> 8U) & 0x1U;
126}
127static inline u32 pri_ringmaster_intr_status1_r(void)
128{
129 return 0x0012005cU;
130}
131static inline u32 pri_ringmaster_global_ctl_r(void)
132{
133 return 0x00120060U;
134}
135static inline u32 pri_ringmaster_global_ctl_ring_reset_asserted_f(void)
136{
137 return 0x1U;
138}
139static inline u32 pri_ringmaster_global_ctl_ring_reset_deasserted_f(void)
140{
141 return 0x0U;
142}
143static inline u32 pri_ringmaster_enum_fbp_r(void)
144{
145 return 0x00120074U;
146}
147static inline u32 pri_ringmaster_enum_fbp_count_v(u32 r)
148{
149 return (r >> 0U) & 0x1fU;
150}
151static inline u32 pri_ringmaster_enum_gpc_r(void)
152{
153 return 0x00120078U;
154}
155static inline u32 pri_ringmaster_enum_gpc_count_v(u32 r)
156{
157 return (r >> 0U) & 0x1fU;
158}
159#endif
diff --git a/include/gk20a/hw_pri_ringstation_fbp_gk20a.h b/include/gk20a/hw_pri_ringstation_fbp_gk20a.h
deleted file mode 100644
index 06e08bd..0000000
--- a/include/gk20a/hw_pri_ringstation_fbp_gk20a.h
+++ /dev/null
@@ -1,231 +0,0 @@
1/*
2 * drivers/video/tegra/host/gk20a/hw_pri_ringstation_fbp_gk20a.h
3 *
4 * Copyright (c) 2012-2013, NVIDIA Corporation. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25 /*
26 * Function naming determines intended use:
27 *
28 * <x>_r(void) : Returns the offset for register <x>.
29 *
30 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
31 *
32 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
33 *
34 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
35 * and masked to place it at field <y> of register <x>. This value
36 * can be |'d with others to produce a full register value for
37 * register <x>.
38 *
39 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
40 * value can be ~'d and then &'d to clear the value of field <y> for
41 * register <x>.
42 *
43 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
44 * to place it at field <y> of register <x>. This value can be |'d
45 * with others to produce a full register value for <x>.
46 *
47 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
48 * <x> value 'r' after being shifted to place its LSB at bit 0.
49 * This value is suitable for direct comparison with other unshifted
50 * values appropriate for use in field <y> of register <x>.
51 *
52 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
53 * field <y> of register <x>. This value is suitable for direct
54 * comparison with unshifted values appropriate for use in field <y>
55 * of register <x>.
56 */
57
58#ifndef __hw_pri_ringstation_fbp_gk20a_h__
59#define __hw_pri_ringstation_fbp_gk20a_h__
60/*This file is autogenerated. Do not edit. */
61
62static inline u32 pri_ringstation_fbp_master_config_r(u32 i)
63{
64 return 0x00124300+((i)*4);
65}
66static inline u32 pri_ringstation_fbp_master_config__size_1_v(void)
67{
68 return 64;
69}
70static inline u32 pri_ringstation_fbp_master_config_timeout_s(void)
71{
72 return 18;
73}
74static inline u32 pri_ringstation_fbp_master_config_timeout_f(u32 v)
75{
76 return (v & 0x3ffff) << 0;
77}
78static inline u32 pri_ringstation_fbp_master_config_timeout_m(void)
79{
80 return 0x3ffff << 0;
81}
82static inline u32 pri_ringstation_fbp_master_config_timeout_v(u32 r)
83{
84 return (r >> 0) & 0x3ffff;
85}
86static inline u32 pri_ringstation_fbp_master_config_timeout_i_v(void)
87{
88 return 0x00000064;
89}
90static inline u32 pri_ringstation_fbp_master_config_timeout_i_f(void)
91{
92 return 0x64;
93}
94static inline u32 pri_ringstation_fbp_master_config_fs_action_s(void)
95{
96 return 1;
97}
98static inline u32 pri_ringstation_fbp_master_config_fs_action_f(u32 v)
99{
100 return (v & 0x1) << 30;
101}
102static inline u32 pri_ringstation_fbp_master_config_fs_action_m(void)
103{
104 return 0x1 << 30;
105}
106static inline u32 pri_ringstation_fbp_master_config_fs_action_v(u32 r)
107{
108 return (r >> 30) & 0x1;
109}
110static inline u32 pri_ringstation_fbp_master_config_fs_action_error_v(void)
111{
112 return 0x00000000;
113}
114static inline u32 pri_ringstation_fbp_master_config_fs_action_error_f(void)
115{
116 return 0x0;
117}
118static inline u32 pri_ringstation_fbp_master_config_fs_action_soldier_on_v(void)
119{
120 return 0x00000001;
121}
122static inline u32 pri_ringstation_fbp_master_config_fs_action_soldier_on_f(void)
123{
124 return 0x40000000;
125}
126static inline u32 pri_ringstation_fbp_master_config_reset_action_s(void)
127{
128 return 1;
129}
130static inline u32 pri_ringstation_fbp_master_config_reset_action_f(u32 v)
131{
132 return (v & 0x1) << 31;
133}
134static inline u32 pri_ringstation_fbp_master_config_reset_action_m(void)
135{
136 return 0x1 << 31;
137}
138static inline u32 pri_ringstation_fbp_master_config_reset_action_v(u32 r)
139{
140 return (r >> 31) & 0x1;
141}
142static inline u32 pri_ringstation_fbp_master_config_reset_action_error_v(void)
143{
144 return 0x00000000;
145}
146static inline u32 pri_ringstation_fbp_master_config_reset_action_error_f(void)
147{
148 return 0x0;
149}
150static inline u32 pri_ringstation_fbp_master_config_reset_action_soldier_on_v(void)
151{
152 return 0x00000001;
153}
154static inline u32 pri_ringstation_fbp_master_config_reset_action_soldier_on_f(void)
155{
156 return 0x80000000;
157}
158static inline u32 pri_ringstation_fbp_master_config_setup_clocks_s(void)
159{
160 return 3;
161}
162static inline u32 pri_ringstation_fbp_master_config_setup_clocks_f(u32 v)
163{
164 return (v & 0x7) << 20;
165}
166static inline u32 pri_ringstation_fbp_master_config_setup_clocks_m(void)
167{
168 return 0x7 << 20;
169}
170static inline u32 pri_ringstation_fbp_master_config_setup_clocks_v(u32 r)
171{
172 return (r >> 20) & 0x7;
173}
174static inline u32 pri_ringstation_fbp_master_config_setup_clocks_i_v(void)
175{
176 return 0x00000000;
177}
178static inline u32 pri_ringstation_fbp_master_config_setup_clocks_i_f(void)
179{
180 return 0x0;
181}
182static inline u32 pri_ringstation_fbp_master_config_wait_clocks_s(void)
183{
184 return 3;
185}
186static inline u32 pri_ringstation_fbp_master_config_wait_clocks_f(u32 v)
187{
188 return (v & 0x7) << 24;
189}
190static inline u32 pri_ringstation_fbp_master_config_wait_clocks_m(void)
191{
192 return 0x7 << 24;
193}
194static inline u32 pri_ringstation_fbp_master_config_wait_clocks_v(u32 r)
195{
196 return (r >> 24) & 0x7;
197}
198static inline u32 pri_ringstation_fbp_master_config_wait_clocks_i_v(void)
199{
200 return 0x00000000;
201}
202static inline u32 pri_ringstation_fbp_master_config_wait_clocks_i_f(void)
203{
204 return 0x0;
205}
206static inline u32 pri_ringstation_fbp_master_config_hold_clocks_s(void)
207{
208 return 3;
209}
210static inline u32 pri_ringstation_fbp_master_config_hold_clocks_f(u32 v)
211{
212 return (v & 0x7) << 27;
213}
214static inline u32 pri_ringstation_fbp_master_config_hold_clocks_m(void)
215{
216 return 0x7 << 27;
217}
218static inline u32 pri_ringstation_fbp_master_config_hold_clocks_v(u32 r)
219{
220 return (r >> 27) & 0x7;
221}
222static inline u32 pri_ringstation_fbp_master_config_hold_clocks_i_v(void)
223{
224 return 0x00000000;
225}
226static inline u32 pri_ringstation_fbp_master_config_hold_clocks_i_f(void)
227{
228 return 0x0;
229}
230
231#endif /* __hw_pri_ringstation_fbp_gk20a_h__ */
diff --git a/include/gk20a/hw_pri_ringstation_gpc_gk20a.h b/include/gk20a/hw_pri_ringstation_gpc_gk20a.h
deleted file mode 100644
index 6b57429..0000000
--- a/include/gk20a/hw_pri_ringstation_gpc_gk20a.h
+++ /dev/null
@@ -1,79 +0,0 @@
1/*
2 * Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22/*
23 * Function naming determines intended use:
24 *
25 * <x>_r(void) : Returns the offset for register <x>.
26 *
27 * <x>_o(void) : Returns the offset for element <x>.
28 *
29 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
30 *
31 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
32 *
33 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
34 * and masked to place it at field <y> of register <x>. This value
35 * can be |'d with others to produce a full register value for
36 * register <x>.
37 *
38 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
39 * value can be ~'d and then &'d to clear the value of field <y> for
40 * register <x>.
41 *
42 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
43 * to place it at field <y> of register <x>. This value can be |'d
44 * with others to produce a full register value for <x>.
45 *
46 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
47 * <x> value 'r' after being shifted to place its LSB at bit 0.
48 * This value is suitable for direct comparison with other unshifted
49 * values appropriate for use in field <y> of register <x>.
50 *
51 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
52 * field <y> of register <x>. This value is suitable for direct
53 * comparison with unshifted values appropriate for use in field <y>
54 * of register <x>.
55 */
56#ifndef _hw_pri_ringstation_gpc_gk20a_h_
57#define _hw_pri_ringstation_gpc_gk20a_h_
58
59static inline u32 pri_ringstation_gpc_master_config_r(u32 i)
60{
61 return 0x00128300U + i*4U;
62}
63static inline u32 pri_ringstation_gpc_gpc0_priv_error_adr_r(void)
64{
65 return 0x00128120U;
66}
67static inline u32 pri_ringstation_gpc_gpc0_priv_error_wrdat_r(void)
68{
69 return 0x00128124U;
70}
71static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_r(void)
72{
73 return 0x00128128U;
74}
75static inline u32 pri_ringstation_gpc_gpc0_priv_error_code_r(void)
76{
77 return 0x0012812cU;
78}
79#endif
diff --git a/include/gk20a/hw_pri_ringstation_sys_gk20a.h b/include/gk20a/hw_pri_ringstation_sys_gk20a.h
deleted file mode 100644
index e4d5c3b..0000000
--- a/include/gk20a/hw_pri_ringstation_sys_gk20a.h
+++ /dev/null
@@ -1,91 +0,0 @@
1/*
2 * Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22/*
23 * Function naming determines intended use:
24 *
25 * <x>_r(void) : Returns the offset for register <x>.
26 *
27 * <x>_o(void) : Returns the offset for element <x>.
28 *
29 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
30 *
31 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
32 *
33 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
34 * and masked to place it at field <y> of register <x>. This value
35 * can be |'d with others to produce a full register value for
36 * register <x>.
37 *
38 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
39 * value can be ~'d and then &'d to clear the value of field <y> for
40 * register <x>.
41 *
42 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
43 * to place it at field <y> of register <x>. This value can be |'d
44 * with others to produce a full register value for <x>.
45 *
46 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
47 * <x> value 'r' after being shifted to place its LSB at bit 0.
48 * This value is suitable for direct comparison with other unshifted
49 * values appropriate for use in field <y> of register <x>.
50 *
51 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
52 * field <y> of register <x>. This value is suitable for direct
53 * comparison with unshifted values appropriate for use in field <y>
54 * of register <x>.
55 */
56#ifndef _hw_pri_ringstation_sys_gk20a_h_
57#define _hw_pri_ringstation_sys_gk20a_h_
58
59static inline u32 pri_ringstation_sys_master_config_r(u32 i)
60{
61 return 0x00122300U + i*4U;
62}
63static inline u32 pri_ringstation_sys_decode_config_r(void)
64{
65 return 0x00122204U;
66}
67static inline u32 pri_ringstation_sys_decode_config_ring_m(void)
68{
69 return 0x7U << 0U;
70}
71static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void)
72{
73 return 0x1U;
74}
75static inline u32 pri_ringstation_sys_priv_error_adr_r(void)
76{
77 return 0x00122120U;
78}
79static inline u32 pri_ringstation_sys_priv_error_wrdat_r(void)
80{
81 return 0x00122124U;
82}
83static inline u32 pri_ringstation_sys_priv_error_info_r(void)
84{
85 return 0x00122128U;
86}
87static inline u32 pri_ringstation_sys_priv_error_code_r(void)
88{
89 return 0x0012212cU;
90}
91#endif
diff --git a/include/gk20a/hw_proj_gk20a.h b/include/gk20a/hw_proj_gk20a.h
deleted file mode 100644
index 10509ca..0000000
--- a/include/gk20a/hw_proj_gk20a.h
+++ /dev/null
@@ -1,167 +0,0 @@
1/*
2 * Copyright (c) 2012-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22/*
23 * Function naming determines intended use:
24 *
25 * <x>_r(void) : Returns the offset for register <x>.
26 *
27 * <x>_o(void) : Returns the offset for element <x>.
28 *
29 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
30 *
31 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
32 *
33 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
34 * and masked to place it at field <y> of register <x>. This value
35 * can be |'d with others to produce a full register value for
36 * register <x>.
37 *
38 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
39 * value can be ~'d and then &'d to clear the value of field <y> for
40 * register <x>.
41 *
42 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
43 * to place it at field <y> of register <x>. This value can be |'d
44 * with others to produce a full register value for <x>.
45 *
46 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
47 * <x> value 'r' after being shifted to place its LSB at bit 0.
48 * This value is suitable for direct comparison with other unshifted
49 * values appropriate for use in field <y> of register <x>.
50 *
51 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
52 * field <y> of register <x>. This value is suitable for direct
53 * comparison with unshifted values appropriate for use in field <y>
54 * of register <x>.
55 */
56#ifndef _hw_proj_gk20a_h_
57#define _hw_proj_gk20a_h_
58
59static inline u32 proj_gpc_base_v(void)
60{
61 return 0x00500000U;
62}
63static inline u32 proj_gpc_shared_base_v(void)
64{
65 return 0x00418000U;
66}
67static inline u32 proj_gpc_stride_v(void)
68{
69 return 0x00008000U;
70}
71static inline u32 proj_gpc_priv_stride_v(void)
72{
73 return 0x00000800U;
74}
75static inline u32 proj_ltc_stride_v(void)
76{
77 return 0x00002000U;
78}
79static inline u32 proj_lts_stride_v(void)
80{
81 return 0x00000400U;
82}
83static inline u32 proj_fbpa_stride_v(void)
84{
85 return 0x00001000U;
86}
87static inline u32 proj_ppc_in_gpc_base_v(void)
88{
89 return 0x00003000U;
90}
91static inline u32 proj_ppc_in_gpc_shared_base_v(void)
92{
93 return 0x00003e00U;
94}
95static inline u32 proj_ppc_in_gpc_stride_v(void)
96{
97 return 0x00000200U;
98}
99static inline u32 proj_rop_base_v(void)
100{
101 return 0x00410000U;
102}
103static inline u32 proj_rop_shared_base_v(void)
104{
105 return 0x00408800U;
106}
107static inline u32 proj_rop_stride_v(void)
108{
109 return 0x00000400U;
110}
111static inline u32 proj_tpc_in_gpc_base_v(void)
112{
113 return 0x00004000U;
114}
115static inline u32 proj_tpc_in_gpc_stride_v(void)
116{
117 return 0x00000800U;
118}
119static inline u32 proj_tpc_in_gpc_shared_base_v(void)
120{
121 return 0x00001800U;
122}
123static inline u32 proj_host_num_engines_v(void)
124{
125 return 0x00000002U;
126}
127static inline u32 proj_host_num_pbdma_v(void)
128{
129 return 0x00000001U;
130}
131static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void)
132{
133 return 0x00000001U;
134}
135static inline u32 proj_scal_litter_num_fbps_v(void)
136{
137 return 0x00000001U;
138}
139static inline u32 proj_scal_litter_num_fbpas_v(void)
140{
141 return 0x00000001U;
142}
143static inline u32 proj_scal_litter_num_gpcs_v(void)
144{
145 return 0x00000001U;
146}
147static inline u32 proj_scal_litter_num_pes_per_gpc_v(void)
148{
149 return 0x00000001U;
150}
151static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void)
152{
153 return 0x00000001U;
154}
155static inline u32 proj_scal_litter_num_zcull_banks_v(void)
156{
157 return 0x00000004U;
158}
159static inline u32 proj_scal_max_gpcs_v(void)
160{
161 return 0x00000020U;
162}
163static inline u32 proj_scal_max_tpc_per_gpc_v(void)
164{
165 return 0x00000008U;
166}
167#endif
diff --git a/include/gk20a/hw_pwr_gk20a.h b/include/gk20a/hw_pwr_gk20a.h
deleted file mode 100644
index 2845763..0000000
--- a/include/gk20a/hw_pwr_gk20a.h
+++ /dev/null
@@ -1,823 +0,0 @@
1/*
2 * Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22/*
23 * Function naming determines intended use:
24 *
25 * <x>_r(void) : Returns the offset for register <x>.
26 *
27 * <x>_o(void) : Returns the offset for element <x>.
28 *
29 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
30 *
31 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
32 *
33 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
34 * and masked to place it at field <y> of register <x>. This value
35 * can be |'d with others to produce a full register value for
36 * register <x>.
37 *
38 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
39 * value can be ~'d and then &'d to clear the value of field <y> for
40 * register <x>.
41 *
42 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
43 * to place it at field <y> of register <x>. This value can be |'d
44 * with others to produce a full register value for <x>.
45 *
46 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
47 * <x> value 'r' after being shifted to place its LSB at bit 0.
48 * This value is suitable for direct comparison with other unshifted
49 * values appropriate for use in field <y> of register <x>.
50 *
51 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
52 * field <y> of register <x>. This value is suitable for direct
53 * comparison with unshifted values appropriate for use in field <y>
54 * of register <x>.
55 */
56#ifndef _hw_pwr_gk20a_h_
57#define _hw_pwr_gk20a_h_
58
59static inline u32 pwr_falcon_irqsset_r(void)
60{
61 return 0x0010a000U;
62}
63static inline u32 pwr_falcon_irqsset_swgen0_set_f(void)
64{
65 return 0x40U;
66}
67static inline u32 pwr_falcon_irqsclr_r(void)
68{
69 return 0x0010a004U;
70}
71static inline u32 pwr_falcon_irqstat_r(void)
72{
73 return 0x0010a008U;
74}
75static inline u32 pwr_falcon_irqstat_halt_true_f(void)
76{
77 return 0x10U;
78}
79static inline u32 pwr_falcon_irqstat_exterr_true_f(void)
80{
81 return 0x20U;
82}
83static inline u32 pwr_falcon_irqstat_swgen0_true_f(void)
84{
85 return 0x40U;
86}
87static inline u32 pwr_falcon_irqmode_r(void)
88{
89 return 0x0010a00cU;
90}
91static inline u32 pwr_falcon_irqmset_r(void)
92{
93 return 0x0010a010U;
94}
95static inline u32 pwr_falcon_irqmset_gptmr_f(u32 v)
96{
97 return (v & 0x1U) << 0U;
98}
99static inline u32 pwr_falcon_irqmset_wdtmr_f(u32 v)
100{
101 return (v & 0x1U) << 1U;
102}
103static inline u32 pwr_falcon_irqmset_mthd_f(u32 v)
104{
105 return (v & 0x1U) << 2U;
106}
107static inline u32 pwr_falcon_irqmset_ctxsw_f(u32 v)
108{
109 return (v & 0x1U) << 3U;
110}
111static inline u32 pwr_falcon_irqmset_halt_f(u32 v)
112{
113 return (v & 0x1U) << 4U;
114}
115static inline u32 pwr_falcon_irqmset_exterr_f(u32 v)
116{
117 return (v & 0x1U) << 5U;
118}
119static inline u32 pwr_falcon_irqmset_swgen0_f(u32 v)
120{
121 return (v & 0x1U) << 6U;
122}
123static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v)
124{
125 return (v & 0x1U) << 7U;
126}
127static inline u32 pwr_falcon_irqmclr_r(void)
128{
129 return 0x0010a014U;
130}
131static inline u32 pwr_falcon_irqmclr_gptmr_f(u32 v)
132{
133 return (v & 0x1U) << 0U;
134}
135static inline u32 pwr_falcon_irqmclr_wdtmr_f(u32 v)
136{
137 return (v & 0x1U) << 1U;
138}
139static inline u32 pwr_falcon_irqmclr_mthd_f(u32 v)
140{
141 return (v & 0x1U) << 2U;
142}
143static inline u32 pwr_falcon_irqmclr_ctxsw_f(u32 v)
144{
145 return (v & 0x1U) << 3U;
146}
147static inline u32 pwr_falcon_irqmclr_halt_f(u32 v)
148{
149 return (v & 0x1U) << 4U;
150}
151static inline u32 pwr_falcon_irqmclr_exterr_f(u32 v)
152{
153 return (v & 0x1U) << 5U;
154}
155static inline u32 pwr_falcon_irqmclr_swgen0_f(u32 v)
156{
157 return (v & 0x1U) << 6U;
158}
159static inline u32 pwr_falcon_irqmclr_swgen1_f(u32 v)
160{
161 return (v & 0x1U) << 7U;
162}
163static inline u32 pwr_falcon_irqmclr_ext_f(u32 v)
164{
165 return (v & 0xffU) << 8U;
166}
167static inline u32 pwr_falcon_irqmask_r(void)
168{
169 return 0x0010a018U;
170}
171static inline u32 pwr_falcon_irqdest_r(void)
172{
173 return 0x0010a01cU;
174}
175static inline u32 pwr_falcon_irqdest_host_gptmr_f(u32 v)
176{
177 return (v & 0x1U) << 0U;
178}
179static inline u32 pwr_falcon_irqdest_host_wdtmr_f(u32 v)
180{
181 return (v & 0x1U) << 1U;
182}
183static inline u32 pwr_falcon_irqdest_host_mthd_f(u32 v)
184{
185 return (v & 0x1U) << 2U;
186}
187static inline u32 pwr_falcon_irqdest_host_ctxsw_f(u32 v)
188{
189 return (v & 0x1U) << 3U;
190}
191static inline u32 pwr_falcon_irqdest_host_halt_f(u32 v)
192{
193 return (v & 0x1U) << 4U;
194}
195static inline u32 pwr_falcon_irqdest_host_exterr_f(u32 v)
196{
197 return (v & 0x1U) << 5U;
198}
199static inline u32 pwr_falcon_irqdest_host_swgen0_f(u32 v)
200{
201 return (v & 0x1U) << 6U;
202}
203static inline u32 pwr_falcon_irqdest_host_swgen1_f(u32 v)
204{
205 return (v & 0x1U) << 7U;
206}
207static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v)
208{
209 return (v & 0xffU) << 8U;
210}
211static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v)
212{
213 return (v & 0x1U) << 16U;
214}
215static inline u32 pwr_falcon_irqdest_target_wdtmr_f(u32 v)
216{
217 return (v & 0x1U) << 17U;
218}
219static inline u32 pwr_falcon_irqdest_target_mthd_f(u32 v)
220{
221 return (v & 0x1U) << 18U;
222}
223static inline u32 pwr_falcon_irqdest_target_ctxsw_f(u32 v)
224{
225 return (v & 0x1U) << 19U;
226}
227static inline u32 pwr_falcon_irqdest_target_halt_f(u32 v)
228{
229 return (v & 0x1U) << 20U;
230}
231static inline u32 pwr_falcon_irqdest_target_exterr_f(u32 v)
232{
233 return (v & 0x1U) << 21U;
234}
235static inline u32 pwr_falcon_irqdest_target_swgen0_f(u32 v)
236{
237 return (v & 0x1U) << 22U;
238}
239static inline u32 pwr_falcon_irqdest_target_swgen1_f(u32 v)
240{
241 return (v & 0x1U) << 23U;
242}
243static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v)
244{
245 return (v & 0xffU) << 24U;
246}
247static inline u32 pwr_falcon_curctx_r(void)
248{
249 return 0x0010a050U;
250}
251static inline u32 pwr_falcon_nxtctx_r(void)
252{
253 return 0x0010a054U;
254}
255static inline u32 pwr_falcon_mailbox0_r(void)
256{
257 return 0x0010a040U;
258}
259static inline u32 pwr_falcon_mailbox1_r(void)
260{
261 return 0x0010a044U;
262}
263static inline u32 pwr_falcon_itfen_r(void)
264{
265 return 0x0010a048U;
266}
267static inline u32 pwr_falcon_itfen_ctxen_enable_f(void)
268{
269 return 0x1U;
270}
271static inline u32 pwr_falcon_idlestate_r(void)
272{
273 return 0x0010a04cU;
274}
275static inline u32 pwr_falcon_idlestate_falcon_busy_v(u32 r)
276{
277 return (r >> 0U) & 0x1U;
278}
279static inline u32 pwr_falcon_idlestate_ext_busy_v(u32 r)
280{
281 return (r >> 1U) & 0x7fffU;
282}
283static inline u32 pwr_falcon_os_r(void)
284{
285 return 0x0010a080U;
286}
287static inline u32 pwr_falcon_engctl_r(void)
288{
289 return 0x0010a0a4U;
290}
291static inline u32 pwr_falcon_cpuctl_r(void)
292{
293 return 0x0010a100U;
294}
295static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v)
296{
297 return (v & 0x1U) << 1U;
298}
299static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v)
300{
301 return (v & 0x1U) << 4U;
302}
303static inline u32 pwr_falcon_cpuctl_halt_intr_m(void)
304{
305 return 0x1U << 4U;
306}
307static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r)
308{
309 return (r >> 4U) & 0x1U;
310}
311static inline u32 pwr_falcon_imemc_r(u32 i)
312{
313 return 0x0010a180U + i*16U;
314}
315static inline u32 pwr_falcon_imemc_offs_f(u32 v)
316{
317 return (v & 0x3fU) << 2U;
318}
319static inline u32 pwr_falcon_imemc_blk_f(u32 v)
320{
321 return (v & 0xffU) << 8U;
322}
323static inline u32 pwr_falcon_imemc_aincw_f(u32 v)
324{
325 return (v & 0x1U) << 24U;
326}
327static inline u32 pwr_falcon_imemd_r(u32 i)
328{
329 return 0x0010a184U + i*16U;
330}
331static inline u32 pwr_falcon_imemt_r(u32 i)
332{
333 return 0x0010a188U + i*16U;
334}
335static inline u32 pwr_falcon_bootvec_r(void)
336{
337 return 0x0010a104U;
338}
339static inline u32 pwr_falcon_bootvec_vec_f(u32 v)
340{
341 return (v & 0xffffffffU) << 0U;
342}
343static inline u32 pwr_falcon_dmactl_r(void)
344{
345 return 0x0010a10cU;
346}
347static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void)
348{
349 return 0x1U << 1U;
350}
351static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void)
352{
353 return 0x1U << 2U;
354}
355static inline u32 pwr_falcon_hwcfg_r(void)
356{
357 return 0x0010a108U;
358}
359static inline u32 pwr_falcon_hwcfg_imem_size_v(u32 r)
360{
361 return (r >> 0U) & 0x1ffU;
362}
363static inline u32 pwr_falcon_hwcfg_dmem_size_v(u32 r)
364{
365 return (r >> 9U) & 0x1ffU;
366}
367static inline u32 pwr_falcon_dmatrfbase_r(void)
368{
369 return 0x0010a110U;
370}
371static inline u32 pwr_falcon_dmatrfmoffs_r(void)
372{
373 return 0x0010a114U;
374}
375static inline u32 pwr_falcon_dmatrfcmd_r(void)
376{
377 return 0x0010a118U;
378}
379static inline u32 pwr_falcon_dmatrfcmd_imem_f(u32 v)
380{
381 return (v & 0x1U) << 4U;
382}
383static inline u32 pwr_falcon_dmatrfcmd_write_f(u32 v)
384{
385 return (v & 0x1U) << 5U;
386}
387static inline u32 pwr_falcon_dmatrfcmd_size_f(u32 v)
388{
389 return (v & 0x7U) << 8U;
390}
391static inline u32 pwr_falcon_dmatrfcmd_ctxdma_f(u32 v)
392{
393 return (v & 0x7U) << 12U;
394}
395static inline u32 pwr_falcon_dmatrffboffs_r(void)
396{
397 return 0x0010a11cU;
398}
399static inline u32 pwr_falcon_exterraddr_r(void)
400{
401 return 0x0010a168U;
402}
403static inline u32 pwr_falcon_exterrstat_r(void)
404{
405 return 0x0010a16cU;
406}
407static inline u32 pwr_falcon_exterrstat_valid_m(void)
408{
409 return 0x1U << 31U;
410}
411static inline u32 pwr_falcon_exterrstat_valid_v(u32 r)
412{
413 return (r >> 31U) & 0x1U;
414}
415static inline u32 pwr_falcon_exterrstat_valid_true_v(void)
416{
417 return 0x00000001U;
418}
419static inline u32 pwr_pmu_falcon_icd_cmd_r(void)
420{
421 return 0x0010a200U;
422}
423static inline u32 pwr_pmu_falcon_icd_cmd_opc_s(void)
424{
425 return 4U;
426}
427static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v)
428{
429 return (v & 0xfU) << 0U;
430}
431static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void)
432{
433 return 0xfU << 0U;
434}
435static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r)
436{
437 return (r >> 0U) & 0xfU;
438}
439static inline u32 pwr_pmu_falcon_icd_cmd_opc_rreg_f(void)
440{
441 return 0x8U;
442}
443static inline u32 pwr_pmu_falcon_icd_cmd_opc_rstat_f(void)
444{
445 return 0xeU;
446}
447static inline u32 pwr_pmu_falcon_icd_cmd_idx_f(u32 v)
448{
449 return (v & 0x1fU) << 8U;
450}
451static inline u32 pwr_pmu_falcon_icd_rdata_r(void)
452{
453 return 0x0010a20cU;
454}
455static inline u32 pwr_falcon_dmemc_r(u32 i)
456{
457 return 0x0010a1c0U + i*8U;
458}
459static inline u32 pwr_falcon_dmemc_offs_f(u32 v)
460{
461 return (v & 0x3fU) << 2U;
462}
463static inline u32 pwr_falcon_dmemc_offs_m(void)
464{
465 return 0x3fU << 2U;
466}
467static inline u32 pwr_falcon_dmemc_blk_f(u32 v)
468{
469 return (v & 0xffU) << 8U;
470}
471static inline u32 pwr_falcon_dmemc_blk_m(void)
472{
473 return 0xffU << 8U;
474}
475static inline u32 pwr_falcon_dmemc_aincw_f(u32 v)
476{
477 return (v & 0x1U) << 24U;
478}
479static inline u32 pwr_falcon_dmemc_aincr_f(u32 v)
480{
481 return (v & 0x1U) << 25U;
482}
483static inline u32 pwr_falcon_dmemd_r(u32 i)
484{
485 return 0x0010a1c4U + i*8U;
486}
487static inline u32 pwr_pmu_new_instblk_r(void)
488{
489 return 0x0010a480U;
490}
491static inline u32 pwr_pmu_new_instblk_ptr_f(u32 v)
492{
493 return (v & 0xfffffffU) << 0U;
494}
495static inline u32 pwr_pmu_new_instblk_target_fb_f(void)
496{
497 return 0x0U;
498}
499static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void)
500{
501 return 0x20000000U;
502}
503static inline u32 pwr_pmu_new_instblk_target_sys_ncoh_f(void)
504{
505 return 0x30000000U;
506}
507static inline u32 pwr_pmu_new_instblk_valid_f(u32 v)
508{
509 return (v & 0x1U) << 30U;
510}
511static inline u32 pwr_pmu_mutex_id_r(void)
512{
513 return 0x0010a488U;
514}
515static inline u32 pwr_pmu_mutex_id_value_v(u32 r)
516{
517 return (r >> 0U) & 0xffU;
518}
519static inline u32 pwr_pmu_mutex_id_value_init_v(void)
520{
521 return 0x00000000U;
522}
523static inline u32 pwr_pmu_mutex_id_value_not_avail_v(void)
524{
525 return 0x000000ffU;
526}
527static inline u32 pwr_pmu_mutex_id_release_r(void)
528{
529 return 0x0010a48cU;
530}
531static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v)
532{
533 return (v & 0xffU) << 0U;
534}
535static inline u32 pwr_pmu_mutex_id_release_value_m(void)
536{
537 return 0xffU << 0U;
538}
539static inline u32 pwr_pmu_mutex_id_release_value_init_v(void)
540{
541 return 0x00000000U;
542}
543static inline u32 pwr_pmu_mutex_id_release_value_init_f(void)
544{
545 return 0x0U;
546}
547static inline u32 pwr_pmu_mutex_r(u32 i)
548{
549 return 0x0010a580U + i*4U;
550}
551static inline u32 pwr_pmu_mutex__size_1_v(void)
552{
553 return 0x00000010U;
554}
555static inline u32 pwr_pmu_mutex_value_f(u32 v)
556{
557 return (v & 0xffU) << 0U;
558}
559static inline u32 pwr_pmu_mutex_value_v(u32 r)
560{
561 return (r >> 0U) & 0xffU;
562}
563static inline u32 pwr_pmu_mutex_value_initial_lock_f(void)
564{
565 return 0x0U;
566}
567static inline u32 pwr_pmu_queue_head_r(u32 i)
568{
569 return 0x0010a4a0U + i*4U;
570}
571static inline u32 pwr_pmu_queue_head__size_1_v(void)
572{
573 return 0x00000004U;
574}
575static inline u32 pwr_pmu_queue_head_address_f(u32 v)
576{
577 return (v & 0xffffffffU) << 0U;
578}
579static inline u32 pwr_pmu_queue_head_address_v(u32 r)
580{
581 return (r >> 0U) & 0xffffffffU;
582}
583static inline u32 pwr_pmu_queue_tail_r(u32 i)
584{
585 return 0x0010a4b0U + i*4U;
586}
587static inline u32 pwr_pmu_queue_tail__size_1_v(void)
588{
589 return 0x00000004U;
590}
591static inline u32 pwr_pmu_queue_tail_address_f(u32 v)
592{
593 return (v & 0xffffffffU) << 0U;
594}
595static inline u32 pwr_pmu_queue_tail_address_v(u32 r)
596{
597 return (r >> 0U) & 0xffffffffU;
598}
599static inline u32 pwr_pmu_msgq_head_r(void)
600{
601 return 0x0010a4c8U;
602}
603static inline u32 pwr_pmu_msgq_head_val_f(u32 v)
604{
605 return (v & 0xffffffffU) << 0U;
606}
607static inline u32 pwr_pmu_msgq_head_val_v(u32 r)
608{
609 return (r >> 0U) & 0xffffffffU;
610}
611static inline u32 pwr_pmu_msgq_tail_r(void)
612{
613 return 0x0010a4ccU;
614}
615static inline u32 pwr_pmu_msgq_tail_val_f(u32 v)
616{
617 return (v & 0xffffffffU) << 0U;
618}
619static inline u32 pwr_pmu_msgq_tail_val_v(u32 r)
620{
621 return (r >> 0U) & 0xffffffffU;
622}
623static inline u32 pwr_pmu_idle_mask_r(u32 i)
624{
625 return 0x0010a504U + i*16U;
626}
627static inline u32 pwr_pmu_idle_mask_gr_enabled_f(void)
628{
629 return 0x1U;
630}
631static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void)
632{
633 return 0x200000U;
634}
635static inline u32 pwr_pmu_idle_count_r(u32 i)
636{
637 return 0x0010a508U + i*16U;
638}
639static inline u32 pwr_pmu_idle_count_value_f(u32 v)
640{
641 return (v & 0x7fffffffU) << 0U;
642}
643static inline u32 pwr_pmu_idle_count_value_v(u32 r)
644{
645 return (r >> 0U) & 0x7fffffffU;
646}
647static inline u32 pwr_pmu_idle_count_reset_f(u32 v)
648{
649 return (v & 0x1U) << 31U;
650}
651static inline u32 pwr_pmu_idle_ctrl_r(u32 i)
652{
653 return 0x0010a50cU + i*16U;
654}
655static inline u32 pwr_pmu_idle_ctrl_value_m(void)
656{
657 return 0x3U << 0U;
658}
659static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void)
660{
661 return 0x2U;
662}
663static inline u32 pwr_pmu_idle_ctrl_value_always_f(void)
664{
665 return 0x3U;
666}
667static inline u32 pwr_pmu_idle_ctrl_filter_m(void)
668{
669 return 0x1U << 2U;
670}
671static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void)
672{
673 return 0x0U;
674}
675static inline u32 pwr_pmu_idle_threshold_r(u32 i)
676{
677 return 0x0010a8a0U + i*4U;
678}
679static inline u32 pwr_pmu_idle_threshold_value_f(u32 v)
680{
681 return (v & 0x7fffffffU) << 0U;
682}
683static inline u32 pwr_pmu_idle_intr_r(void)
684{
685 return 0x0010a9e8U;
686}
687static inline u32 pwr_pmu_idle_intr_en_f(u32 v)
688{
689 return (v & 0x1U) << 0U;
690}
691static inline u32 pwr_pmu_idle_intr_en_disabled_v(void)
692{
693 return 0x00000000U;
694}
695static inline u32 pwr_pmu_idle_intr_en_enabled_v(void)
696{
697 return 0x00000001U;
698}
699static inline u32 pwr_pmu_idle_intr_status_r(void)
700{
701 return 0x0010a9ecU;
702}
703static inline u32 pwr_pmu_idle_intr_status_intr_f(u32 v)
704{
705 return (v & 0x1U) << 0U;
706}
707static inline u32 pwr_pmu_idle_intr_status_intr_m(void)
708{
709 return U32(0x1U) << 0U;
710}
711static inline u32 pwr_pmu_idle_intr_status_intr_v(u32 r)
712{
713 return (r >> 0U) & 0x1U;
714}
715static inline u32 pwr_pmu_idle_mask_supp_r(u32 i)
716{
717 return 0x0010a9f0U + i*8U;
718}
719static inline u32 pwr_pmu_idle_mask_1_supp_r(u32 i)
720{
721 return 0x0010a9f4U + i*8U;
722}
723static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i)
724{
725 return 0x0010aa30U + i*8U;
726}
727static inline u32 pwr_pmu_debug_r(u32 i)
728{
729 return 0x0010a5c0U + i*4U;
730}
731static inline u32 pwr_pmu_debug__size_1_v(void)
732{
733 return 0x00000004U;
734}
735static inline u32 pwr_pmu_mailbox_r(u32 i)
736{
737 return 0x0010a450U + i*4U;
738}
739static inline u32 pwr_pmu_mailbox__size_1_v(void)
740{
741 return 0x0000000cU;
742}
743static inline u32 pwr_pmu_bar0_addr_r(void)
744{
745 return 0x0010a7a0U;
746}
747static inline u32 pwr_pmu_bar0_data_r(void)
748{
749 return 0x0010a7a4U;
750}
751static inline u32 pwr_pmu_bar0_ctl_r(void)
752{
753 return 0x0010a7acU;
754}
755static inline u32 pwr_pmu_bar0_timeout_r(void)
756{
757 return 0x0010a7a8U;
758}
759static inline u32 pwr_pmu_bar0_fecs_error_r(void)
760{
761 return 0x0010a988U;
762}
763static inline u32 pwr_pmu_bar0_error_status_r(void)
764{
765 return 0x0010a7b0U;
766}
767static inline u32 pwr_pmu_pg_idlefilth_r(u32 i)
768{
769 return 0x0010a6c0U + i*4U;
770}
771static inline u32 pwr_pmu_pg_ppuidlefilth_r(u32 i)
772{
773 return 0x0010a6e8U + i*4U;
774}
775static inline u32 pwr_pmu_pg_idle_cnt_r(u32 i)
776{
777 return 0x0010a710U + i*4U;
778}
779static inline u32 pwr_pmu_pg_intren_r(u32 i)
780{
781 return 0x0010a760U + i*4U;
782}
783static inline u32 pwr_fbif_transcfg_r(u32 i)
784{
785 return 0x0010a600U + i*4U;
786}
787static inline u32 pwr_fbif_transcfg_target_local_fb_f(void)
788{
789 return 0x0U;
790}
791static inline u32 pwr_fbif_transcfg_target_coherent_sysmem_f(void)
792{
793 return 0x1U;
794}
795static inline u32 pwr_fbif_transcfg_target_noncoherent_sysmem_f(void)
796{
797 return 0x2U;
798}
799static inline u32 pwr_fbif_transcfg_mem_type_s(void)
800{
801 return 1U;
802}
803static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v)
804{
805 return (v & 0x1U) << 2U;
806}
807static inline u32 pwr_fbif_transcfg_mem_type_m(void)
808{
809 return 0x1U << 2U;
810}
811static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r)
812{
813 return (r >> 2U) & 0x1U;
814}
815static inline u32 pwr_fbif_transcfg_mem_type_virtual_f(void)
816{
817 return 0x0U;
818}
819static inline u32 pwr_fbif_transcfg_mem_type_physical_f(void)
820{
821 return 0x4U;
822}
823#endif
diff --git a/include/gk20a/hw_ram_gk20a.h b/include/gk20a/hw_ram_gk20a.h
deleted file mode 100644
index ed385d9..0000000
--- a/include/gk20a/hw_ram_gk20a.h
+++ /dev/null
@@ -1,443 +0,0 @@
1/*
2 * Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22/*
23 * Function naming determines intended use:
24 *
25 * <x>_r(void) : Returns the offset for register <x>.
26 *
27 * <x>_o(void) : Returns the offset for element <x>.
28 *
29 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
30 *
31 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
32 *
33 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
34 * and masked to place it at field <y> of register <x>. This value
35 * can be |'d with others to produce a full register value for
36 * register <x>.
37 *
38 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
39 * value can be ~'d and then &'d to clear the value of field <y> for
40 * register <x>.
41 *
42 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
43 * to place it at field <y> of register <x>. This value can be |'d
44 * with others to produce a full register value for <x>.
45 *
46 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
47 * <x> value 'r' after being shifted to place its LSB at bit 0.
48 * This value is suitable for direct comparison with other unshifted
49 * values appropriate for use in field <y> of register <x>.
50 *
51 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
52 * field <y> of register <x>. This value is suitable for direct
53 * comparison with unshifted values appropriate for use in field <y>
54 * of register <x>.
55 */
56#ifndef _hw_ram_gk20a_h_
57#define _hw_ram_gk20a_h_
58
59static inline u32 ram_in_ramfc_s(void)
60{
61 return 4096U;
62}
63static inline u32 ram_in_ramfc_w(void)
64{
65 return 0U;
66}
67static inline u32 ram_in_page_dir_base_target_f(u32 v)
68{
69 return (v & 0x3U) << 0U;
70}
71static inline u32 ram_in_page_dir_base_target_w(void)
72{
73 return 128U;
74}
75static inline u32 ram_in_page_dir_base_target_vid_mem_f(void)
76{
77 return 0x0U;
78}
79static inline u32 ram_in_page_dir_base_target_sys_mem_coh_f(void)
80{
81 return 0x2U;
82}
83static inline u32 ram_in_page_dir_base_target_sys_mem_ncoh_f(void)
84{
85 return 0x3U;
86}
87static inline u32 ram_in_page_dir_base_vol_w(void)
88{
89 return 128U;
90}
91static inline u32 ram_in_page_dir_base_vol_true_f(void)
92{
93 return 0x4U;
94}
95static inline u32 ram_in_page_dir_base_lo_f(u32 v)
96{
97 return (v & 0xfffffU) << 12U;
98}
99static inline u32 ram_in_page_dir_base_lo_w(void)
100{
101 return 128U;
102}
103static inline u32 ram_in_page_dir_base_hi_f(u32 v)
104{
105 return (v & 0xffU) << 0U;
106}
107static inline u32 ram_in_page_dir_base_hi_w(void)
108{
109 return 129U;
110}
111static inline u32 ram_in_adr_limit_lo_f(u32 v)
112{
113 return (v & 0xfffffU) << 12U;
114}
115static inline u32 ram_in_adr_limit_lo_w(void)
116{
117 return 130U;
118}
119static inline u32 ram_in_adr_limit_hi_f(u32 v)
120{
121 return (v & 0xffU) << 0U;
122}
123static inline u32 ram_in_adr_limit_hi_w(void)
124{
125 return 131U;
126}
127static inline u32 ram_in_engine_cs_w(void)
128{
129 return 132U;
130}
131static inline u32 ram_in_engine_cs_wfi_v(void)
132{
133 return 0x00000000U;
134}
135static inline u32 ram_in_engine_cs_wfi_f(void)
136{
137 return 0x0U;
138}
139static inline u32 ram_in_engine_cs_fg_v(void)
140{
141 return 0x00000001U;
142}
143static inline u32 ram_in_engine_cs_fg_f(void)
144{
145 return 0x8U;
146}
147static inline u32 ram_in_gr_cs_w(void)
148{
149 return 132U;
150}
151static inline u32 ram_in_gr_cs_wfi_f(void)
152{
153 return 0x0U;
154}
155static inline u32 ram_in_gr_wfi_target_w(void)
156{
157 return 132U;
158}
159static inline u32 ram_in_gr_wfi_mode_w(void)
160{
161 return 132U;
162}
163static inline u32 ram_in_gr_wfi_mode_physical_v(void)
164{
165 return 0x00000000U;
166}
167static inline u32 ram_in_gr_wfi_mode_physical_f(void)
168{
169 return 0x0U;
170}
171static inline u32 ram_in_gr_wfi_mode_virtual_v(void)
172{
173 return 0x00000001U;
174}
175static inline u32 ram_in_gr_wfi_mode_virtual_f(void)
176{
177 return 0x4U;
178}
179static inline u32 ram_in_gr_wfi_ptr_lo_f(u32 v)
180{
181 return (v & 0xfffffU) << 12U;
182}
183static inline u32 ram_in_gr_wfi_ptr_lo_w(void)
184{
185 return 132U;
186}
187static inline u32 ram_in_gr_wfi_ptr_hi_f(u32 v)
188{
189 return (v & 0xffU) << 0U;
190}
191static inline u32 ram_in_gr_wfi_ptr_hi_w(void)
192{
193 return 133U;
194}
195static inline u32 ram_in_base_shift_v(void)
196{
197 return 0x0000000cU;
198}
199static inline u32 ram_in_alloc_size_v(void)
200{
201 return 0x00001000U;
202}
203static inline u32 ram_fc_size_val_v(void)
204{
205 return 0x00000200U;
206}
207static inline u32 ram_fc_gp_put_w(void)
208{
209 return 0U;
210}
211static inline u32 ram_fc_userd_w(void)
212{
213 return 2U;
214}
215static inline u32 ram_fc_userd_hi_w(void)
216{
217 return 3U;
218}
219static inline u32 ram_fc_signature_w(void)
220{
221 return 4U;
222}
223static inline u32 ram_fc_gp_get_w(void)
224{
225 return 5U;
226}
227static inline u32 ram_fc_pb_get_w(void)
228{
229 return 6U;
230}
231static inline u32 ram_fc_pb_get_hi_w(void)
232{
233 return 7U;
234}
235static inline u32 ram_fc_pb_top_level_get_w(void)
236{
237 return 8U;
238}
239static inline u32 ram_fc_pb_top_level_get_hi_w(void)
240{
241 return 9U;
242}
243static inline u32 ram_fc_acquire_w(void)
244{
245 return 12U;
246}
247static inline u32 ram_fc_semaphorea_w(void)
248{
249 return 14U;
250}
251static inline u32 ram_fc_semaphoreb_w(void)
252{
253 return 15U;
254}
255static inline u32 ram_fc_semaphorec_w(void)
256{
257 return 16U;
258}
259static inline u32 ram_fc_semaphored_w(void)
260{
261 return 17U;
262}
263static inline u32 ram_fc_gp_base_w(void)
264{
265 return 18U;
266}
267static inline u32 ram_fc_gp_base_hi_w(void)
268{
269 return 19U;
270}
271static inline u32 ram_fc_gp_fetch_w(void)
272{
273 return 20U;
274}
275static inline u32 ram_fc_pb_fetch_w(void)
276{
277 return 21U;
278}
279static inline u32 ram_fc_pb_fetch_hi_w(void)
280{
281 return 22U;
282}
283static inline u32 ram_fc_pb_put_w(void)
284{
285 return 23U;
286}
287static inline u32 ram_fc_pb_put_hi_w(void)
288{
289 return 24U;
290}
291static inline u32 ram_fc_pb_header_w(void)
292{
293 return 33U;
294}
295static inline u32 ram_fc_pb_count_w(void)
296{
297 return 34U;
298}
299static inline u32 ram_fc_subdevice_w(void)
300{
301 return 37U;
302}
303static inline u32 ram_fc_formats_w(void)
304{
305 return 39U;
306}
307static inline u32 ram_fc_syncpointa_w(void)
308{
309 return 41U;
310}
311static inline u32 ram_fc_syncpointb_w(void)
312{
313 return 42U;
314}
315static inline u32 ram_fc_target_w(void)
316{
317 return 43U;
318}
319static inline u32 ram_fc_hce_ctrl_w(void)
320{
321 return 57U;
322}
323static inline u32 ram_fc_chid_w(void)
324{
325 return 58U;
326}
327static inline u32 ram_fc_chid_id_f(u32 v)
328{
329 return (v & 0xfffU) << 0U;
330}
331static inline u32 ram_fc_chid_id_w(void)
332{
333 return 0U;
334}
335static inline u32 ram_fc_runlist_timeslice_w(void)
336{
337 return 62U;
338}
339static inline u32 ram_fc_pb_timeslice_w(void)
340{
341 return 63U;
342}
343static inline u32 ram_userd_base_shift_v(void)
344{
345 return 0x00000009U;
346}
347static inline u32 ram_userd_chan_size_v(void)
348{
349 return 0x00000200U;
350}
351static inline u32 ram_userd_put_w(void)
352{
353 return 16U;
354}
355static inline u32 ram_userd_get_w(void)
356{
357 return 17U;
358}
359static inline u32 ram_userd_ref_w(void)
360{
361 return 18U;
362}
363static inline u32 ram_userd_put_hi_w(void)
364{
365 return 19U;
366}
367static inline u32 ram_userd_ref_threshold_w(void)
368{
369 return 20U;
370}
371static inline u32 ram_userd_top_level_get_w(void)
372{
373 return 22U;
374}
375static inline u32 ram_userd_top_level_get_hi_w(void)
376{
377 return 23U;
378}
379static inline u32 ram_userd_get_hi_w(void)
380{
381 return 24U;
382}
383static inline u32 ram_userd_gp_get_w(void)
384{
385 return 34U;
386}
387static inline u32 ram_userd_gp_put_w(void)
388{
389 return 35U;
390}
391static inline u32 ram_userd_gp_top_level_get_w(void)
392{
393 return 22U;
394}
395static inline u32 ram_userd_gp_top_level_get_hi_w(void)
396{
397 return 23U;
398}
399static inline u32 ram_rl_entry_size_v(void)
400{
401 return 0x00000008U;
402}
403static inline u32 ram_rl_entry_chid_f(u32 v)
404{
405 return (v & 0xfffU) << 0U;
406}
407static inline u32 ram_rl_entry_id_f(u32 v)
408{
409 return (v & 0xfffU) << 0U;
410}
411static inline u32 ram_rl_entry_type_f(u32 v)
412{
413 return (v & 0x1U) << 13U;
414}
415static inline u32 ram_rl_entry_type_chid_f(void)
416{
417 return 0x0U;
418}
419static inline u32 ram_rl_entry_type_tsg_f(void)
420{
421 return 0x2000U;
422}
423static inline u32 ram_rl_entry_timeslice_scale_f(u32 v)
424{
425 return (v & 0xfU) << 14U;
426}
427static inline u32 ram_rl_entry_timeslice_scale_3_f(void)
428{
429 return 0xc000U;
430}
431static inline u32 ram_rl_entry_timeslice_timeout_f(u32 v)
432{
433 return (v & 0xffU) << 18U;
434}
435static inline u32 ram_rl_entry_timeslice_timeout_128_f(void)
436{
437 return 0x2000000U;
438}
439static inline u32 ram_rl_entry_tsg_length_f(u32 v)
440{
441 return (v & 0x3fU) << 26U;
442}
443#endif
diff --git a/include/gk20a/hw_therm_gk20a.h b/include/gk20a/hw_therm_gk20a.h
deleted file mode 100644
index 075c9bc..0000000
--- a/include/gk20a/hw_therm_gk20a.h
+++ /dev/null
@@ -1,367 +0,0 @@
1/*
2 * Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22/*
23 * Function naming determines intended use:
24 *
25 * <x>_r(void) : Returns the offset for register <x>.
26 *
27 * <x>_o(void) : Returns the offset for element <x>.
28 *
29 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
30 *
31 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
32 *
33 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
34 * and masked to place it at field <y> of register <x>. This value
35 * can be |'d with others to produce a full register value for
36 * register <x>.
37 *
38 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
39 * value can be ~'d and then &'d to clear the value of field <y> for
40 * register <x>.
41 *
42 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
43 * to place it at field <y> of register <x>. This value can be |'d
44 * with others to produce a full register value for <x>.
45 *
46 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
47 * <x> value 'r' after being shifted to place its LSB at bit 0.
48 * This value is suitable for direct comparison with other unshifted
49 * values appropriate for use in field <y> of register <x>.
50 *
51 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
52 * field <y> of register <x>. This value is suitable for direct
53 * comparison with unshifted values appropriate for use in field <y>
54 * of register <x>.
55 */
56#ifndef _hw_therm_gk20a_h_
57#define _hw_therm_gk20a_h_
58
59static inline u32 therm_use_a_r(void)
60{
61 return 0x00020798U;
62}
63static inline u32 therm_use_a_ext_therm_0_enable_f(void)
64{
65 return 0x1U;
66}
67static inline u32 therm_use_a_ext_therm_1_enable_f(void)
68{
69 return 0x2U;
70}
71static inline u32 therm_use_a_ext_therm_2_enable_f(void)
72{
73 return 0x4U;
74}
75static inline u32 therm_evt_ext_therm_0_r(void)
76{
77 return 0x00020700U;
78}
79static inline u32 therm_evt_ext_therm_0_slow_factor_f(u32 v)
80{
81 return (v & 0x3fU) << 8U;
82}
83static inline u32 therm_evt_ext_therm_0_slow_factor_init_v(void)
84{
85 return 0x00000000U;
86}
87static inline u32 therm_evt_ext_therm_0_priority_f(u32 v)
88{
89 return (v & 0x1fU) << 24U;
90}
91static inline u32 therm_evt_ext_therm_1_r(void)
92{
93 return 0x00020704U;
94}
95static inline u32 therm_evt_ext_therm_1_slow_factor_f(u32 v)
96{
97 return (v & 0x3fU) << 8U;
98}
99static inline u32 therm_evt_ext_therm_1_slow_factor_init_v(void)
100{
101 return 0x00000000U;
102}
103static inline u32 therm_evt_ext_therm_1_priority_f(u32 v)
104{
105 return (v & 0x1fU) << 24U;
106}
107static inline u32 therm_evt_ext_therm_2_r(void)
108{
109 return 0x00020708U;
110}
111static inline u32 therm_evt_ext_therm_2_slow_factor_f(u32 v)
112{
113 return (v & 0x3fU) << 8U;
114}
115static inline u32 therm_evt_ext_therm_2_slow_factor_init_v(void)
116{
117 return 0x00000000U;
118}
119static inline u32 therm_evt_ext_therm_2_priority_f(u32 v)
120{
121 return (v & 0x1fU) << 24U;
122}
123static inline u32 therm_weight_1_r(void)
124{
125 return 0x00020024U;
126}
127static inline u32 therm_config1_r(void)
128{
129 return 0x00020050U;
130}
131static inline u32 therm_config2_r(void)
132{
133 return 0x00020130U;
134}
135static inline u32 therm_config2_slowdown_factor_extended_f(u32 v)
136{
137 return (v & 0x1U) << 24U;
138}
139static inline u32 therm_config2_grad_enable_f(u32 v)
140{
141 return (v & 0x1U) << 31U;
142}
143static inline u32 therm_gate_ctrl_r(u32 i)
144{
145 return 0x00020200U + i*4U;
146}
147static inline u32 therm_gate_ctrl_eng_clk_m(void)
148{
149 return 0x3U << 0U;
150}
151static inline u32 therm_gate_ctrl_eng_clk_run_f(void)
152{
153 return 0x0U;
154}
155static inline u32 therm_gate_ctrl_eng_clk_auto_f(void)
156{
157 return 0x1U;
158}
159static inline u32 therm_gate_ctrl_eng_clk_stop_f(void)
160{
161 return 0x2U;
162}
163static inline u32 therm_gate_ctrl_blk_clk_m(void)
164{
165 return 0x3U << 2U;
166}
167static inline u32 therm_gate_ctrl_blk_clk_run_f(void)
168{
169 return 0x0U;
170}
171static inline u32 therm_gate_ctrl_blk_clk_auto_f(void)
172{
173 return 0x4U;
174}
175static inline u32 therm_gate_ctrl_eng_pwr_m(void)
176{
177 return 0x3U << 4U;
178}
179static inline u32 therm_gate_ctrl_eng_pwr_auto_f(void)
180{
181 return 0x10U;
182}
183static inline u32 therm_gate_ctrl_eng_pwr_off_v(void)
184{
185 return 0x00000002U;
186}
187static inline u32 therm_gate_ctrl_eng_pwr_off_f(void)
188{
189 return 0x20U;
190}
191static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v)
192{
193 return (v & 0x1fU) << 8U;
194}
195static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void)
196{
197 return 0x1fU << 8U;
198}
199static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v)
200{
201 return (v & 0x7U) << 13U;
202}
203static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void)
204{
205 return 0x7U << 13U;
206}
207static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v)
208{
209 return (v & 0xfU) << 16U;
210}
211static inline u32 therm_gate_ctrl_eng_delay_before_m(void)
212{
213 return 0xfU << 16U;
214}
215static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v)
216{
217 return (v & 0xfU) << 20U;
218}
219static inline u32 therm_gate_ctrl_eng_delay_after_m(void)
220{
221 return 0xfU << 20U;
222}
223static inline u32 therm_fecs_idle_filter_r(void)
224{
225 return 0x00020288U;
226}
227static inline u32 therm_fecs_idle_filter_value_m(void)
228{
229 return 0xffffffffU << 0U;
230}
231static inline u32 therm_hubmmu_idle_filter_r(void)
232{
233 return 0x0002028cU;
234}
235static inline u32 therm_hubmmu_idle_filter_value_m(void)
236{
237 return 0xffffffffU << 0U;
238}
239static inline u32 therm_clk_slowdown_r(u32 i)
240{
241 return 0x00020160U + i*4U;
242}
243static inline u32 therm_clk_slowdown_idle_factor_f(u32 v)
244{
245 return (v & 0x3fU) << 16U;
246}
247static inline u32 therm_clk_slowdown_idle_factor_m(void)
248{
249 return 0x3fU << 16U;
250}
251static inline u32 therm_clk_slowdown_idle_factor_v(u32 r)
252{
253 return (r >> 16U) & 0x3fU;
254}
255static inline u32 therm_clk_slowdown_idle_factor_disabled_f(void)
256{
257 return 0x0U;
258}
259static inline u32 therm_grad_stepping_table_r(u32 i)
260{
261 return 0x000202c8U + i*4U;
262}
263static inline u32 therm_grad_stepping_table_slowdown_factor0_f(u32 v)
264{
265 return (v & 0x3fU) << 0U;
266}
267static inline u32 therm_grad_stepping_table_slowdown_factor0_m(void)
268{
269 return 0x3fU << 0U;
270}
271static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f(void)
272{
273 return 0x1U;
274}
275static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f(void)
276{
277 return 0x2U;
278}
279static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f(void)
280{
281 return 0x6U;
282}
283static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f(void)
284{
285 return 0xeU;
286}
287static inline u32 therm_grad_stepping_table_slowdown_factor1_f(u32 v)
288{
289 return (v & 0x3fU) << 6U;
290}
291static inline u32 therm_grad_stepping_table_slowdown_factor1_m(void)
292{
293 return 0x3fU << 6U;
294}
295static inline u32 therm_grad_stepping_table_slowdown_factor2_f(u32 v)
296{
297 return (v & 0x3fU) << 12U;
298}
299static inline u32 therm_grad_stepping_table_slowdown_factor2_m(void)
300{
301 return 0x3fU << 12U;
302}
303static inline u32 therm_grad_stepping_table_slowdown_factor3_f(u32 v)
304{
305 return (v & 0x3fU) << 18U;
306}
307static inline u32 therm_grad_stepping_table_slowdown_factor3_m(void)
308{
309 return 0x3fU << 18U;
310}
311static inline u32 therm_grad_stepping_table_slowdown_factor4_f(u32 v)
312{
313 return (v & 0x3fU) << 24U;
314}
315static inline u32 therm_grad_stepping_table_slowdown_factor4_m(void)
316{
317 return 0x3fU << 24U;
318}
319static inline u32 therm_grad_stepping0_r(void)
320{
321 return 0x000202c0U;
322}
323static inline u32 therm_grad_stepping0_feature_s(void)
324{
325 return 1U;
326}
327static inline u32 therm_grad_stepping0_feature_f(u32 v)
328{
329 return (v & 0x1U) << 0U;
330}
331static inline u32 therm_grad_stepping0_feature_m(void)
332{
333 return 0x1U << 0U;
334}
335static inline u32 therm_grad_stepping0_feature_v(u32 r)
336{
337 return (r >> 0U) & 0x1U;
338}
339static inline u32 therm_grad_stepping0_feature_enable_f(void)
340{
341 return 0x1U;
342}
343static inline u32 therm_grad_stepping1_r(void)
344{
345 return 0x000202c4U;
346}
347static inline u32 therm_grad_stepping1_pdiv_duration_f(u32 v)
348{
349 return (v & 0x1ffffU) << 0U;
350}
351static inline u32 therm_clk_timing_r(u32 i)
352{
353 return 0x000203c0U + i*4U;
354}
355static inline u32 therm_clk_timing_grad_slowdown_f(u32 v)
356{
357 return (v & 0x1U) << 16U;
358}
359static inline u32 therm_clk_timing_grad_slowdown_m(void)
360{
361 return 0x1U << 16U;
362}
363static inline u32 therm_clk_timing_grad_slowdown_enabled_f(void)
364{
365 return 0x10000U;
366}
367#endif
diff --git a/include/gk20a/hw_timer_gk20a.h b/include/gk20a/hw_timer_gk20a.h
deleted file mode 100644
index 972d68a..0000000
--- a/include/gk20a/hw_timer_gk20a.h
+++ /dev/null
@@ -1,127 +0,0 @@
1/*
2 * Copyright (c) 2013-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22/*
23 * Function naming determines intended use:
24 *
25 * <x>_r(void) : Returns the offset for register <x>.
26 *
27 * <x>_o(void) : Returns the offset for element <x>.
28 *
29 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
30 *
31 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
32 *
33 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
34 * and masked to place it at field <y> of register <x>. This value
35 * can be |'d with others to produce a full register value for
36 * register <x>.
37 *
38 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
39 * value can be ~'d and then &'d to clear the value of field <y> for
40 * register <x>.
41 *
42 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
43 * to place it at field <y> of register <x>. This value can be |'d
44 * with others to produce a full register value for <x>.
45 *
46 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
47 * <x> value 'r' after being shifted to place its LSB at bit 0.
48 * This value is suitable for direct comparison with other unshifted
49 * values appropriate for use in field <y> of register <x>.
50 *
51 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
52 * field <y> of register <x>. This value is suitable for direct
53 * comparison with unshifted values appropriate for use in field <y>
54 * of register <x>.
55 */
56#ifndef _hw_timer_gk20a_h_
57#define _hw_timer_gk20a_h_
58
59static inline u32 timer_pri_timeout_r(void)
60{
61 return 0x00009080U;
62}
63static inline u32 timer_pri_timeout_period_f(u32 v)
64{
65 return (v & 0xffffffU) << 0U;
66}
67static inline u32 timer_pri_timeout_period_m(void)
68{
69 return 0xffffffU << 0U;
70}
71static inline u32 timer_pri_timeout_period_v(u32 r)
72{
73 return (r >> 0U) & 0xffffffU;
74}
75static inline u32 timer_pri_timeout_en_f(u32 v)
76{
77 return (v & 0x1U) << 31U;
78}
79static inline u32 timer_pri_timeout_en_m(void)
80{
81 return 0x1U << 31U;
82}
83static inline u32 timer_pri_timeout_en_v(u32 r)
84{
85 return (r >> 31U) & 0x1U;
86}
87static inline u32 timer_pri_timeout_en_en_enabled_f(void)
88{
89 return 0x80000000U;
90}
91static inline u32 timer_pri_timeout_en_en_disabled_f(void)
92{
93 return 0x0U;
94}
95static inline u32 timer_pri_timeout_save_0_r(void)
96{
97 return 0x00009084U;
98}
99static inline u32 timer_pri_timeout_save_0_fecs_tgt_v(u32 r)
100{
101 return (r >> 31U) & 0x1U;
102}
103static inline u32 timer_pri_timeout_save_0_addr_v(u32 r)
104{
105 return (r >> 2U) & 0x3fffffU;
106}
107static inline u32 timer_pri_timeout_save_0_write_v(u32 r)
108{
109 return (r >> 1U) & 0x1U;
110}
111static inline u32 timer_pri_timeout_save_1_r(void)
112{
113 return 0x00009088U;
114}
115static inline u32 timer_pri_timeout_fecs_errcode_r(void)
116{
117 return 0x0000908cU;
118}
119static inline u32 timer_time_0_r(void)
120{
121 return 0x00009400U;
122}
123static inline u32 timer_time_1_r(void)
124{
125 return 0x00009410U;
126}
127#endif
diff --git a/include/gk20a/hw_top_gk20a.h b/include/gk20a/hw_top_gk20a.h
deleted file mode 100644
index be7fa4a..0000000
--- a/include/gk20a/hw_top_gk20a.h
+++ /dev/null
@@ -1,211 +0,0 @@
1/*
2 * Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22/*
23 * Function naming determines intended use:
24 *
25 * <x>_r(void) : Returns the offset for register <x>.
26 *
27 * <x>_o(void) : Returns the offset for element <x>.
28 *
29 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
30 *
31 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
32 *
33 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
34 * and masked to place it at field <y> of register <x>. This value
35 * can be |'d with others to produce a full register value for
36 * register <x>.
37 *
38 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
39 * value can be ~'d and then &'d to clear the value of field <y> for
40 * register <x>.
41 *
42 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
43 * to place it at field <y> of register <x>. This value can be |'d
44 * with others to produce a full register value for <x>.
45 *
46 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
47 * <x> value 'r' after being shifted to place its LSB at bit 0.
48 * This value is suitable for direct comparison with other unshifted
49 * values appropriate for use in field <y> of register <x>.
50 *
51 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
52 * field <y> of register <x>. This value is suitable for direct
53 * comparison with unshifted values appropriate for use in field <y>
54 * of register <x>.
55 */
56#ifndef _hw_top_gk20a_h_
57#define _hw_top_gk20a_h_
58
59static inline u32 top_num_gpcs_r(void)
60{
61 return 0x00022430U;
62}
63static inline u32 top_num_gpcs_value_v(u32 r)
64{
65 return (r >> 0U) & 0x1fU;
66}
67static inline u32 top_tpc_per_gpc_r(void)
68{
69 return 0x00022434U;
70}
71static inline u32 top_tpc_per_gpc_value_v(u32 r)
72{
73 return (r >> 0U) & 0x1fU;
74}
75static inline u32 top_num_fbps_r(void)
76{
77 return 0x00022438U;
78}
79static inline u32 top_num_fbps_value_v(u32 r)
80{
81 return (r >> 0U) & 0x1fU;
82}
83static inline u32 top_device_info_r(u32 i)
84{
85 return 0x00022700U + i*4U;
86}
87static inline u32 top_device_info__size_1_v(void)
88{
89 return 0x00000040U;
90}
91static inline u32 top_device_info_chain_v(u32 r)
92{
93 return (r >> 31U) & 0x1U;
94}
95static inline u32 top_device_info_chain_enable_v(void)
96{
97 return 0x00000001U;
98}
99static inline u32 top_device_info_engine_enum_v(u32 r)
100{
101 return (r >> 26U) & 0xfU;
102}
103static inline u32 top_device_info_runlist_enum_v(u32 r)
104{
105 return (r >> 21U) & 0xfU;
106}
107static inline u32 top_device_info_intr_enum_v(u32 r)
108{
109 return (r >> 15U) & 0x1fU;
110}
111static inline u32 top_device_info_reset_enum_v(u32 r)
112{
113 return (r >> 9U) & 0x1fU;
114}
115static inline u32 top_device_info_type_enum_v(u32 r)
116{
117 return (r >> 2U) & 0x1fffffffU;
118}
119static inline u32 top_device_info_type_enum_graphics_v(void)
120{
121 return 0x00000000U;
122}
123static inline u32 top_device_info_type_enum_graphics_f(void)
124{
125 return 0x0U;
126}
127static inline u32 top_device_info_type_enum_copy0_v(void)
128{
129 return 0x00000001U;
130}
131static inline u32 top_device_info_type_enum_copy0_f(void)
132{
133 return 0x4U;
134}
135static inline u32 top_device_info_type_enum_copy1_v(void)
136{
137 return 0x00000002U;
138}
139static inline u32 top_device_info_type_enum_copy1_f(void)
140{
141 return 0x8U;
142}
143static inline u32 top_device_info_type_enum_copy2_v(void)
144{
145 return 0x00000003U;
146}
147static inline u32 top_device_info_type_enum_copy2_f(void)
148{
149 return 0xcU;
150}
151static inline u32 top_device_info_engine_v(u32 r)
152{
153 return (r >> 5U) & 0x1U;
154}
155static inline u32 top_device_info_runlist_v(u32 r)
156{
157 return (r >> 4U) & 0x1U;
158}
159static inline u32 top_device_info_intr_v(u32 r)
160{
161 return (r >> 3U) & 0x1U;
162}
163static inline u32 top_device_info_reset_v(u32 r)
164{
165 return (r >> 2U) & 0x1U;
166}
167static inline u32 top_device_info_entry_v(u32 r)
168{
169 return (r >> 0U) & 0x3U;
170}
171static inline u32 top_device_info_entry_not_valid_v(void)
172{
173 return 0x00000000U;
174}
175static inline u32 top_device_info_entry_enum_v(void)
176{
177 return 0x00000002U;
178}
179static inline u32 top_device_info_entry_engine_type_v(void)
180{
181 return 0x00000003U;
182}
183static inline u32 top_device_info_entry_data_v(void)
184{
185 return 0x00000001U;
186}
187static inline u32 top_fs_status_fbp_r(void)
188{
189 return 0x00022548U;
190}
191static inline u32 top_fs_status_fbp_cluster_v(u32 r)
192{
193 return (r >> 0U) & 0xffffU;
194}
195static inline u32 top_fs_status_fbp_cluster_enable_v(void)
196{
197 return 0x00000000U;
198}
199static inline u32 top_fs_status_fbp_cluster_enable_f(void)
200{
201 return 0x0U;
202}
203static inline u32 top_fs_status_fbp_cluster_disable_v(void)
204{
205 return 0x00000001U;
206}
207static inline u32 top_fs_status_fbp_cluster_disable_f(void)
208{
209 return 0x1U;
210}
211#endif
diff --git a/include/gk20a/hw_trim_gk20a.h b/include/gk20a/hw_trim_gk20a.h
deleted file mode 100644
index f28c21f..0000000
--- a/include/gk20a/hw_trim_gk20a.h
+++ /dev/null
@@ -1,315 +0,0 @@
1/*
2 * Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22/*
23 * Function naming determines intended use:
24 *
25 * <x>_r(void) : Returns the offset for register <x>.
26 *
27 * <x>_o(void) : Returns the offset for element <x>.
28 *
29 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
30 *
31 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
32 *
33 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
34 * and masked to place it at field <y> of register <x>. This value
35 * can be |'d with others to produce a full register value for
36 * register <x>.
37 *
38 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
39 * value can be ~'d and then &'d to clear the value of field <y> for
40 * register <x>.
41 *
42 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
43 * to place it at field <y> of register <x>. This value can be |'d
44 * with others to produce a full register value for <x>.
45 *
46 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
47 * <x> value 'r' after being shifted to place its LSB at bit 0.
48 * This value is suitable for direct comparison with other unshifted
49 * values appropriate for use in field <y> of register <x>.
50 *
51 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
52 * field <y> of register <x>. This value is suitable for direct
53 * comparison with unshifted values appropriate for use in field <y>
54 * of register <x>.
55 */
56#ifndef _hw_trim_gk20a_h_
57#define _hw_trim_gk20a_h_
58
59static inline u32 trim_sys_gpcpll_cfg_r(void)
60{
61 return 0x00137000U;
62}
63static inline u32 trim_sys_gpcpll_cfg_enable_m(void)
64{
65 return 0x1U << 0U;
66}
67static inline u32 trim_sys_gpcpll_cfg_enable_v(u32 r)
68{
69 return (r >> 0U) & 0x1U;
70}
71static inline u32 trim_sys_gpcpll_cfg_enable_no_f(void)
72{
73 return 0x0U;
74}
75static inline u32 trim_sys_gpcpll_cfg_enable_yes_f(void)
76{
77 return 0x1U;
78}
79static inline u32 trim_sys_gpcpll_cfg_iddq_m(void)
80{
81 return 0x1U << 1U;
82}
83static inline u32 trim_sys_gpcpll_cfg_iddq_v(u32 r)
84{
85 return (r >> 1U) & 0x1U;
86}
87static inline u32 trim_sys_gpcpll_cfg_iddq_power_on_v(void)
88{
89 return 0x00000000U;
90}
91static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_m(void)
92{
93 return 0x1U << 4U;
94}
95static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_power_on_f(void)
96{
97 return 0x0U;
98}
99static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_power_off_f(void)
100{
101 return 0x10U;
102}
103static inline u32 trim_sys_gpcpll_cfg_pll_lock_v(u32 r)
104{
105 return (r >> 17U) & 0x1U;
106}
107static inline u32 trim_sys_gpcpll_cfg_pll_lock_true_f(void)
108{
109 return 0x20000U;
110}
111static inline u32 trim_sys_gpcpll_coeff_r(void)
112{
113 return 0x00137004U;
114}
115static inline u32 trim_sys_gpcpll_coeff_mdiv_f(u32 v)
116{
117 return (v & 0xffU) << 0U;
118}
119static inline u32 trim_sys_gpcpll_coeff_mdiv_m(void)
120{
121 return 0xffU << 0U;
122}
123static inline u32 trim_sys_gpcpll_coeff_mdiv_v(u32 r)
124{
125 return (r >> 0U) & 0xffU;
126}
127static inline u32 trim_sys_gpcpll_coeff_ndiv_f(u32 v)
128{
129 return (v & 0xffU) << 8U;
130}
131static inline u32 trim_sys_gpcpll_coeff_ndiv_m(void)
132{
133 return 0xffU << 8U;
134}
135static inline u32 trim_sys_gpcpll_coeff_ndiv_v(u32 r)
136{
137 return (r >> 8U) & 0xffU;
138}
139static inline u32 trim_sys_gpcpll_coeff_pldiv_f(u32 v)
140{
141 return (v & 0x3fU) << 16U;
142}
143static inline u32 trim_sys_gpcpll_coeff_pldiv_m(void)
144{
145 return 0x3fU << 16U;
146}
147static inline u32 trim_sys_gpcpll_coeff_pldiv_v(u32 r)
148{
149 return (r >> 16U) & 0x3fU;
150}
151static inline u32 trim_sys_sel_vco_r(void)
152{
153 return 0x00137100U;
154}
155static inline u32 trim_sys_sel_vco_gpc2clk_out_m(void)
156{
157 return 0x1U << 0U;
158}
159static inline u32 trim_sys_sel_vco_gpc2clk_out_init_v(void)
160{
161 return 0x00000000U;
162}
163static inline u32 trim_sys_sel_vco_gpc2clk_out_init_f(void)
164{
165 return 0x0U;
166}
167static inline u32 trim_sys_sel_vco_gpc2clk_out_bypass_f(void)
168{
169 return 0x0U;
170}
171static inline u32 trim_sys_sel_vco_gpc2clk_out_vco_f(void)
172{
173 return 0x1U;
174}
175static inline u32 trim_sys_gpc2clk_out_r(void)
176{
177 return 0x00137250U;
178}
179static inline u32 trim_sys_gpc2clk_out_bypdiv_s(void)
180{
181 return 6U;
182}
183static inline u32 trim_sys_gpc2clk_out_bypdiv_f(u32 v)
184{
185 return (v & 0x3fU) << 0U;
186}
187static inline u32 trim_sys_gpc2clk_out_bypdiv_m(void)
188{
189 return 0x3fU << 0U;
190}
191static inline u32 trim_sys_gpc2clk_out_bypdiv_v(u32 r)
192{
193 return (r >> 0U) & 0x3fU;
194}
195static inline u32 trim_sys_gpc2clk_out_bypdiv_by31_f(void)
196{
197 return 0x3cU;
198}
199static inline u32 trim_sys_gpc2clk_out_vcodiv_s(void)
200{
201 return 6U;
202}
203static inline u32 trim_sys_gpc2clk_out_vcodiv_f(u32 v)
204{
205 return (v & 0x3fU) << 8U;
206}
207static inline u32 trim_sys_gpc2clk_out_vcodiv_m(void)
208{
209 return 0x3fU << 8U;
210}
211static inline u32 trim_sys_gpc2clk_out_vcodiv_v(u32 r)
212{
213 return (r >> 8U) & 0x3fU;
214}
215static inline u32 trim_sys_gpc2clk_out_vcodiv_by1_f(void)
216{
217 return 0x0U;
218}
219static inline u32 trim_sys_gpc2clk_out_sdiv14_m(void)
220{
221 return 0x1U << 31U;
222}
223static inline u32 trim_sys_gpc2clk_out_sdiv14_indiv4_mode_f(void)
224{
225 return 0x80000000U;
226}
227static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_r(u32 i)
228{
229 return 0x00134124U + i*512U;
230}
231static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_noofipclks_f(u32 v)
232{
233 return (v & 0x3fffU) << 0U;
234}
235static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_write_en_asserted_f(void)
236{
237 return 0x10000U;
238}
239static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_enable_asserted_f(void)
240{
241 return 0x100000U;
242}
243static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_reset_asserted_f(void)
244{
245 return 0x1000000U;
246}
247static inline u32 trim_gpc_clk_cntr_ncgpcclk_cnt_r(u32 i)
248{
249 return 0x00134128U + i*512U;
250}
251static inline u32 trim_gpc_clk_cntr_ncgpcclk_cnt_value_v(u32 r)
252{
253 return (r >> 0U) & 0xfffffU;
254}
255static inline u32 trim_sys_gpcpll_cfg2_r(void)
256{
257 return 0x0013700cU;
258}
259static inline u32 trim_sys_gpcpll_cfg2_pll_stepa_f(u32 v)
260{
261 return (v & 0xffU) << 24U;
262}
263static inline u32 trim_sys_gpcpll_cfg2_pll_stepa_m(void)
264{
265 return 0xffU << 24U;
266}
267static inline u32 trim_sys_gpcpll_cfg3_r(void)
268{
269 return 0x00137018U;
270}
271static inline u32 trim_sys_gpcpll_cfg3_pll_stepb_f(u32 v)
272{
273 return (v & 0xffU) << 16U;
274}
275static inline u32 trim_sys_gpcpll_cfg3_pll_stepb_m(void)
276{
277 return 0xffU << 16U;
278}
279static inline u32 trim_sys_gpcpll_ndiv_slowdown_r(void)
280{
281 return 0x0013701cU;
282}
283static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_m(void)
284{
285 return 0x1U << 22U;
286}
287static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_yes_f(void)
288{
289 return 0x400000U;
290}
291static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_no_f(void)
292{
293 return 0x0U;
294}
295static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_m(void)
296{
297 return 0x1U << 31U;
298}
299static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_yes_f(void)
300{
301 return 0x80000000U;
302}
303static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_no_f(void)
304{
305 return 0x0U;
306}
307static inline u32 trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_r(void)
308{
309 return 0x001328a0U;
310}
311static inline u32 trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_pll_dynramp_done_synced_v(u32 r)
312{
313 return (r >> 24U) & 0x1U;
314}
315#endif
diff --git a/include/nvgpu/acr/nvgpu_acr.h b/include/nvgpu/acr/nvgpu_acr.h
index 7a0143e..cdb7bb8 100644
--- a/include/nvgpu/acr/nvgpu_acr.h
+++ b/include/nvgpu/acr/nvgpu_acr.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2016-2021, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"), 5 * copy of this software and associated documentation files (the "Software"),
@@ -39,7 +39,11 @@ struct hs_acr;
39struct nvgpu_acr; 39struct nvgpu_acr;
40 40
41#define HSBIN_ACR_BL_UCODE_IMAGE "pmu_bl.bin" 41#define HSBIN_ACR_BL_UCODE_IMAGE "pmu_bl.bin"
42#define GM20B_HSBIN_ACR_PROD_UCODE "nv_acr_ucode_prod.bin"
43#define GM20B_HSBIN_ACR_DBG_UCODE "nv_acr_ucode_dbg.bin"
42#define HSBIN_ACR_UCODE_IMAGE "acr_ucode.bin" 44#define HSBIN_ACR_UCODE_IMAGE "acr_ucode.bin"
45#define HSBIN_ACR_PROD_UCODE "acr_ucode_prod.bin"
46#define HSBIN_ACR_DBG_UCODE "acr_ucode_dbg.bin"
43#define HSBIN_ACR_AHESASC_PROD_UCODE "acr_ahesasc_prod_ucode.bin" 47#define HSBIN_ACR_AHESASC_PROD_UCODE "acr_ahesasc_prod_ucode.bin"
44#define HSBIN_ACR_ASB_PROD_UCODE "acr_asb_prod_ucode.bin" 48#define HSBIN_ACR_ASB_PROD_UCODE "acr_asb_prod_ucode.bin"
45#define HSBIN_ACR_AHESASC_DBG_UCODE "acr_ahesasc_dbg_ucode.bin" 49#define HSBIN_ACR_AHESASC_DBG_UCODE "acr_ahesasc_dbg_ucode.bin"
diff --git a/include/nvgpu/bug.h b/include/nvgpu/bug.h
index 3d139b7..82d641b 100644
--- a/include/nvgpu/bug.h
+++ b/include/nvgpu/bug.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"), 5 * copy of this software and associated documentation files (the "Software"),
@@ -24,6 +24,24 @@
24 24
25#ifdef __KERNEL__ 25#ifdef __KERNEL__
26#include <linux/bug.h> 26#include <linux/bug.h>
27/*
28 * Define an assert macro that code within nvgpu can use.
29 *
30 * The goal of this macro is for debugging but what that means varies from OS
31 * to OS. On Linux wee don't want to BUG() for general driver misbehaving. BUG()
32 * is a very heavy handed tool - in fact there's probably no where within the
33 * nvgpu core code where it makes sense to use a BUG() when running under Linux.
34 *
35 * However, on QNX (and POSIX) BUG() will just kill the current process. This
36 * means we can use it for handling bugs in nvgpu.
37 *
38 * As a result this macro varies depending on platform.
39 */
40#define nvgpu_assert(cond) ((void) WARN_ON(!(cond)))
41#define nvgpu_do_assert_print(g, fmt, arg...) \
42 do { \
43 nvgpu_err(g, fmt, ##arg); \
44 } while (false)
27#elif defined(__NVGPU_POSIX__) 45#elif defined(__NVGPU_POSIX__)
28#include <nvgpu/posix/bug.h> 46#include <nvgpu/posix/bug.h>
29#else 47#else
diff --git a/include/nvgpu/enabled.h b/include/nvgpu/enabled.h
index ef55dad..51e9358 100644
--- a/include/nvgpu/enabled.h
+++ b/include/nvgpu/enabled.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2017-2022, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"), 5 * copy of this software and associated documentation files (the "Software"),
@@ -85,7 +85,12 @@ struct gk20a;
85#define NVGPU_MM_USE_PHYSICAL_SG 27 85#define NVGPU_MM_USE_PHYSICAL_SG 27
86/* WAR for gm20b chips. */ 86/* WAR for gm20b chips. */
87#define NVGPU_MM_FORCE_128K_PMU_VM 28 87#define NVGPU_MM_FORCE_128K_PMU_VM 28
88 88/* SW ERRATA to disable L3 alloc Bit of the physical address.
89 * Bit number varies between SOCs.
90 * E.g. 64GB physical RAM support for gv11b requires this SW errata
91 * to be enabled.
92 */
93#define NVGPU_DISABLE_L3_SUPPORT 29
89/* 94/*
90 * Host flags 95 * Host flags
91 */ 96 */
diff --git a/include/nvgpu/gk20a.h b/include/nvgpu/gk20a.h
index aa95969..19bfaee 100644
--- a/include/nvgpu/gk20a.h
+++ b/include/nvgpu/gk20a.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2011-2020, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2011-2022, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * GK20A Graphics 4 * GK20A Graphics
5 * 5 *
@@ -517,6 +517,7 @@ struct gpu_ops {
517 u32 *priv_addr_table, 517 u32 *priv_addr_table,
518 u32 *priv_addr_table_index); 518 u32 *priv_addr_table_index);
519 u32 (*fecs_ctxsw_mailbox_size)(void); 519 u32 (*fecs_ctxsw_mailbox_size)(void);
520 u32 (*gpc0_gpccs_ctxsw_mailbox_size)(void);
520 int (*init_sw_bundle64)(struct gk20a *g); 521 int (*init_sw_bundle64)(struct gk20a *g);
521 int (*alloc_global_ctx_buffers)(struct gk20a *g); 522 int (*alloc_global_ctx_buffers)(struct gk20a *g);
522 int (*map_global_ctx_buffers)(struct gk20a *g, 523 int (*map_global_ctx_buffers)(struct gk20a *g,
@@ -719,7 +720,7 @@ struct gpu_ops {
719 struct ch_state *ch_state); 720 struct ch_state *ch_state);
720 u32 (*intr_0_error_mask)(struct gk20a *g); 721 u32 (*intr_0_error_mask)(struct gk20a *g);
721 int (*is_preempt_pending)(struct gk20a *g, u32 id, 722 int (*is_preempt_pending)(struct gk20a *g, u32 id,
722 unsigned int id_type); 723 unsigned int id_type, bool preempt_retries_left);
723 void (*init_pbdma_intr_descs)(struct fifo_gk20a *f); 724 void (*init_pbdma_intr_descs)(struct fifo_gk20a *f);
724 int (*reset_enable_hw)(struct gk20a *g); 725 int (*reset_enable_hw)(struct gk20a *g);
725 int (*setup_userd)(struct channel_gk20a *c); 726 int (*setup_userd)(struct channel_gk20a *c);
@@ -1079,6 +1080,7 @@ struct gpu_ops {
1079 u32 (*pmu_pg_supported_engines_list)(struct gk20a *g); 1080 u32 (*pmu_pg_supported_engines_list)(struct gk20a *g);
1080 u32 (*pmu_pg_engines_feature_list)(struct gk20a *g, 1081 u32 (*pmu_pg_engines_feature_list)(struct gk20a *g,
1081 u32 pg_engine_id); 1082 u32 pg_engine_id);
1083 int (*pmu_process_pg_event)(struct gk20a *g, void *pmumsg);
1082 bool (*pmu_is_lpwr_feature_supported)(struct gk20a *g, 1084 bool (*pmu_is_lpwr_feature_supported)(struct gk20a *g,
1083 u32 feature_id); 1085 u32 feature_id);
1084 int (*pmu_lpwr_enable_pg)(struct gk20a *g, bool pstate_lock); 1086 int (*pmu_lpwr_enable_pg)(struct gk20a *g, bool pstate_lock);
@@ -1793,6 +1795,8 @@ bool gk20a_check_poweron(struct gk20a *g);
1793int gk20a_prepare_poweroff(struct gk20a *g); 1795int gk20a_prepare_poweroff(struct gk20a *g);
1794int gk20a_finalize_poweron(struct gk20a *g); 1796int gk20a_finalize_poweron(struct gk20a *g);
1795 1797
1798int nvgpu_wait_for_stall_interrupts(struct gk20a *g, u32 timeout);
1799int nvgpu_wait_for_nonstall_interrupts(struct gk20a *g, u32 timeout);
1796void nvgpu_wait_for_deferred_interrupts(struct gk20a *g); 1800void nvgpu_wait_for_deferred_interrupts(struct gk20a *g);
1797 1801
1798struct gk20a * __must_check gk20a_get(struct gk20a *g); 1802struct gk20a * __must_check gk20a_get(struct gk20a *g);
diff --git a/include/nvgpu/hw/gk20a/hw_gr_gk20a.h b/include/nvgpu/hw/gk20a/hw_gr_gk20a.h
index 826108f..376cc8f 100644
--- a/include/nvgpu/hw/gk20a/hw_gr_gk20a.h
+++ b/include/nvgpu/hw/gk20a/hw_gr_gk20a.h
@@ -1380,6 +1380,10 @@ static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void)
1380{ 1380{
1381 return 0x00502400U; 1381 return 0x00502400U;
1382} 1382}
1383static inline u32 gr_gpc0_gpccs_ctxsw_mailbox__size_1_v(void)
1384{
1385 return 0x00000010U;
1386}
1383static inline u32 gr_fecs_ctxsw_idlestate_r(void) 1387static inline u32 gr_fecs_ctxsw_idlestate_r(void)
1384{ 1388{
1385 return 0x00409420U; 1389 return 0x00409420U;
@@ -3804,4 +3808,61 @@ static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f(void)
3804{ 3808{
3805 return 0x40000000U; 3809 return 0x40000000U;
3806} 3810}
3811
3812static inline u32 gr_gpc0_gpccs_falcon_irqstat_r(void)
3813{
3814 return 0x00502008U;
3815}
3816static inline u32 gr_gpc0_gpccs_falcon_irqmode_r(void)
3817{
3818 return 0x0050200cU;
3819}
3820static inline u32 gr_gpc0_gpccs_falcon_irqmask_r(void)
3821{
3822 return 0x00502018U;
3823}
3824static inline u32 gr_gpc0_gpccs_falcon_irqdest_r(void)
3825{
3826 return 0x0050201cU;
3827}
3828static inline u32 gr_gpc0_gpccs_falcon_debug1_r(void)
3829{
3830 return 0x00502090U;
3831}
3832static inline u32 gr_gpc0_gpccs_falcon_debuginfo_r(void)
3833{
3834 return 0x00502094U;
3835}
3836static inline u32 gr_gpc0_gpccs_falcon_engctl_r(void)
3837{
3838 return 0x005020a4U;
3839}
3840static inline u32 gr_gpc0_gpccs_falcon_curctx_r(void)
3841{
3842 return 0x00502050U;
3843}
3844static inline u32 gr_gpc0_gpccs_falcon_nxtctx_r(void)
3845{
3846 return 0x00502054U;
3847}
3848static inline u32 gr_gpc0_gpccs_ctxsw_mailbox_r(u32 i)
3849{
3850 return 0x00502800U + i*4U;
3851}
3852static inline u32 gr_gpc0_gpccs_falcon_icd_cmd_r(void)
3853{
3854 return 0x00502200U;
3855}
3856static inline u32 gr_gpc0_gpccs_falcon_icd_cmd_opc_rreg_f(void)
3857{
3858 return 0x8U;
3859}
3860static inline u32 gr_gpc0_gpccs_falcon_icd_cmd_idx_f(u32 v)
3861{
3862 return (v & 0x1fU) << 8U;
3863}
3864static inline u32 gr_gpc_gpccs_falcon_icd_rdata_r(void)
3865{
3866 return 0x0050220cU;
3867}
3807#endif 3868#endif
diff --git a/include/nvgpu/hw/gm20b/hw_gr_gm20b.h b/include/nvgpu/hw/gm20b/hw_gr_gm20b.h
index 5bbb3b9..79ad326 100644
--- a/include/nvgpu/hw/gm20b/hw_gr_gm20b.h
+++ b/include/nvgpu/hw/gm20b/hw_gr_gm20b.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2014-2023, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"), 5 * copy of this software and associated documentation files (the "Software"),
@@ -1396,6 +1396,10 @@ static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void)
1396{ 1396{
1397 return 0x00502400U; 1397 return 0x00502400U;
1398} 1398}
1399static inline u32 gr_gpc0_gpccs_ctxsw_mailbox__size_1_v(void)
1400{
1401 return 0x00000010U;
1402}
1399static inline u32 gr_fecs_ctxsw_idlestate_r(void) 1403static inline u32 gr_fecs_ctxsw_idlestate_r(void)
1400{ 1404{
1401 return 0x00409420U; 1405 return 0x00409420U;
@@ -2344,6 +2348,14 @@ static inline u32 gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_m(void)
2344{ 2348{
2345 return 0x1U << 4U; 2349 return 0x1U << 4U;
2346} 2350}
2351static inline u32 gr_gpcs_tpcs_tex_m_dbg2_tex_rd_coalesce_en_f(u32 v)
2352{
2353 return (v & 0x1U) << 5U;
2354}
2355static inline u32 gr_gpcs_tpcs_tex_m_dbg2_tex_rd_coalesce_en_m(void)
2356{
2357 return 0x1U << 5U;
2358}
2347static inline u32 gr_gpccs_falcon_addr_r(void) 2359static inline u32 gr_gpccs_falcon_addr_r(void)
2348{ 2360{
2349 return 0x0041a0acU; 2361 return 0x0041a0acU;
diff --git a/include/nvgpu/hw/gp106/hw_gr_gp106.h b/include/nvgpu/hw/gp106/hw_gr_gp106.h
index 3ebed7e..ac82901 100644
--- a/include/nvgpu/hw/gp106/hw_gr_gp106.h
+++ b/include/nvgpu/hw/gp106/hw_gr_gp106.h
@@ -1508,6 +1508,10 @@ static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void)
1508{ 1508{
1509 return 0x00502400U; 1509 return 0x00502400U;
1510} 1510}
1511static inline u32 gr_gpc0_gpccs_ctxsw_mailbox__size_1_v(void)
1512{
1513 return 0x00000010U;
1514}
1511static inline u32 gr_fecs_ctxsw_idlestate_r(void) 1515static inline u32 gr_fecs_ctxsw_idlestate_r(void)
1512{ 1516{
1513 return 0x00409420U; 1517 return 0x00409420U;
diff --git a/include/nvgpu/hw/gp10b/hw_gr_gp10b.h b/include/nvgpu/hw/gp10b/hw_gr_gp10b.h
index f7bc4c2..89c6bba 100644
--- a/include/nvgpu/hw/gp10b/hw_gr_gp10b.h
+++ b/include/nvgpu/hw/gp10b/hw_gr_gp10b.h
@@ -1584,6 +1584,10 @@ static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void)
1584{ 1584{
1585 return 0x00502400U; 1585 return 0x00502400U;
1586} 1586}
1587static inline u32 gr_gpc0_gpccs_ctxsw_mailbox__size_1_v(void)
1588{
1589 return 0x00000010U;
1590}
1587static inline u32 gr_fecs_ctxsw_idlestate_r(void) 1591static inline u32 gr_fecs_ctxsw_idlestate_r(void)
1588{ 1592{
1589 return 0x00409420U; 1593 return 0x00409420U;
diff --git a/include/nvgpu/hw/gv100/hw_gr_gv100.h b/include/nvgpu/hw/gv100/hw_gr_gv100.h
index 0f83d6b..3955a63 100644
--- a/include/nvgpu/hw/gv100/hw_gr_gv100.h
+++ b/include/nvgpu/hw/gv100/hw_gr_gv100.h
@@ -1816,6 +1816,10 @@ static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void)
1816{ 1816{
1817 return 0x00502400U; 1817 return 0x00502400U;
1818} 1818}
1819static inline u32 gr_gpc0_gpccs_ctxsw_mailbox__size_1_v(void)
1820{
1821 return 0x00000010U;
1822}
1819static inline u32 gr_fecs_ctxsw_idlestate_r(void) 1823static inline u32 gr_fecs_ctxsw_idlestate_r(void)
1820{ 1824{
1821 return 0x00409420U; 1825 return 0x00409420U;
diff --git a/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
index f7d8089..4a3da79 100644
--- a/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
+++ b/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
@@ -2420,6 +2420,10 @@ static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void)
2420{ 2420{
2421 return 0x00502400U; 2421 return 0x00502400U;
2422} 2422}
2423static inline u32 gr_gpc0_gpccs_ctxsw_mailbox__size_1_v(void)
2424{
2425 return 0x00000010U;
2426}
2423static inline u32 gr_fecs_ctxsw_idlestate_r(void) 2427static inline u32 gr_fecs_ctxsw_idlestate_r(void)
2424{ 2428{
2425 return 0x00409420U; 2429 return 0x00409420U;
diff --git a/include/nvgpu/log.h b/include/nvgpu/log.h
index 70a1676..2bcca33 100644
--- a/include/nvgpu/log.h
+++ b/include/nvgpu/log.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"), 5 * copy of this software and associated documentation files (the "Software"),
@@ -80,6 +80,7 @@ void __nvgpu_log_dbg(struct gk20a *g, u64 log_mask,
80#define gpu_dbg_vidmem BIT(24) /* VIDMEM tracing. */ 80#define gpu_dbg_vidmem BIT(24) /* VIDMEM tracing. */
81#define gpu_dbg_nvlink BIT(25) /* nvlink Operation tracing. */ 81#define gpu_dbg_nvlink BIT(25) /* nvlink Operation tracing. */
82#define gpu_dbg_clk_arb BIT(26) /* Clk arbiter debugging. */ 82#define gpu_dbg_clk_arb BIT(26) /* Clk arbiter debugging. */
83#define gpu_dbg_ecc BIT(27) /* Print ECC Info Logs. */
83#define gpu_dbg_mem BIT(31) /* memory accesses; very verbose. */ 84#define gpu_dbg_mem BIT(31) /* memory accesses; very verbose. */
84 85
85/** 86/**
diff --git a/include/nvgpu/nvgpu_err.h b/include/nvgpu/nvgpu_err.h
new file mode 100644
index 0000000..0595faf
--- /dev/null
+++ b/include/nvgpu/nvgpu_err.h
@@ -0,0 +1,359 @@
1/*
2 * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef NVGPU_NVGPU_ERR_H
24#define NVGPU_NVGPU_ERR_H
25
26/**
27 * @file
28 *
29 * Define indices for HW units and errors. Define structures used to carry error
30 * information. Declare prototype for APIs that are used to report GPU HW errors
31 * to the Safety_Services framework.
32 */
33
34#include <nvgpu/types.h>
35#include <nvgpu/atomic.h>
36
37struct gk20a;
38
39/**
40 * @defgroup INDICES_FOR_GPU_HW_UNITS
41 * Macros used to assign unique index to GPU HW units.
42 * @{
43 */
44#define NVGPU_ERR_MODULE_SM (0U)
45#define NVGPU_ERR_MODULE_FECS (1U)
46#define NVGPU_ERR_MODULE_PMU (2U)
47/**
48 * @}
49 */
50
51/**
52 * @defgroup LIST_OF_ERRORS_REPORTED_FROM_SM
53 * Macros used to assign unique index to errors reported from the SM unit.
54 * @{
55 */
56#define GPU_SM_L1_TAG_ECC_CORRECTED (0U)
57#define GPU_SM_L1_TAG_ECC_UNCORRECTED (1U)
58#define GPU_SM_CBU_ECC_UNCORRECTED (3U)
59#define GPU_SM_LRF_ECC_UNCORRECTED (5U)
60#define GPU_SM_L1_DATA_ECC_UNCORRECTED (7U)
61#define GPU_SM_ICACHE_L0_DATA_ECC_UNCORRECTED (9U)
62#define GPU_SM_ICACHE_L1_DATA_ECC_UNCORRECTED (11U)
63#define GPU_SM_ICACHE_L0_PREDECODE_ECC_UNCORRECTED (13U)
64#define GPU_SM_L1_TAG_MISS_FIFO_ECC_UNCORRECTED (15U)
65#define GPU_SM_L1_TAG_S2R_PIXPRF_ECC_UNCORRECTED (17U)
66#define GPU_SM_ICACHE_L1_PREDECODE_ECC_UNCORRECTED (20U)
67/**
68 * @}
69 */
70
71/**
72 * @defgroup LIST_OF_ERRORS_REPORTED_FROM_FECS
73 * Macros used to assign unique index to errors reported from the FECS unit.
74 * @{
75 */
76#define GPU_FECS_FALCON_IMEM_ECC_CORRECTED (0U)
77#define GPU_FECS_FALCON_IMEM_ECC_UNCORRECTED (1U)
78#define GPU_FECS_FALCON_DMEM_ECC_UNCORRECTED (3U)
79/**
80 * @}
81 */
82
83/**
84 * @defgroup LIST_OF_ERRORS_REPORTED_FROM_GPCCS
85 * Macros used to assign unique index to errors reported from the GPCCS unit.
86 * @{
87 */
88#define GPU_GPCCS_FALCON_IMEM_ECC_CORRECTED (0U)
89#define GPU_GPCCS_FALCON_IMEM_ECC_UNCORRECTED (1U)
90#define GPU_GPCCS_FALCON_DMEM_ECC_UNCORRECTED (3U)
91/**
92 * @}
93 */
94
95/**
96 * @defgroup LIST_OF_ERRORS_REPORTED_FROM_MMU
97 * Macros used to assign unique index to errors reported from the MMU unit.
98 * @{
99 */
100#define GPU_MMU_L1TLB_SA_DATA_ECC_UNCORRECTED (1U)
101#define GPU_MMU_L1TLB_FA_DATA_ECC_UNCORRECTED (3U)
102/**
103 * @}
104 */
105
106/**
107 * @defgroup LIST_OF_ERRORS_REPORTED_FROM_GCC
108 * Macros used to assign unique index to errors reported from the GCC unit.
109 * @{
110 */
111#define GPU_GCC_L15_ECC_UNCORRECTED (1U)
112/**
113 * @}
114 */
115
116
117/**
118 * @defgroup LIST_OF_ERRORS_REPORTED_FROM_PMU
119 * Macros used to assign unique index to errors reported from the PMU unit.
120 * @{
121 */
122#define GPU_PMU_FALCON_IMEM_ECC_CORRECTED (0U)
123#define GPU_PMU_FALCON_IMEM_ECC_UNCORRECTED (1U)
124#define GPU_PMU_FALCON_DMEM_ECC_UNCORRECTED (3U)
125/**
126 * @}
127 */
128
129/**
130 * @defgroup LIST_OF_ERRORS_REPORTED_FROM_LTC
131 * Macros used to assign unique index to errors reported from the LTC unit.
132 * @{
133 */
134#define GPU_LTC_CACHE_DSTG_ECC_CORRECTED (0U)
135#define GPU_LTC_CACHE_DSTG_ECC_UNCORRECTED (1U)
136#define GPU_LTC_CACHE_TSTG_ECC_UNCORRECTED (3U)
137#define GPU_LTC_CACHE_DSTG_BE_ECC_UNCORRECTED (7U)
138/**
139 * @}
140 */
141
142/**
143 * @defgroup LIST_OF_ERRORS_REPORTED_FROM_HUBMMU
144 * Macros used to assign unique index to errors reported from the HUBMMU unit.
145 * @{
146 */
147#define GPU_HUBMMU_L2TLB_SA_DATA_ECC_UNCORRECTED (1U)
148#define GPU_HUBMMU_TLB_SA_DATA_ECC_UNCORRECTED (3U)
149#define GPU_HUBMMU_PTE_DATA_ECC_UNCORRECTED (5U)
150#define GPU_HUBMMU_PDE0_DATA_ECC_UNCORRECTED (7U)
151#define GPU_HUBMMU_PAGE_FAULT_ERROR (8U)
152
153
154#ifdef CONFIG_NVGPU_SUPPORT_LINUX_ECC_ERROR_REPORTING
155/**
156 * @}
157 */
158
159/**
160 * nvgpu_err_desc structure holds fields which describe an error along with
161 * function callback which can be used to inject the error.
162 */
163struct nvgpu_err_desc {
164 /** String representation of error. */
165 const char *name;
166
167 /** Flag to classify an error as critical or non-critical. */
168 bool is_critical;
169
170 /**
171 * Error Threshold: once this threshold value is reached, then the
172 * corresponding error counter will be reset to 0 and the error will be
173 * propagated to Safety_Services.
174 */
175 int err_threshold;
176
177 /**
178 * Total number of times an error has occurred (since its last reset).
179 */
180 nvgpu_atomic_t err_count;
181
182 /** Error ID. */
183 u8 error_id;
184};
185
186/**
187 * gpu_err_header structure holds fields which are required to identify the
188 * version of header, sub-error type, sub-unit id, error address and time stamp.
189 */
190struct gpu_err_header {
191 /** Version of GPU error header. */
192 struct {
193 /** Major version number. */
194 u16 major;
195 /** Minor version number. */
196 u16 minor;
197 } version;
198
199 /** Sub error type corresponding to the error that is being reported. */
200 u32 sub_err_type;
201
202 /** ID of the sub-unit in a HW unit which encountered an error. */
203 u64 sub_unit_id;
204
205 /** Location of the error. */
206 u64 address;
207
208 /** Timestamp in nano seconds. */
209 u64 timestamp_ns;
210};
211
212struct gpu_ecc_error_info {
213 struct gpu_err_header header;
214
215 /** Number of ECC errors. */
216 u64 err_cnt;
217};
218
219/**
220 * nvgpu_err_hw_module structure holds fields which describe the h/w modules
221 * error reporting capabilities.
222 */
223struct nvgpu_err_hw_module {
224 /** String representation of a given HW unit. */
225 const char *name;
226
227 /** HW unit ID. */
228 u32 hw_unit;
229
230 /** Total number of errors reported from a given HW unit. */
231 u32 num_errs;
232
233 u32 base_ecc_service_id;
234
235 /** Used to get error description from look-up table. */
236 struct nvgpu_err_desc *errs;
237};
238
239struct nvgpu_ecc_reporting_ops {
240 void (*report_ecc_err)(struct gk20a *g, u32 hw_unit, u32 inst,
241 u32 err_id, u64 err_addr, u64 err_count);
242};
243
244struct nvgpu_ecc_reporting {
245 struct nvgpu_spinlock lock;
246 /* This flag is protected by the above spinlock */
247 bool ecc_reporting_service_enabled;
248 const struct nvgpu_ecc_reporting_ops *ops;
249};
250
251 /**
252 * This macro is used to initialize the members of nvgpu_err_desc struct.
253 */
254#define GPU_ERR(err, critical, id, threshold, ecount) \
255{ \
256 .name = (err), \
257 .is_critical = (critical), \
258 .error_id = (id), \
259 .err_threshold = (threshold), \
260 .err_count = NVGPU_ATOMIC_INIT(ecount), \
261}
262
263/**
264 * This macro is used to initialize critical errors.
265 */
266#define GPU_CRITERR(err, id, threshold, ecount) \
267 GPU_ERR(err, true, id, threshold, ecount)
268
269/**
270 * This macro is used to initialize non-critical errors.
271 */
272#define GPU_NONCRITERR(err, id, threshold, ecount) \
273 GPU_ERR(err, false, id, threshold, ecount)
274
275/**
276 * @brief GPU HW errors need to be reported to Safety_Services via SDL unit.
277 * This function provides an interface to report ECC erros to SDL unit.
278 *
279 * @param g [in] - The GPU driver struct.
280 * @param hw_unit [in] - Index of HW unit.
281 * - List of valid HW unit IDs
282 * - NVGPU_ERR_MODULE_SM
283 * - NVGPU_ERR_MODULE_FECS
284 * - NVGPU_ERR_MODULE_GPCCS
285 * - NVGPU_ERR_MODULE_MMU
286 * - NVGPU_ERR_MODULE_GCC
287 * - NVGPU_ERR_MODULE_PMU
288 * - NVGPU_ERR_MODULE_LTC
289 * - NVGPU_ERR_MODULE_HUBMMU
290 * @param inst [in] - Instance ID.
291 * - In case of multiple instances of the same HW
292 * unit (e.g., there are multiple instances of
293 * SM), it is used to identify the instance
294 * that encountered a fault.
295 * @param err_id [in] - Error index.
296 * - For SM:
297 * - Min: GPU_SM_L1_TAG_ECC_CORRECTED
298 * - Max: GPU_SM_ICACHE_L1_PREDECODE_ECC_UNCORRECTED
299 * - For FECS:
300 * - Min: GPU_FECS_FALCON_IMEM_ECC_CORRECTED
301 * - Max: GPU_FECS_INVALID_ERROR
302 * - For GPCCS:
303 * - Min: GPU_GPCCS_FALCON_IMEM_ECC_CORRECTED
304 * - Max: GPU_GPCCS_FALCON_DMEM_ECC_UNCORRECTED
305 * - For MMU:
306 * - Min: GPU_MMU_L1TLB_SA_DATA_ECC_UNCORRECTED
307 * - Max: GPU_MMU_L1TLB_FA_DATA_ECC_UNCORRECTED
308 * - For GCC:
309 * - Min: GPU_GCC_L15_ECC_UNCORRECTED
310 * - Max: GPU_GCC_L15_ECC_UNCORRECTED
311 * - For PMU:
312 * - Min: GPU_PMU_FALCON_IMEM_ECC_CORRECTED
313 * - Max: GPU_PMU_FALCON_DMEM_ECC_UNCORRECTED
314 * - For LTC:
315 * - Min: GPU_LTC_CACHE_DSTG_ECC_CORRECTED
316 * - Max: GPU_LTC_CACHE_DSTG_BE_ECC_UNCORRECTED
317 * - For HUBMMU:
318 * - Min: GPU_HUBMMU_L2TLB_SA_DATA_ECC_UNCORRECTED
319 * - Max: GPU_HUBMMU_PDE0_DATA_ECC_UNCORRECTED
320 * @param err_addr [in] - Error address.
321 * - This is the location at which correctable or
322 * uncorrectable error has occurred.
323 * @param err_count [in] - Error count.
324 *
325 * - Checks whether SDL is supported in the current GPU platform. If SDL is not
326 * supported, it simply returns.
327 * - Validates both \a hw_unit and \a err_id indices. In case of a failure,
328 * invokes #nvgpu_sdl_handle_report_failure() api.
329 * - Gets the current time of a clock. In case of a failure, invokes
330 * #nvgpu_sdl_handle_report_failure() api.
331 * - Gets error description from internal look-up table using \a hw_unit and
332 * \a err_id indices.
333 * - Forms error packet using details such as time-stamp, \a hw_unit, \a err_id,
334 * criticality of the error, \a inst, \a err_addr, \a err_count, error
335 * description, and size of the error packet.
336 * - Performs compile-time assert check to ensure that the size of the error
337 * packet does not exceed the maximum allowable size specified in
338 * #MAX_ERR_MSG_SIZE.
339 *
340 * @return None
341 */
342void nvgpu_report_ecc_err(struct gk20a *g, u32 hw_unit, u32 inst,
343 u32 err_id, u64 err_addr, u64 err_count);
344
345void nvgpu_init_ecc_reporting(struct gk20a *g);
346void nvgpu_enable_ecc_reporting(struct gk20a *g);
347void nvgpu_disable_ecc_reporting(struct gk20a *g);
348void nvgpu_deinit_ecc_reporting(struct gk20a *g);
349
350#else
351
352static inline void nvgpu_report_ecc_err(struct gk20a *g, u32 hw_unit, u32 inst,
353 u32 err_id, u64 err_addr, u64 err_count) {
354
355}
356
357#endif /* CONFIG_NVGPU_SUPPORT_LINUX_ECC_ERROR_REPORTING */
358
359#endif /* NVGPU_NVGPU_ERR_H */ \ No newline at end of file
diff --git a/include/nvgpu/nvlink.h b/include/nvgpu/nvlink.h
index 26c83f1..a74111c 100644
--- a/include/nvgpu/nvlink.h
+++ b/include/nvgpu/nvlink.h
@@ -26,7 +26,7 @@
26#include <nvgpu/types.h> 26#include <nvgpu/types.h>
27 27
28#ifdef __KERNEL__ 28#ifdef __KERNEL__
29//#include <nvgpu/linux/nvlink.h> 29#include <nvgpu/linux/nvlink.h>
30#elif defined(__NVGPU_POSIX__) 30#elif defined(__NVGPU_POSIX__)
31#include <nvgpu/posix/nvlink.h> 31#include <nvgpu/posix/nvlink.h>
32#else 32#else
diff --git a/include/nvgpu/pmu.h b/include/nvgpu/pmu.h
index 2b745c7..fb1b016 100644
--- a/include/nvgpu/pmu.h
+++ b/include/nvgpu/pmu.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2017-2022, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"), 5 * copy of this software and associated documentation files (the "Software"),
@@ -94,6 +94,23 @@
94#define PMU_STATE_STARTED 7U /* Fully unitialized */ 94#define PMU_STATE_STARTED 7U /* Fully unitialized */
95#define PMU_STATE_EXIT 8U /* Exit PMU state machine */ 95#define PMU_STATE_EXIT 8U /* Exit PMU state machine */
96 96
97/* state transition :
98 * OFF => [OFF_ON_PENDING optional] => ON_PENDING => ON => OFF
99 * ON => OFF is always synchronized
100 */
101/* elpg is off */
102#define PMU_ELPG_STAT_OFF 0U
103/* elpg is on */
104#define PMU_ELPG_STAT_ON 1U
105/* elpg is off, ALLOW cmd has been sent, wait for ack */
106#define PMU_ELPG_STAT_ON_PENDING 2U
107/* elpg is on, DISALLOW cmd has been sent, wait for ack */
108#define PMU_ELPG_STAT_OFF_PENDING 3U
109/* elpg is off, caller has requested on, but ALLOW
110 * cmd hasn't been sent due to ENABLE_ALLOW delay
111 */
112#define PMU_ELPG_STAT_OFF_ON_PENDING 4U
113
97#define GK20A_PMU_UCODE_NB_MAX_OVERLAY 32U 114#define GK20A_PMU_UCODE_NB_MAX_OVERLAY 32U
98#define GK20A_PMU_UCODE_NB_MAX_DATE_LENGTH 64U 115#define GK20A_PMU_UCODE_NB_MAX_DATE_LENGTH 64U
99 116
@@ -351,6 +368,7 @@ struct nvgpu_pmu {
351 u32 stat_dmem_offset[PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE]; 368 u32 stat_dmem_offset[PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE];
352 369
353 u32 elpg_stat; 370 u32 elpg_stat;
371 u32 disallow_state;
354 372
355 u32 mscg_stat; 373 u32 mscg_stat;
356 u32 mscg_transition_state; 374 u32 mscg_transition_state;
diff --git a/include/nvgpu/pmuif/gpmuif_pg.h b/include/nvgpu/pmuif/gpmuif_pg.h
index 69a7ea4..58311ae 100644
--- a/include/nvgpu/pmuif/gpmuif_pg.h
+++ b/include/nvgpu/pmuif/gpmuif_pg.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2017-2022, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"), 5 * copy of this software and associated documentation files (the "Software"),
@@ -33,6 +33,11 @@
33#define PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE (0x00000005U) 33#define PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE (0x00000005U)
34#define PMU_PG_ELPG_ENGINE_MAX PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE 34#define PMU_PG_ELPG_ENGINE_MAX PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE
35 35
36/* Async PG message IDs */
37enum {
38 PMU_PG_MSG_ASYNC_CMD_DISALLOW,
39};
40
36/* PG message */ 41/* PG message */
37enum { 42enum {
38 PMU_PG_ELPG_MSG_INIT_ACK, 43 PMU_PG_ELPG_MSG_INIT_ACK,
@@ -73,12 +78,19 @@ struct pmu_pg_msg_eng_buf_stat {
73 u8 status; 78 u8 status;
74}; 79};
75 80
81struct pmu_pg_msg_async_cmd_resp {
82 u8 msg_type;
83 u8 ctrl_id;
84 u8 msg_id;
85};
86
76struct pmu_pg_msg { 87struct pmu_pg_msg {
77 union { 88 union {
78 u8 msg_type; 89 u8 msg_type;
79 struct pmu_pg_msg_elpg_msg elpg_msg; 90 struct pmu_pg_msg_elpg_msg elpg_msg;
80 struct pmu_pg_msg_stat stat; 91 struct pmu_pg_msg_stat stat;
81 struct pmu_pg_msg_eng_buf_stat eng_buf_stat; 92 struct pmu_pg_msg_eng_buf_stat eng_buf_stat;
93 struct pmu_pg_msg_async_cmd_resp async_cmd_resp;
82 /* TBD: other pg messages */ 94 /* TBD: other pg messages */
83 union pmu_ap_msg ap_msg; 95 union pmu_ap_msg ap_msg;
84 struct nv_pmu_rppg_msg rppg_msg; 96 struct nv_pmu_rppg_msg rppg_msg;
diff --git a/include/nvgpu/tsg.h b/include/nvgpu/tsg.h
index 7cd97c9..f5391e7 100644
--- a/include/nvgpu/tsg.h
+++ b/include/nvgpu/tsg.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2014-2021, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"), 5 * copy of this software and associated documentation files (the "Software"),
@@ -90,7 +90,7 @@ int gk20a_enable_tsg(struct tsg_gk20a *tsg);
90int gk20a_disable_tsg(struct tsg_gk20a *tsg); 90int gk20a_disable_tsg(struct tsg_gk20a *tsg);
91int gk20a_tsg_bind_channel(struct tsg_gk20a *tsg, 91int gk20a_tsg_bind_channel(struct tsg_gk20a *tsg,
92 struct channel_gk20a *ch); 92 struct channel_gk20a *ch);
93int gk20a_tsg_unbind_channel(struct channel_gk20a *ch); 93int gk20a_tsg_unbind_channel(struct channel_gk20a *ch, bool force);
94 94
95void gk20a_tsg_event_id_post_event(struct tsg_gk20a *tsg, 95void gk20a_tsg_event_id_post_event(struct tsg_gk20a *tsg,
96 int event_id); 96 int event_id);
diff --git a/include/os/linux/debug.c b/include/os/linux/debug.c
index 5f0703c..b8c4596 100644
--- a/include/os/linux/debug.c
+++ b/include/os/linux/debug.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) 2017-2018 NVIDIA Corporation. All rights reserved. 2 * Copyright (C) 2017-2021 NVIDIA Corporation. All rights reserved.
3 * 3 *
4 * This software is licensed under the terms of the GNU General Public 4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and 5 * License version 2, as published by the Free Software Foundation, and
@@ -224,7 +224,7 @@ static int railgate_residency_show(struct seq_file *s, void *data)
224 unsigned long total_rail_gate_time_ms; 224 unsigned long total_rail_gate_time_ms;
225 unsigned long total_rail_ungate_time_ms; 225 unsigned long total_rail_ungate_time_ms;
226 226
227 if (platform->is_railgated(dev_from_gk20a(g))) { 227 if (platform && platform->is_railgated && platform->is_railgated(dev_from_gk20a(g))) {
228 time_since_last_state_transition_ms = 228 time_since_last_state_transition_ms =
229 jiffies_to_msecs(jiffies - 229 jiffies_to_msecs(jiffies -
230 g->pstats.last_rail_gate_complete); 230 g->pstats.last_rail_gate_complete);
diff --git a/include/os/linux/driver_common.c b/include/os/linux/driver_common.c
index c76dabe..8f5872d 100644
--- a/include/os/linux/driver_common.c
+++ b/include/os/linux/driver_common.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify it 4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License, 5 * under the terms and conditions of the GNU General Public License,
@@ -18,6 +18,7 @@
18#include <linux/dma-mapping.h> 18#include <linux/dma-mapping.h>
19#include <linux/mm.h> 19#include <linux/mm.h>
20#include <linux/slab.h> 20#include <linux/slab.h>
21#include <linux/of_platform.h>
21#include <uapi/linux/nvgpu.h> 22#include <uapi/linux/nvgpu.h>
22 23
23#include <nvgpu/defaults.h> 24#include <nvgpu/defaults.h>
@@ -241,6 +242,8 @@ int nvgpu_probe(struct gk20a *g,
241 struct device *dev = dev_from_gk20a(g); 242 struct device *dev = dev_from_gk20a(g);
242 struct gk20a_platform *platform = dev_get_drvdata(dev); 243 struct gk20a_platform *platform = dev_get_drvdata(dev);
243 int err = 0; 244 int err = 0;
245 struct device_node *np = dev->of_node;
246 bool disable_l3_alloc = false;
244 247
245 nvgpu_init_vars(g); 248 nvgpu_init_vars(g);
246 nvgpu_init_gr_vars(g); 249 nvgpu_init_gr_vars(g);
@@ -265,6 +268,12 @@ int nvgpu_probe(struct gk20a *g,
265 return err; 268 return err;
266 } 269 }
267 270
271 disable_l3_alloc = of_property_read_bool(np, "disable_l3_alloc");
272 if (disable_l3_alloc) {
273 nvgpu_log_info(g, "L3 alloc is disabled\n");
274 __nvgpu_set_enabled(g, NVGPU_DISABLE_L3_SUPPORT, true);
275 }
276
268 nvgpu_init_mm_vars(g); 277 nvgpu_init_mm_vars(g);
269 278
270 /* platform probe can defer do user init only if probe succeeds */ 279 /* platform probe can defer do user init only if probe succeeds */
@@ -312,30 +321,70 @@ static int cyclic_delta(int a, int b)
312} 321}
313 322
314/** 323/**
315 * nvgpu_wait_for_deferred_interrupts - Wait for interrupts to complete 324 * nvgpu_wait_for_stall_interrupts - Wait for the stalling interrupts to
325 * complete.
316 * 326 *
317 * @g - The GPU to wait on. 327 * @g - The GPU to wait on.
328 * @timeout - maximum time period to wait for.
318 * 329 *
319 * Waits until all interrupt handlers that have been scheduled to run have 330 * Waits until all stalling interrupt handlers that have been scheduled to run
320 * completed. 331 * have completed.
321 */ 332 */
322void nvgpu_wait_for_deferred_interrupts(struct gk20a *g) 333int nvgpu_wait_for_stall_interrupts(struct gk20a *g, u32 timeout)
323{ 334{
324 struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); 335 struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
325 int stall_irq_threshold = atomic_read(&l->hw_irq_stall_count); 336 int stall_irq_threshold = atomic_read(&l->hw_irq_stall_count);
326 int nonstall_irq_threshold = atomic_read(&l->hw_irq_nonstall_count);
327 337
328 /* wait until all stalling irqs are handled */ 338 /* wait until all stalling irqs are handled */
329 NVGPU_COND_WAIT(&l->sw_irq_stall_last_handled_wq, 339 return NVGPU_COND_WAIT(&l->sw_irq_stall_last_handled_wq,
330 cyclic_delta(stall_irq_threshold, 340 cyclic_delta(stall_irq_threshold,
331 atomic_read(&l->sw_irq_stall_last_handled)) 341 atomic_read(&l->sw_irq_stall_last_handled))
332 <= 0, 0); 342 <= 0, timeout);
343}
344
345/**
346 * nvgpu_wait_for_nonstall_interrupts - Wait for the nonstalling interrupts to
347 * complete.
348 *
349 * @g - The GPU to wait on.
350 * @timeout - maximum time period to wait for.
351 *
352 * Waits until all non-stalling interrupt handlers that have been scheduled to
353 * run have completed.
354 */
355int nvgpu_wait_for_nonstall_interrupts(struct gk20a *g, u32 timeout)
356{
357 struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
358 int nonstall_irq_threshold = atomic_read(&l->hw_irq_nonstall_count);
333 359
334 /* wait until all non-stalling irqs are handled */ 360 /* wait until all non-stalling irqs are handled */
335 NVGPU_COND_WAIT(&l->sw_irq_nonstall_last_handled_wq, 361 return NVGPU_COND_WAIT(&l->sw_irq_nonstall_last_handled_wq,
336 cyclic_delta(nonstall_irq_threshold, 362 cyclic_delta(nonstall_irq_threshold,
337 atomic_read(&l->sw_irq_nonstall_last_handled)) 363 atomic_read(&l->sw_irq_nonstall_last_handled))
338 <= 0, 0); 364 <= 0, timeout);
365}
366
367/**
368 * nvgpu_wait_for_deferred_interrupts - Wait for interrupts to complete
369 *
370 * @g - The GPU to wait on.
371 *
372 * Waits until all interrupt handlers that have been scheduled to run have
373 * completed.
374 */
375void nvgpu_wait_for_deferred_interrupts(struct gk20a *g)
376{
377 int ret;
378
379 ret = nvgpu_wait_for_stall_interrupts(g, 0U);
380 if (ret != 0) {
381 nvgpu_err(g, "wait for stall interrupts failed %d", ret);
382 }
383
384 ret = nvgpu_wait_for_nonstall_interrupts(g, 0U);
385 if (ret != 0) {
386 nvgpu_err(g, "wait for nonstall interrupts failed %d", ret);
387 }
339} 388}
340 389
341static void nvgpu_free_gk20a(struct gk20a *g) 390static void nvgpu_free_gk20a(struct gk20a *g)
diff --git a/include/os/linux/ecc_linux.h b/include/os/linux/ecc_linux.h
new file mode 100644
index 0000000..7e0f650
--- /dev/null
+++ b/include/os/linux/ecc_linux.h
@@ -0,0 +1,49 @@
1/*
2 *
3 * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24#ifndef NVGPU_OS_ECC_LINUX_H
25#define NVGPU_OS_ECC_LINUX_H
26
27#ifdef CONFIG_NVGPU_SUPPORT_LINUX_ECC_ERROR_REPORTING
28
29#include <linux/tegra_l1ss_kernel_interface.h>
30#include <linux/tegra_l1ss_ioctl.h>
31#include <linux/tegra_nv_guard_service_id.h>
32#include <linux/tegra_nv_guard_group_id.h>
33
34#include <nvgpu/nvgpu_err.h>
35
36struct nvgpu_ecc_reporting_linux {
37 struct nvgpu_ecc_reporting common;
38 client_param_t priv;
39};
40
41static inline struct nvgpu_ecc_reporting_linux *get_ecc_reporting_linux(
42 struct nvgpu_ecc_reporting *ecc_report)
43{
44 return container_of(ecc_report, struct nvgpu_ecc_reporting_linux, common);
45}
46
47#endif /* CONFIG_NVGPU_SUPPORT_LINUX_ECC_ERROR_REPORTING */
48
49#endif \ No newline at end of file
diff --git a/include/os/linux/ioctl_clk_arb.c b/include/os/linux/ioctl_clk_arb.c
index 477222d..9f32102 100644
--- a/include/os/linux/ioctl_clk_arb.c
+++ b/include/os/linux/ioctl_clk_arb.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2016-2021, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * This software is licensed under the terms of the GNU General Public 4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and 5 * License version 2, as published by the Free Software Foundation, and
@@ -51,19 +51,28 @@ static int nvgpu_clk_arb_release_completion_dev(struct inode *inode,
51{ 51{
52 struct nvgpu_clk_dev *dev = filp->private_data; 52 struct nvgpu_clk_dev *dev = filp->private_data;
53 struct nvgpu_clk_session *session = dev->session; 53 struct nvgpu_clk_session *session = dev->session;
54 struct gk20a *g = session->g;
55 struct nvgpu_clk_arb *arb = g->clk_arb;
54 56
57 clk_arb_dbg(g, " ");
55 58
56 clk_arb_dbg(session->g, " "); 59 nvgpu_spinlock_acquire(&session->session_lock);
60 nvgpu_spinlock_acquire(&arb->requests_lock);
61
62 nvgpu_list_del(&dev->node);
63
64 nvgpu_spinlock_release(&arb->requests_lock);
65 nvgpu_spinlock_release(&session->session_lock);
57 66
58 /* This is done to account for the extra refcount taken in 67 /* This is done to account for the extra refcount taken in
59 * nvgpu_clk_arb_commit_request_fd without events support in iGPU 68 * nvgpu_clk_arb_commit_request_fd without events support in iGPU
60 */ 69 */
61 if (!session->g->clk_arb->clk_arb_events_supported) { 70 if (!arb->clk_arb_events_supported) {
62 nvgpu_ref_put(&dev->refcount, nvgpu_clk_arb_free_fd); 71 nvgpu_ref_put(&dev->refcount, nvgpu_clk_arb_free_fd);
63 } 72 }
64 73
65 nvgpu_ref_put(&session->refcount, nvgpu_clk_arb_free_session);
66 nvgpu_ref_put(&dev->refcount, nvgpu_clk_arb_free_fd); 74 nvgpu_ref_put(&dev->refcount, nvgpu_clk_arb_free_fd);
75 nvgpu_ref_put(&session->refcount, nvgpu_clk_arb_free_session);
67 return 0; 76 return 0;
68} 77}
69 78
diff --git a/include/os/linux/ioctl_ctrl.c b/include/os/linux/ioctl_ctrl.c
index ee141ff..841d345 100644
--- a/include/os/linux/ioctl_ctrl.c
+++ b/include/os/linux/ioctl_ctrl.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2011-2020, NVIDIA Corporation. All rights reserved. 2 * Copyright (c) 2011-2021, NVIDIA Corporation. All rights reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify it 4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License, 5 * under the terms and conditions of the GNU General Public License,
@@ -60,7 +60,6 @@ struct gk20a_ctrl_priv {
60 struct nvgpu_list_node list; 60 struct nvgpu_list_node list;
61 struct { 61 struct {
62 struct vm_area_struct *vma; 62 struct vm_area_struct *vma;
63 unsigned long flags;
64 bool vma_mapped; 63 bool vma_mapped;
65 } usermode_vma; 64 } usermode_vma;
66}; 65};
@@ -488,27 +487,26 @@ static int gk20a_ctrl_alloc_as(
488 487
489 snprintf(name, sizeof(name), "nvhost-%s-fd%d", g->name, fd); 488 snprintf(name, sizeof(name), "nvhost-%s-fd%d", g->name, fd);
490 489
491 file = anon_inode_getfile(name, l->as_dev.cdev.ops, NULL, O_RDWR);
492 if (IS_ERR(file)) {
493 err = PTR_ERR(file);
494 goto clean_up;
495 }
496
497 err = gk20a_as_alloc_share(g, args->big_page_size, 490 err = gk20a_as_alloc_share(g, args->big_page_size,
498 gk20a_as_translate_as_alloc_flags(g, 491 gk20a_as_translate_as_alloc_flags(g,
499 args->flags), 492 args->flags),
500 &as_share); 493 &as_share);
501 if (err) 494 if (err)
502 goto clean_up_file; 495 goto clean_up;
496
497 file = anon_inode_getfile(name, l->as_dev.cdev.ops, as_share, O_RDWR);
498 if (IS_ERR(file)) {
499 err = PTR_ERR(file);
500 goto clean_up_as;
501 }
503 502
504 fd_install(fd, file); 503 fd_install(fd, file);
505 file->private_data = as_share;
506 504
507 args->as_fd = fd; 505 args->as_fd = fd;
508 return 0; 506 return 0;
509 507
510clean_up_file: 508clean_up_as:
511 fput(file); 509 gk20a_as_release_share(as_share);
512clean_up: 510clean_up:
513 put_unused_fd(fd); 511 put_unused_fd(fd);
514 return err; 512 return err;
@@ -692,12 +690,15 @@ static int nvgpu_gpu_ioctl_trigger_suspend(struct gk20a *g)
692 690
693 err = gk20a_busy(g); 691 err = gk20a_busy(g);
694 if (err) 692 if (err)
695 return err; 693 return err;
696 694
697 nvgpu_mutex_acquire(&g->dbg_sessions_lock); 695 if (g->ops.gr.trigger_suspend) {
698 err = gr_gk20a_elpg_protected_call(g, 696 nvgpu_mutex_acquire(&g->dbg_sessions_lock);
697 err = gr_gk20a_elpg_protected_call(g,
699 g->ops.gr.trigger_suspend(g)); 698 g->ops.gr.trigger_suspend(g));
700 nvgpu_mutex_release(&g->dbg_sessions_lock); 699 nvgpu_mutex_release(&g->dbg_sessions_lock);
700 } else
701 err = -EINVAL;
701 702
702 gk20a_idle(g); 703 gk20a_idle(g);
703 704
@@ -731,8 +732,13 @@ static int nvgpu_gpu_ioctl_wait_for_pause(struct gk20a *g,
731 goto out_free; 732 goto out_free;
732 733
733 nvgpu_mutex_acquire(&g->dbg_sessions_lock); 734 nvgpu_mutex_acquire(&g->dbg_sessions_lock);
734 (void)gr_gk20a_elpg_protected_call(g, 735 if (g->ops.gr.wait_for_pause) {
736 (void)gr_gk20a_elpg_protected_call(g,
735 g->ops.gr.wait_for_pause(g, w_state)); 737 g->ops.gr.wait_for_pause(g, w_state));
738 } else {
739 err = -EINVAL;
740 goto out_idle;
741 }
736 742
737 for (sm_id = 0; sm_id < g->gr.no_of_sm; sm_id++) { 743 for (sm_id = 0; sm_id < g->gr.no_of_sm; sm_id++) {
738 ioctl_w_state[sm_id].valid_warps[0] = 744 ioctl_w_state[sm_id].valid_warps[0] =
@@ -755,6 +761,7 @@ static int nvgpu_gpu_ioctl_wait_for_pause(struct gk20a *g,
755 err = -EFAULT; 761 err = -EFAULT;
756 } 762 }
757 763
764out_idle:
758 nvgpu_mutex_release(&g->dbg_sessions_lock); 765 nvgpu_mutex_release(&g->dbg_sessions_lock);
759 766
760 gk20a_idle(g); 767 gk20a_idle(g);
@@ -772,12 +779,15 @@ static int nvgpu_gpu_ioctl_resume_from_pause(struct gk20a *g)
772 779
773 err = gk20a_busy(g); 780 err = gk20a_busy(g);
774 if (err) 781 if (err)
775 return err; 782 return err;
776 783
777 nvgpu_mutex_acquire(&g->dbg_sessions_lock); 784 if (g->ops.gr.resume_from_pause) {
778 err = gr_gk20a_elpg_protected_call(g, 785 nvgpu_mutex_acquire(&g->dbg_sessions_lock);
786 err = gr_gk20a_elpg_protected_call(g,
779 g->ops.gr.resume_from_pause(g)); 787 g->ops.gr.resume_from_pause(g));
780 nvgpu_mutex_release(&g->dbg_sessions_lock); 788 nvgpu_mutex_release(&g->dbg_sessions_lock);
789 } else
790 err = -EINVAL;
781 791
782 gk20a_idle(g); 792 gk20a_idle(g);
783 793
@@ -792,8 +802,11 @@ static int nvgpu_gpu_ioctl_clear_sm_errors(struct gk20a *g)
792 if (err) 802 if (err)
793 return err; 803 return err;
794 804
795 err = gr_gk20a_elpg_protected_call(g, 805 if (g->ops.gr.clear_sm_errors) {
806 err = gr_gk20a_elpg_protected_call(g,
796 g->ops.gr.clear_sm_errors(g)); 807 g->ops.gr.clear_sm_errors(g));
808 } else
809 err = -EINVAL;
797 810
798 gk20a_idle(g); 811 gk20a_idle(g);
799 812
@@ -806,9 +819,12 @@ static int nvgpu_gpu_ioctl_has_any_exception(
806{ 819{
807 u32 tpc_exception_en; 820 u32 tpc_exception_en;
808 821
809 nvgpu_mutex_acquire(&g->dbg_sessions_lock); 822 if (g->ops.gr.tpc_enabled_exceptions) {
810 tpc_exception_en = g->ops.gr.tpc_enabled_exceptions(g); 823 nvgpu_mutex_acquire(&g->dbg_sessions_lock);
811 nvgpu_mutex_release(&g->dbg_sessions_lock); 824 tpc_exception_en = g->ops.gr.tpc_enabled_exceptions(g);
825 nvgpu_mutex_release(&g->dbg_sessions_lock);
826 } else
827 return -EINVAL;
812 828
813 args->tpc_exception_en_sm_mask = tpc_exception_en; 829 args->tpc_exception_en_sm_mask = tpc_exception_en;
814 830
@@ -2023,7 +2039,6 @@ int gk20a_ctrl_dev_mmap(struct file *filp, struct vm_area_struct *vma)
2023 vma->vm_end - vma->vm_start, vma->vm_page_prot); 2039 vma->vm_end - vma->vm_start, vma->vm_page_prot);
2024 if (!err) { 2040 if (!err) {
2025 priv->usermode_vma.vma = vma; 2041 priv->usermode_vma.vma = vma;
2026 priv->usermode_vma.flags = vma->vm_flags;
2027 vma->vm_private_data = priv; 2042 vma->vm_private_data = priv;
2028 priv->usermode_vma.vma_mapped = true; 2043 priv->usermode_vma.vma_mapped = true;
2029 } 2044 }
@@ -2034,7 +2049,7 @@ int gk20a_ctrl_dev_mmap(struct file *filp, struct vm_area_struct *vma)
2034 return err; 2049 return err;
2035} 2050}
2036 2051
2037static void alter_usermode_mapping(struct gk20a *g, 2052static int alter_usermode_mapping(struct gk20a *g,
2038 struct gk20a_ctrl_priv *priv, 2053 struct gk20a_ctrl_priv *priv,
2039 bool poweroff) 2054 bool poweroff)
2040{ 2055{
@@ -2042,57 +2057,80 @@ static void alter_usermode_mapping(struct gk20a *g,
2042 struct vm_area_struct *vma = priv->usermode_vma.vma; 2057 struct vm_area_struct *vma = priv->usermode_vma.vma;
2043 bool vma_mapped = priv->usermode_vma.vma_mapped; 2058 bool vma_mapped = priv->usermode_vma.vma_mapped;
2044 u64 addr; 2059 u64 addr;
2045 int err; 2060 int err = 0;
2046 2061
2047 if (!vma) { 2062 if (!vma) {
2048 /* Nothing to do - no mmap called */ 2063 /* Nothing to do - no mmap called */
2049 return; 2064 return 0;
2050 } 2065 }
2051 2066
2052 addr = l->regs_bus_addr + g->ops.fifo.usermode_base(g); 2067 addr = l->regs_bus_addr + g->ops.fifo.usermode_base(g);
2053 2068
2054 down_write(&vma->vm_mm->mmap_sem);
2055
2056 /* 2069 /*
2057 * This is a no-op for the below cases 2070 * This is a no-op for the below cases
2058 * a) poweroff and !vma_mapped - > do nothing as no map exists 2071 * a) poweroff and !vma_mapped - > do nothing as no map exists
2059 * b) !poweroff and vmap_mapped -> do nothing as already mapped 2072 * b) !poweroff and vmap_mapped -> do nothing as already mapped
2060 */ 2073 */
2061 if (poweroff && vma_mapped) { 2074 if (poweroff != vma_mapped) {
2075 return 0;
2076 }
2077
2078 /*
2079 * We use trylock due to lock inversion: we need to acquire
2080 * mmap_lock while holding ctrl_privs_lock. usermode_vma_close
2081 * does it in reverse order. Trylock is a way to avoid deadlock.
2082 */
2083 if (!down_write_trylock(&vma->vm_mm->mmap_sem)) {
2084 return -EBUSY;
2085 }
2086
2087 if (poweroff) {
2062 err = zap_vma_ptes(vma, vma->vm_start, SZ_4K); 2088 err = zap_vma_ptes(vma, vma->vm_start, SZ_4K);
2063 if (err == 0) { 2089 if (err == 0) {
2064 vma->vm_flags = VM_NONE;
2065 priv->usermode_vma.vma_mapped = false; 2090 priv->usermode_vma.vma_mapped = false;
2066 } else { 2091 } else {
2067 nvgpu_err(g, "can't remove usermode mapping"); 2092 nvgpu_err(g, "can't remove usermode mapping");
2068 } 2093 }
2069 } else if (!poweroff && !vma_mapped) { 2094 } else {
2070 vma->vm_flags = priv->usermode_vma.flags;
2071 err = io_remap_pfn_range(vma, vma->vm_start, 2095 err = io_remap_pfn_range(vma, vma->vm_start,
2072 addr >> PAGE_SHIFT, 2096 addr >> PAGE_SHIFT,
2073 SZ_4K, vma->vm_page_prot); 2097 SZ_4K, vma->vm_page_prot);
2074 if (err != 0) { 2098 if (err != 0) {
2075 nvgpu_err(g, "can't restore usermode mapping"); 2099 nvgpu_err(g, "can't restore usermode mapping");
2076 vma->vm_flags = VM_NONE;
2077 } else { 2100 } else {
2078 priv->usermode_vma.vma_mapped = true; 2101 priv->usermode_vma.vma_mapped = true;
2079 } 2102 }
2080 } 2103 }
2081 2104
2082 up_write(&vma->vm_mm->mmap_sem); 2105 up_write(&vma->vm_mm->mmap_sem);
2106
2107 return err;
2083} 2108}
2084 2109
2085static void alter_usermode_mappings(struct gk20a *g, bool poweroff) 2110static void alter_usermode_mappings(struct gk20a *g, bool poweroff)
2086{ 2111{
2087 struct gk20a_ctrl_priv *priv; 2112 struct gk20a_ctrl_priv *priv;
2088 struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); 2113 struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
2114 int err = 0;
2089 2115
2090 nvgpu_mutex_acquire(&l->ctrl.privs_lock); 2116 do {
2091 nvgpu_list_for_each_entry(priv, &l->ctrl.privs, 2117 nvgpu_mutex_acquire(&l->ctrl.privs_lock);
2092 gk20a_ctrl_priv, list) { 2118 nvgpu_list_for_each_entry(priv, &l->ctrl.privs,
2093 alter_usermode_mapping(g, priv, poweroff); 2119 gk20a_ctrl_priv, list) {
2094 } 2120 err = alter_usermode_mapping(g, priv, poweroff);
2095 nvgpu_mutex_release(&l->ctrl.privs_lock); 2121 if (err != 0) {
2122 break;
2123 }
2124 }
2125 nvgpu_mutex_release(&l->ctrl.privs_lock);
2126
2127 if (err == -EBUSY) {
2128 nvgpu_log_info(g, "ctrl_privs_lock lock contended. retry altering usermode mappings");
2129 nvgpu_udelay(10);
2130 } else if (err != 0) {
2131 nvgpu_err(g, "can't alter usermode mapping. err = %d", err);
2132 }
2133 } while (err == -EBUSY);
2096} 2134}
2097 2135
2098void nvgpu_hide_usermode_for_poweroff(struct gk20a *g) 2136void nvgpu_hide_usermode_for_poweroff(struct gk20a *g)
diff --git a/include/os/linux/ioctl_tsg.c b/include/os/linux/ioctl_tsg.c
index 2f8cb3a..296b02b 100644
--- a/include/os/linux/ioctl_tsg.c
+++ b/include/os/linux/ioctl_tsg.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2014-2021, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify it 4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License, 5 * under the terms and conditions of the GNU General Public License,
@@ -134,7 +134,10 @@ static int gk20a_tsg_unbind_channel_fd(struct tsg_gk20a *tsg, int ch_fd)
134 goto out; 134 goto out;
135 } 135 }
136 136
137 err = gk20a_tsg_unbind_channel(ch); 137 err = gk20a_tsg_unbind_channel(ch, false);
138 if (err == -EAGAIN) {
139 goto out;
140 }
138 141
139 /* 142 /*
140 * Mark the channel timedout since channel unbound from TSG 143 * Mark the channel timedout since channel unbound from TSG
@@ -307,17 +310,10 @@ static int gk20a_tsg_event_id_enable(struct tsg_gk20a *tsg,
307 snprintf(name, sizeof(name), "nvgpu-event%d-fd%d", 310 snprintf(name, sizeof(name), "nvgpu-event%d-fd%d",
308 event_id, local_fd); 311 event_id, local_fd);
309 312
310 file = anon_inode_getfile(name, &gk20a_event_id_ops,
311 NULL, O_RDWR);
312 if (IS_ERR(file)) {
313 err = PTR_ERR(file);
314 goto clean_up;
315 }
316
317 event_id_data = nvgpu_kzalloc(tsg->g, sizeof(*event_id_data)); 313 event_id_data = nvgpu_kzalloc(tsg->g, sizeof(*event_id_data));
318 if (!event_id_data) { 314 if (!event_id_data) {
319 err = -ENOMEM; 315 err = -ENOMEM;
320 goto clean_up_file; 316 goto clean_up;
321 } 317 }
322 event_id_data->g = g; 318 event_id_data->g = g;
323 event_id_data->id = tsg->tsgid; 319 event_id_data->id = tsg->tsgid;
@@ -330,12 +326,18 @@ static int gk20a_tsg_event_id_enable(struct tsg_gk20a *tsg,
330 326
331 nvgpu_init_list_node(&event_id_data->event_id_node); 327 nvgpu_init_list_node(&event_id_data->event_id_node);
332 328
329 file = anon_inode_getfile(name, &gk20a_event_id_ops,
330 event_id_data, O_RDWR);
331 if (IS_ERR(file)) {
332 err = PTR_ERR(file);
333 goto clean_up_free;
334 }
335
333 nvgpu_mutex_acquire(&tsg->event_id_list_lock); 336 nvgpu_mutex_acquire(&tsg->event_id_list_lock);
334 nvgpu_list_add_tail(&event_id_data->event_id_node, &tsg->event_id_list); 337 nvgpu_list_add_tail(&event_id_data->event_id_node, &tsg->event_id_list);
335 nvgpu_mutex_release(&tsg->event_id_list_lock); 338 nvgpu_mutex_release(&tsg->event_id_list_lock);
336 339
337 fd_install(local_fd, file); 340 fd_install(local_fd, file);
338 file->private_data = event_id_data;
339 341
340 *fd = local_fd; 342 *fd = local_fd;
341 343
@@ -343,8 +345,6 @@ static int gk20a_tsg_event_id_enable(struct tsg_gk20a *tsg,
343 345
344clean_up_free: 346clean_up_free:
345 nvgpu_kfree(g, event_id_data); 347 nvgpu_kfree(g, event_id_data);
346clean_up_file:
347 fput(file);
348clean_up: 348clean_up:
349 put_unused_fd(local_fd); 349 put_unused_fd(local_fd);
350free_ref: 350free_ref:
diff --git a/include/os/linux/module.c b/include/os/linux/module.c
index 807df2c..fdbab46 100644
--- a/include/os/linux/module.c
+++ b/include/os/linux/module.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * GK20A Graphics 2 * GK20A Graphics
3 * 3 *
4 * Copyright (c) 2011-2020, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2011-2021, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License, 7 * under the terms and conditions of the GNU General Public License,
@@ -49,6 +49,7 @@
49#include <nvgpu/clk_arb.h> 49#include <nvgpu/clk_arb.h>
50#include <nvgpu/timers.h> 50#include <nvgpu/timers.h>
51#include <nvgpu/channel.h> 51#include <nvgpu/channel.h>
52#include <nvgpu/nvgpu_err.h>
52 53
53#include "platform_gk20a.h" 54#include "platform_gk20a.h"
54#include "sysfs.h" 55#include "sysfs.h"
@@ -355,6 +356,10 @@ int gk20a_pm_finalize_poweron(struct device *dev)
355 gk20a_init_cde_support(l); 356 gk20a_init_cde_support(l);
356#endif 357#endif
357 358
359#ifdef CONFIG_NVGPU_SUPPORT_LINUX_ECC_ERROR_REPORTING
360 nvgpu_enable_ecc_reporting(g);
361#endif
362
358 err = gk20a_sched_ctrl_init(g); 363 err = gk20a_sched_ctrl_init(g);
359 if (err) { 364 if (err) {
360 nvgpu_err(g, "failed to init sched control"); 365 nvgpu_err(g, "failed to init sched control");
@@ -364,9 +369,14 @@ int gk20a_pm_finalize_poweron(struct device *dev)
364 g->sw_ready = true; 369 g->sw_ready = true;
365 370
366done: 371done:
367 if (err) 372 if (err) {
368 g->power_on = false; 373 g->power_on = false;
369 374
375#ifdef CONFIG_NVGPU_SUPPORT_LINUX_ECC_ERROR_REPORTING
376 nvgpu_disable_ecc_reporting(g);
377#endif
378 }
379
370 nvgpu_mutex_release(&g->power_lock); 380 nvgpu_mutex_release(&g->power_lock);
371 return err; 381 return err;
372} 382}
@@ -433,6 +443,10 @@ static int gk20a_pm_prepare_poweroff(struct device *dev)
433 /* Stop CPU from accessing the GPU registers. */ 443 /* Stop CPU from accessing the GPU registers. */
434 gk20a_lockout_registers(g); 444 gk20a_lockout_registers(g);
435 445
446#ifdef CONFIG_NVGPU_SUPPORT_LINUX_ECC_ERROR_REPORTING
447 nvgpu_disable_ecc_reporting(g);
448#endif
449
436 nvgpu_hide_usermode_for_poweroff(g); 450 nvgpu_hide_usermode_for_poweroff(g);
437 nvgpu_mutex_release(&g->power_lock); 451 nvgpu_mutex_release(&g->power_lock);
438 return 0; 452 return 0;
@@ -1382,6 +1396,10 @@ static int gk20a_probe(struct platform_device *dev)
1382 goto return_err; 1396 goto return_err;
1383 } 1397 }
1384 1398
1399#ifdef CONFIG_NVGPU_SUPPORT_LINUX_ECC_ERROR_REPORTING
1400 nvgpu_init_ecc_reporting(gk20a);
1401#endif
1402
1385 gk20a->nvgpu_reboot_nb.notifier_call = 1403 gk20a->nvgpu_reboot_nb.notifier_call =
1386 nvgpu_kernel_shutdown_notification; 1404 nvgpu_kernel_shutdown_notification;
1387 err = register_reboot_notifier(&gk20a->nvgpu_reboot_nb); 1405 err = register_reboot_notifier(&gk20a->nvgpu_reboot_nb);
diff --git a/include/os/linux/os_linux.h b/include/os/linux/os_linux.h
index 25c6c03..adcfdb2 100644
--- a/include/os/linux/os_linux.h
+++ b/include/os/linux/os_linux.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify it 4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License, 5 * under the terms and conditions of the GNU General Public License,
@@ -25,6 +25,7 @@
25 25
26#include "cde.h" 26#include "cde.h"
27#include "sched.h" 27#include "sched.h"
28#include "ecc_linux.h"
28 29
29struct nvgpu_os_linux_ops { 30struct nvgpu_os_linux_ops {
30 struct { 31 struct {
@@ -134,6 +135,10 @@ struct nvgpu_os_linux {
134 135
135 u64 regs_bus_addr; 136 u64 regs_bus_addr;
136 137
138#ifdef CONFIG_NVGPU_SUPPORT_LINUX_ECC_ERROR_REPORTING
139 struct nvgpu_ecc_reporting_linux ecc_reporting_linux;
140#endif
141
137 struct nvgpu_os_linux_ops ops; 142 struct nvgpu_os_linux_ops ops;
138 143
139#ifdef CONFIG_DEBUG_FS 144#ifdef CONFIG_DEBUG_FS
diff --git a/include/os/linux/platform_gv11b_tegra.c b/include/os/linux/platform_gv11b_tegra.c
index 6c9d0f5..7900eaa 100644
--- a/include/os/linux/platform_gv11b_tegra.c
+++ b/include/os/linux/platform_gv11b_tegra.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * GV11B Tegra Platform Interface 2 * GV11B Tegra Platform Interface
3 * 3 *
4 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License, 7 * under the terms and conditions of the GNU General Public License,
@@ -322,7 +322,7 @@ struct gk20a_platform gv11b_tegra_platform = {
322 322
323 .honors_aperture = true, 323 .honors_aperture = true,
324 .unified_memory = true, 324 .unified_memory = true,
325 .dma_mask = DMA_BIT_MASK(36), 325 .dma_mask = DMA_BIT_MASK(38),
326 326
327 .reset_assert = gp10b_tegra_reset_assert, 327 .reset_assert = gp10b_tegra_reset_assert,
328 .reset_deassert = gp10b_tegra_reset_deassert, 328 .reset_deassert = gp10b_tegra_reset_deassert,
diff --git a/include/os/linux/scale.c b/include/os/linux/scale.c
index 388e168..f8f0ef9 100644
--- a/include/os/linux/scale.c
+++ b/include/os/linux/scale.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * gk20a clock scaling profile 2 * gk20a clock scaling profile
3 * 3 *
4 * Copyright (c) 2013-2020, NVIDIA Corporation. All rights reserved. 4 * Copyright (c) 2013-2023, NVIDIA Corporation. All rights reserved.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License, 7 * under the terms and conditions of the GNU General Public License,
@@ -148,32 +148,24 @@ static int gk20a_scale_target(struct device *dev, unsigned long *freq,
148{ 148{
149 struct gk20a_platform *platform = dev_get_drvdata(dev); 149 struct gk20a_platform *platform = dev_get_drvdata(dev);
150 struct gk20a *g = platform->g; 150 struct gk20a *g = platform->g;
151 struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
152 struct gk20a_scale_profile *profile = g->scale_profile; 151 struct gk20a_scale_profile *profile = g->scale_profile;
153 struct devfreq *devfreq = l->devfreq;
154 unsigned long local_freq = *freq; 152 unsigned long local_freq = *freq;
155 unsigned long rounded_rate; 153 unsigned long rounded_rate;
154#ifdef CONFIG_GK20A_PM_QOS
156 unsigned long min_freq = 0, max_freq = 0; 155 unsigned long min_freq = 0, max_freq = 0;
156#endif
157 157
158 if (nvgpu_clk_arb_has_active_req(g)) 158 if (nvgpu_clk_arb_has_active_req(g))
159 return 0; 159 return 0;
160
161#ifdef CONFIG_GK20A_PM_QOS
160 /* 162 /*
161 * Calculate floor and cap frequency values 163 * devfreq takes care of min/max freq clipping in update_devfreq() then
162 * 164 * invoked devfreq->profile->target(), thus we only need to do freq
163 * Policy : 165 * clipping based on pm_qos constraint
164 * We have two APIs to clip the frequency
165 * 1. devfreq
166 * 2. pm_qos
167 *
168 * To calculate floor (min) freq, we select MAX of floor frequencies
169 * requested from both APIs
170 * To get cap (max) freq, we select MIN of max frequencies
171 *
172 * In case we have conflict (min_freq > max_freq) after above
173 * steps, we ensure that max_freq wins over min_freq
174 */ 166 */
175 min_freq = max_t(u32, devfreq->min_freq, profile->qos_min_freq); 167 min_freq = profile->qos_min_freq;
176 max_freq = min_t(u32, devfreq->max_freq, profile->qos_max_freq); 168 max_freq = profile->qos_max_freq;
177 169
178 if (min_freq > max_freq) 170 if (min_freq > max_freq)
179 min_freq = max_freq; 171 min_freq = max_freq;
@@ -184,6 +176,7 @@ static int gk20a_scale_target(struct device *dev, unsigned long *freq,
184 176
185 if (local_freq > max_freq) 177 if (local_freq > max_freq)
186 local_freq = max_freq; 178 local_freq = max_freq;
179#endif
187 180
188 /* set the final frequency */ 181 /* set the final frequency */
189 rounded_rate = platform->clk_round_rate(dev, local_freq); 182 rounded_rate = platform->clk_round_rate(dev, local_freq);
diff --git a/include/os/linux/sdl.c b/include/os/linux/sdl.c
new file mode 100644
index 0000000..c4dccdc
--- /dev/null
+++ b/include/os/linux/sdl.c
@@ -0,0 +1,341 @@
1/*
2 * Copyright (c) 2021, NVIDIA Corporation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <nvgpu/gk20a.h>
18#include <nvgpu/types.h>
19#include <nvgpu/nvgpu_err.h>
20#include <nvgpu/timers.h>
21#include <nvgpu/bug.h>
22
23#include "ecc_linux.h"
24#include "os_linux.h"
25#include "module.h"
26
27/* This look-up table initializes the list of hw units and their errors.
28 * It also specifies the error injection mechanism supported, for each error.
29 * In case of hw error injection support, this initialization will be overriden
30 * by the values provided from the hal layes of corresponding hw units.
31 */
32static struct nvgpu_err_hw_module gv11b_err_lut[] = {
33 {
34 .name = "sm",
35 .hw_unit = (u32)NVGPU_ERR_MODULE_SM,
36 .num_errs = 21U,
37 .base_ecc_service_id =
38 NVGUARD_SERVICE_IGPU_SM_SWERR_L1_TAG_ECC_CORRECTED,
39 .errs = (struct nvgpu_err_desc[]) {
40 GPU_NONCRITERR("l1_tag_ecc_corrected",
41 GPU_SM_L1_TAG_ECC_CORRECTED, 0, 0),
42 GPU_CRITERR("l1_tag_ecc_uncorrected",
43 GPU_SM_L1_TAG_ECC_UNCORRECTED, 0, 0),
44 GPU_NONCRITERR("cbu_ecc_corrected", 0, 0, 0),
45 GPU_CRITERR("cbu_ecc_uncorrected",
46 GPU_SM_CBU_ECC_UNCORRECTED, 0, 0),
47 GPU_NONCRITERR("lrf_ecc_corrected", 0, 0, 0),
48 GPU_CRITERR("lrf_ecc_uncorrected",
49 GPU_SM_LRF_ECC_UNCORRECTED, 0, 0),
50 GPU_NONCRITERR("l1_data_ecc_corrected", 0, 0, 0),
51 GPU_CRITERR("l1_data_ecc_uncorrected",
52 GPU_SM_L1_DATA_ECC_UNCORRECTED, 0, 0),
53 GPU_NONCRITERR("icache_l0_data_ecc_corrected", 0, 0, 0),
54 GPU_CRITERR("icache_l0_data_ecc_uncorrected",
55 GPU_SM_ICACHE_L0_DATA_ECC_UNCORRECTED, 0, 0),
56 GPU_NONCRITERR("icache_l1_data_ecc_corrected", 0, 0, 0),
57 GPU_CRITERR("icache_l1_data_ecc_uncorrected",
58 GPU_SM_ICACHE_L1_DATA_ECC_UNCORRECTED, 0, 0),
59 GPU_NONCRITERR("icache_l0_predecode_ecc_corrected", 0, 0, 0),
60 GPU_CRITERR("icache_l0_predecode_ecc_uncorrected",
61 GPU_SM_ICACHE_L0_PREDECODE_ECC_UNCORRECTED, 0, 0),
62 GPU_NONCRITERR("l1_tag_miss_fifo_ecc_corrected", 0, 0, 0),
63 GPU_CRITERR("l1_tag_miss_fifo_ecc_uncorrected",
64 GPU_SM_L1_TAG_MISS_FIFO_ECC_UNCORRECTED, 0, 0),
65 GPU_NONCRITERR("l1_tag_s2r_pixprf_ecc_corrected", 0, 0, 0),
66 GPU_CRITERR("l1_tag_s2r_pixprf_ecc_uncorrected",
67 GPU_SM_L1_TAG_S2R_PIXPRF_ECC_UNCORRECTED, 0, 0),
68 GPU_CRITERR("machine_check_error", 0, 0, 0),
69 GPU_NONCRITERR("icache_l1_predecode_ecc_corrected", 0, 0, 0),
70 GPU_CRITERR("icache_l1_predecode_ecc_uncorrected",
71 GPU_SM_ICACHE_L1_PREDECODE_ECC_UNCORRECTED, 0, 0),
72 },
73 },
74 {
75 .name = "fecs",
76 .hw_unit = (u32)NVGPU_ERR_MODULE_FECS,
77 .num_errs = 4U,
78 .base_ecc_service_id =
79 NVGUARD_SERVICE_IGPU_FECS_SWERR_FALCON_IMEM_ECC_CORRECTED,
80 .errs = (struct nvgpu_err_desc[]) {
81 GPU_NONCRITERR("falcon_imem_ecc_corrected",
82 GPU_FECS_FALCON_IMEM_ECC_CORRECTED, 0, 0),
83 GPU_CRITERR("falcon_imem_ecc_uncorrected",
84 GPU_FECS_FALCON_IMEM_ECC_UNCORRECTED, 0, 0),
85 GPU_NONCRITERR("falcon_dmem_ecc_corrected", 0, 0, 0),
86 GPU_CRITERR("falcon_dmem_ecc_uncorrected",
87 GPU_FECS_FALCON_DMEM_ECC_UNCORRECTED, 0, 0),
88 },
89 },
90 {
91 .name = "pmu",
92 .hw_unit = NVGPU_ERR_MODULE_PMU,
93 .num_errs = 4U,
94 .base_ecc_service_id =
95 NVGUARD_SERVICE_IGPU_PMU_SWERR_FALCON_IMEM_ECC_CORRECTED,
96 .errs = (struct nvgpu_err_desc[]) {
97 GPU_NONCRITERR("falcon_imem_ecc_corrected",
98 GPU_PMU_FALCON_IMEM_ECC_CORRECTED, 0, 0),
99 GPU_CRITERR("falcon_imem_ecc_uncorrected",
100 GPU_PMU_FALCON_IMEM_ECC_UNCORRECTED, 0, 0),
101 GPU_NONCRITERR("falcon_dmem_ecc_corrected", 0, 0, 0),
102 GPU_CRITERR("falcon_dmem_ecc_uncorrected",
103 GPU_PMU_FALCON_DMEM_ECC_UNCORRECTED, 0, 0),
104 },
105 },
106};
107
108static void nvgpu_init_err_msg_header(struct gpu_err_header *header)
109{
110 header->version.major = (u16)1U;
111 header->version.minor = (u16)0U;
112 header->sub_err_type = 0U;
113 header->sub_unit_id = 0UL;
114 header->address = 0UL;
115 header->timestamp_ns = 0UL;
116}
117
118static void nvgpu_init_ecc_err_msg(struct gpu_ecc_error_info *err_info)
119{
120 nvgpu_init_err_msg_header(&err_info->header);
121 err_info->err_cnt = 0UL;
122}
123
124static void nvgpu_report_ecc_error_linux(struct gk20a *g, u32 hw_unit, u32 inst,
125 u32 err_id, u64 err_addr, u64 err_count)
126{
127 int err = 0;
128 u32 s_id = 0;
129 u8 err_status = 0;
130 u8 err_info_size = 0;
131 u64 timestamp = 0ULL;
132 int err_threshold_counter = 0;
133 struct gpu_ecc_error_info err_pkt;
134 struct nvgpu_err_desc *err_desc = NULL;
135 struct nvgpu_err_hw_module *hw_module = NULL;
136 nv_guard_request_t req;
137
138 memset(&req, 0, sizeof(req));
139 nvgpu_init_ecc_err_msg(&err_pkt);
140 if (hw_unit >= sizeof(gv11b_err_lut)/sizeof(gv11b_err_lut[0])) {
141 err = -EINVAL;
142 goto done;
143 }
144
145 hw_module = &gv11b_err_lut[hw_unit];
146 if (err_id >= hw_module->num_errs) {
147 nvgpu_err(g, "invalid err_id (%u) for hw module (%u)",
148 err_id, hw_module->hw_unit);
149 err = -EINVAL;
150 goto done;
151 }
152 err_desc = &hw_module->errs[err_id];
153 timestamp = (u64)nvgpu_current_time_ns();
154
155 err_pkt.header.timestamp_ns = timestamp;
156 err_pkt.header.sub_unit_id = inst;
157 err_pkt.header.address = err_addr;
158 err_pkt.err_cnt = err_count;
159 err_info_size = sizeof(err_pkt);
160
161 s_id = hw_module->base_ecc_service_id + err_id;
162
163 if (err_desc->is_critical) {
164 err_status = NVGUARD_ERROR_DETECTED;
165 } else {
166 err_status = NVGUARD_NO_ERROR;
167 }
168
169 nvgpu_atomic_inc(&err_desc->err_count);
170 err_threshold_counter = nvgpu_atomic_cmpxchg(&err_desc->err_count,
171 err_desc->err_threshold + 1, 0);
172
173 if (unlikely(err_threshold_counter != err_desc->err_threshold + 1)) {
174 goto done;
175 }
176
177 nvgpu_log(g, gpu_dbg_ecc, "ECC reporting hw: %s, desc:%s, count:%llu",
178 hw_module->name, err_desc->name, err_count);
179
180 req.srv_id_cmd = NVGUARD_SERVICESTATUS_NOTIFICATION;
181 req.srv_status.srv_id = (nv_guard_service_id_t)s_id;
182 req.srv_status.status = err_status;
183 req.srv_status.timestamp = timestamp;
184 req.srv_status.error_info_size = err_info_size;
185 memcpy(req.srv_status.error_info, (u8*)&err_pkt, err_info_size);
186
187 /*
188 * l1ss_submit_rq may fail due to kmalloc failures but may pass in
189 * subsequent calls
190 */
191 err = l1ss_submit_rq(&req, true);
192 if (err != 0) {
193 nvgpu_err(g, "Error returned from L1SS submit %d", err);
194 }
195
196 if (err_desc->is_critical) {
197 nvgpu_quiesce(g);
198 }
199
200done:
201 return;
202}
203
204static void nvgpu_report_ecc_error_empty(struct gk20a *g, u32 hw_unit, u32 inst,
205 u32 err_id, u64 err_addr, u64 err_count) {
206 nvgpu_log(g, gpu_dbg_ecc, "ECC reporting empty");
207}
208
209const struct nvgpu_ecc_reporting_ops default_disabled_ecc_report_ops = {
210 .report_ecc_err = nvgpu_report_ecc_error_empty,
211};
212
213const struct nvgpu_ecc_reporting_ops ecc_enable_report_ops = {
214 .report_ecc_err = nvgpu_report_ecc_error_linux,
215};
216
217static int nvgpu_l1ss_callback(l1ss_cli_callback_param param, void *data)
218{
219 struct gk20a *g = (struct gk20a *)data;
220 struct nvgpu_os_linux *l = NULL;
221 struct nvgpu_ecc_reporting_linux *ecc_reporting_linux = NULL;
222 int err = 0;
223 /* Ensure we have a valid gk20a struct before proceeding */
224 if ((g == NULL) || (gk20a_get(g) == NULL)) {
225 return -ENODEV;
226 }
227
228 l = nvgpu_os_linux_from_gk20a(g);
229 ecc_reporting_linux = &l->ecc_reporting_linux;
230
231 nvgpu_spinlock_acquire(&ecc_reporting_linux->common.lock);
232 if (param == L1SS_READY) {
233 if (!ecc_reporting_linux->common.ecc_reporting_service_enabled) {
234 ecc_reporting_linux->common.ecc_reporting_service_enabled = true;
235 ecc_reporting_linux->common.ops = &ecc_enable_report_ops;
236 nvgpu_log(g, gpu_dbg_ecc, "ECC reporting is enabled");
237 }
238 } else if (param == L1SS_NOT_READY) {
239 if (ecc_reporting_linux->common.ecc_reporting_service_enabled) {
240 ecc_reporting_linux->common.ecc_reporting_service_enabled = false;
241 ecc_reporting_linux->common.ops = &default_disabled_ecc_report_ops;
242 nvgpu_log(g, gpu_dbg_ecc, "ECC reporting is disabled");
243 }
244 } else {
245 err = -EINVAL;
246 }
247 nvgpu_spinlock_release(&ecc_reporting_linux->common.lock);
248
249 gk20a_put(g);
250
251 return err;
252}
253
254void nvgpu_init_ecc_reporting(struct gk20a *g)
255{
256 struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
257 struct nvgpu_ecc_reporting_linux *ecc_report_linux = &l->ecc_reporting_linux;
258 int err = 0;
259 /* This will invoke the registration API */
260 nvgpu_spinlock_init(&ecc_report_linux->common.lock);
261 ecc_report_linux->priv.id = (NVGUARD_GROUPID_IGPU & NVGUARD_GROUPINDEX_FIELDMASK);
262 ecc_report_linux->priv.cli_callback = nvgpu_l1ss_callback;
263 ecc_report_linux->priv.data = g;
264 ecc_report_linux->common.ops = &default_disabled_ecc_report_ops;
265
266 nvgpu_log(g, gpu_dbg_ecc, "ECC reporting Init");
267
268 /*
269 * err == 0 indicates service is available but not active yet.
270 * err == 1 indicates service is available and active
271 * error for other cases.
272 */
273 err = l1ss_register_client(&ecc_report_linux->priv);
274 if (err == 0) {
275 ecc_report_linux->common.ecc_reporting_service_enabled = false;
276 nvgpu_log(g, gpu_dbg_ecc, "ECC reporting init success");
277 } else if (err == 1) {
278 ecc_report_linux->common.ecc_reporting_service_enabled = true;
279 /* Actual Ops will be replaced during nvgpu_enable_ecc_reporting
280 * called as part of gk20a_busy()
281 */
282 } else {
283 nvgpu_log(g, gpu_dbg_ecc, "ECC reporting init failure %d", err);
284 }
285}
286
287void nvgpu_deinit_ecc_reporting(struct gk20a *g)
288{
289 struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
290 struct nvgpu_ecc_reporting_linux *ecc_report_linux = &l->ecc_reporting_linux;
291
292 if (ecc_report_linux->common.ecc_reporting_service_enabled) {
293 ecc_report_linux->common.ecc_reporting_service_enabled = false;
294 l1ss_deregister_client(ecc_report_linux->priv.id);
295 memset(ecc_report_linux, 0, sizeof(*ecc_report_linux));
296 nvgpu_log(g, gpu_dbg_ecc, "ECC reporting de-init success");
297 }
298
299}
300
301void nvgpu_enable_ecc_reporting(struct gk20a *g)
302{
303 struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
304 struct nvgpu_ecc_reporting_linux *ecc_report_linux = &l->ecc_reporting_linux;
305 struct nvgpu_ecc_reporting *error_reporting = &ecc_report_linux->common;
306
307 nvgpu_spinlock_acquire(&ecc_report_linux->common.lock);
308 if (error_reporting->ecc_reporting_service_enabled) {
309 error_reporting->ops = &ecc_enable_report_ops;
310 nvgpu_log(g, gpu_dbg_ecc, "ECC reporting is enabled");
311 }
312 nvgpu_spinlock_release(&ecc_report_linux->common.lock);
313}
314
315void nvgpu_disable_ecc_reporting(struct gk20a *g)
316{
317 struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
318 struct nvgpu_ecc_reporting_linux *ecc_report_linux = &l->ecc_reporting_linux;
319 struct nvgpu_ecc_reporting *error_reporting = &ecc_report_linux->common;
320
321 nvgpu_spinlock_acquire(&ecc_report_linux->common.lock);
322 error_reporting->ops = &default_disabled_ecc_report_ops;
323 nvgpu_log(g, gpu_dbg_ecc, "ECC reporting is disabled");
324 nvgpu_spinlock_release(&ecc_report_linux->common.lock);
325}
326
327void nvgpu_report_ecc_err(struct gk20a *g, u32 hw_unit, u32 inst,
328 u32 err_id, u64 err_addr, u64 err_count)
329{
330 struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
331 struct nvgpu_ecc_reporting_linux *ecc_report_linux = &l->ecc_reporting_linux;
332 struct nvgpu_ecc_reporting *error_reporting = &ecc_report_linux->common;
333 void (*report_ecc_err_func)(struct gk20a *g, u32 hw_unit, u32 inst,
334 u32 err_id, u64 err_addr, u64 err_count);
335
336 nvgpu_spinlock_acquire(&ecc_report_linux->common.lock);
337 report_ecc_err_func = error_reporting->ops->report_ecc_err;
338 nvgpu_spinlock_release(&ecc_report_linux->common.lock);
339
340 report_ecc_err_func(g, hw_unit, inst, err_id, err_addr, err_count);
341}
diff --git a/include/os/linux/vm.c b/include/os/linux/vm.c
index dc807ab..8956cce 100644
--- a/include/os/linux/vm.c
+++ b/include/os/linux/vm.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2017-2022, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify it 4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License, 5 * under the terms and conditions of the GNU General Public License,
@@ -50,8 +50,10 @@ static u32 nvgpu_vm_translate_linux_flags(struct gk20a *g, u32 flags)
50 core_flags |= NVGPU_VM_MAP_IO_COHERENT; 50 core_flags |= NVGPU_VM_MAP_IO_COHERENT;
51 if (flags & NVGPU_AS_MAP_BUFFER_FLAGS_UNMAPPED_PTE) 51 if (flags & NVGPU_AS_MAP_BUFFER_FLAGS_UNMAPPED_PTE)
52 core_flags |= NVGPU_VM_MAP_UNMAPPED_PTE; 52 core_flags |= NVGPU_VM_MAP_UNMAPPED_PTE;
53 if (flags & NVGPU_AS_MAP_BUFFER_FLAGS_L3_ALLOC) 53 if (!nvgpu_is_enabled(g, NVGPU_DISABLE_L3_SUPPORT)) {
54 core_flags |= NVGPU_VM_MAP_L3_ALLOC; 54 if (flags & NVGPU_AS_MAP_BUFFER_FLAGS_L3_ALLOC)
55 core_flags |= NVGPU_VM_MAP_L3_ALLOC;
56 }
55 if (flags & NVGPU_AS_MAP_BUFFER_FLAGS_DIRECT_KIND_CTRL) 57 if (flags & NVGPU_AS_MAP_BUFFER_FLAGS_DIRECT_KIND_CTRL)
56 core_flags |= NVGPU_VM_MAP_DIRECT_KIND_CTRL; 58 core_flags |= NVGPU_VM_MAP_DIRECT_KIND_CTRL;
57 if (flags & NVGPU_AS_MAP_BUFFER_FLAGS_PLATFORM_ATOMIC) 59 if (flags & NVGPU_AS_MAP_BUFFER_FLAGS_PLATFORM_ATOMIC)
diff --git a/include/os/posix/nvgpu.c b/include/os/posix/nvgpu.c
index e485ed7..5b68113 100644
--- a/include/os/posix/nvgpu.c
+++ b/include/os/posix/nvgpu.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"), 5 * copy of this software and associated documentation files (the "Software"),
@@ -36,6 +36,22 @@
36 36
37#include "os_posix.h" 37#include "os_posix.h"
38 38
39int nvgpu_wait_for_stall_interrupts(struct gk20a *g, u32 timeout)
40{
41 /*
42 * No interrupts in userspace so nothing to wait for.
43 */
44 return 0;
45}
46
47int nvgpu_wait_for_nonstall_interrupts(struct gk20a *g, u32 timeout)
48{
49 /*
50 * No interrupts in userspace so nothing to wait for.
51 */
52 return 0;
53}
54
39void nvgpu_wait_for_deferred_interrupts(struct gk20a *g) 55void nvgpu_wait_for_deferred_interrupts(struct gk20a *g)
40{ 56{
41 /* 57 /*
diff --git a/nvdebug.h b/nvdebug.h
index 50230f7..e5b6564 100644
--- a/nvdebug.h
+++ b/nvdebug.h
@@ -9,13 +9,15 @@
9 * - Helper functions for nvdebug 9 * - Helper functions for nvdebug
10 */ 10 */
11 11
12// TODO(jbakita): Don't depend on these.
13#include <nvgpu/gk20a.h> // For struct gk20a
14#include <linux/proc_fs.h> // For PDE_DATA() macro 12#include <linux/proc_fs.h> // For PDE_DATA() macro
15#include <linux/device.h> // For dev_get_drvdata() 13#include <linux/device.h> // For dev_get_drvdata()
16#include <linux/version.h> // For KERNEL_VERSION and LINUX_VERSION_CODE 14#include <linux/version.h> // For KERNEL_VERSION and LINUX_VERSION_CODE
17#include <asm/io.h> 15#include <asm/io.h>
18 16
17// Fully defined in include/nvgpu/gk20a.h. We only pass around pointers to
18// this, so declare as incomplete type to avoid pulling in the nvgpu headers.
19struct gk20a;
20
19/* Runlist Channel 21/* Runlist Channel
20 A timeslice group (TSG) is composed of channels. Each channel is a FIFO queue 22 A timeslice group (TSG) is composed of channels. Each channel is a FIFO queue
21 of GPU commands. These commands are typically queued from userspace. 23 of GPU commands. These commands are typically queued from userspace.
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-30 12:18:41 -0400