diff options
author | Saman Sahebi <saman63@cs.unc.edu> | 2023-08-03 18:00:31 -0400 |
---|---|---|
committer | Joshua Bakita <bakitajoshua@gmail.com> | 2023-10-29 15:45:32 -0400 |
commit | bebffaf223e975ab8f6fcf5fb6bd6de814fb614c (patch) | |
tree | 694f33d3e2b22590fd264e58a42f74ce64c645b0 /nvdebug.h | |
parent | 7fda166c68c58887a90521911228ef734c7d4e4f (diff) |
patched issues with GPU compatability for CE_MAP
Diffstat (limited to 'nvdebug.h')
-rw-r--r-- | nvdebug.h | 13 |
1 files changed, 9 insertions, 4 deletions
@@ -389,7 +389,9 @@ typedef union { | |||
389 | #define NV_CHIP_ID_GP106 0x136 // Discrete GeForce GTX 1060 | 389 | #define NV_CHIP_ID_GP106 0x136 // Discrete GeForce GTX 1060 |
390 | #define NV_CHIP_ID_GV11B 0x15B // Jetson Xavier embedded GPU | 390 | #define NV_CHIP_ID_GV11B 0x15B // Jetson Xavier embedded GPU |
391 | #define NV_CHIP_ID_KEPLER 0x0E0 | 391 | #define NV_CHIP_ID_KEPLER 0x0E0 |
392 | #define NV_CHIP_ID_PASCAL 0x130 | ||
392 | #define NV_CHIP_ID_VOLTA 0x140 | 393 | #define NV_CHIP_ID_VOLTA 0x140 |
394 | #define NV_CHIP_ID_TURING 0x160 | ||
393 | #define NV_CHIP_ID_AMPERE 0x170 | 395 | #define NV_CHIP_ID_AMPERE 0x170 |
394 | 396 | ||
395 | inline static const char* ARCH2NAME(uint32_t arch) { | 397 | inline static const char* ARCH2NAME(uint32_t arch) { |
@@ -687,10 +689,12 @@ typedef union { | |||
687 | Also see dev_ce.ref.txt of NVIDIA's open-gpu-doc for info. | 689 | Also see dev_ce.ref.txt of NVIDIA's open-gpu-doc for info. |
688 | */ | 690 | */ |
689 | #define NV_PTOP_SCAL_NUM_CES 0x00022444 | 691 | #define NV_PTOP_SCAL_NUM_CES 0x00022444 |
690 | //defined GRCE->CE mapping offset from nvgpu | 692 | // Defined GRCE->CE mapping offsets from nvgpu |
691 | #define NV_GRCE_FOR_CE(i)(0x00104034+(i)*4) | 693 | #define NV_GRCE_FOR_CE_GV100(i) (0x00104034+(i)*4) |
692 | //defined LCE->PCE mapping offset from nvgpu (same as ce_pce2lce_config_r(i) in nvgpu) | 694 | // Defined LCE->PCE mapping offset from nvgpu (same as ce_pce2lce_config_r(i) in nvgpu) |
693 | #define NV_LCE_FOR_PCE(i)(0x00104040+(i)*4) | 695 | #define NV_LCE_FOR_PCE_GV100(i) (0x00104040+(i)*4) |
696 | #define NV_LCE_FOR_PCE_GA100(i) (0x00104100+(i)*4) | ||
697 | #define NV_LCE_FOR_PCE_GP100(i) (0x0010402c+(i)/2) | ||
694 | 698 | ||
695 | /* Physical Copy Engine (PCE) information | 699 | /* Physical Copy Engine (PCE) information |
696 | On Pascal GPUs or newer, this register complements the above information by | 700 | On Pascal GPUs or newer, this register complements the above information by |
@@ -704,6 +708,7 @@ typedef union { | |||
704 | Also see dev_ce.ref.txt of NVIDIA's open-gpu-doc for info. | 708 | Also see dev_ce.ref.txt of NVIDIA's open-gpu-doc for info. |
705 | */ | 709 | */ |
706 | #define NV_CE_PCE_MAP 0x00104028 | 710 | #define NV_CE_PCE_MAP 0x00104028 |
711 | #define MAP_SIZE 32 | ||
707 | 712 | ||
708 | 713 | ||
709 | /* Location of the 1Kb instance block with page tables for BAR1 and BAR2. | 714 | /* Location of the 1Kb instance block with page tables for BAR1 and BAR2. |