diff options
| author | Joshua J Bakita <jbakita@rtsrv.cs.unc.edu> | 2023-11-08 14:41:47 -0500 |
|---|---|---|
| committer | Joshua Bakita <bakitajoshua@gmail.com> | 2023-11-08 15:01:24 -0500 |
| commit | 3aab3c220f3f0bcc3d3d58d0daf6fd6acf1819e2 (patch) | |
| tree | 71a0fef6595e65d42808e1f963cdd4957c2f28e6 /nvdebug.h | |
| parent | b9d8f6a83a8e5fec38e9e20a54ee13838936fa10 (diff) | |
Expand support for printing LCE<->PCE and GRCE->LCE configurationrtas24-ae
Tested working on Pascal, Volta, Volta Integrated, Turing, Ampere,
and Ada.
Also clean up minor spacing issues, an errantly added file
(nvdebug.mod), and fix some inconsistencies with upstream.
Diffstat (limited to 'nvdebug.h')
| -rw-r--r-- | nvdebug.h | 21 |
1 files changed, 14 insertions, 7 deletions
| @@ -391,8 +391,11 @@ typedef union { | |||
| 391 | #define NV_CHIP_ID_KEPLER 0x0E0 | 391 | #define NV_CHIP_ID_KEPLER 0x0E0 |
| 392 | #define NV_CHIP_ID_PASCAL 0x130 | 392 | #define NV_CHIP_ID_PASCAL 0x130 |
| 393 | #define NV_CHIP_ID_VOLTA 0x140 | 393 | #define NV_CHIP_ID_VOLTA 0x140 |
| 394 | #define NV_CHIP_ID_VOLTA_INTEGRATED 0x150 | ||
| 394 | #define NV_CHIP_ID_TURING 0x160 | 395 | #define NV_CHIP_ID_TURING 0x160 |
| 395 | #define NV_CHIP_ID_AMPERE 0x170 | 396 | #define NV_CHIP_ID_AMPERE 0x170 |
| 397 | #define NV_CHIP_ID_HOPPER 0x180 | ||
| 398 | #define NV_CHIP_ID_ADA 0x190 | ||
| 396 | 399 | ||
| 397 | inline static const char* ARCH2NAME(uint32_t arch) { | 400 | inline static const char* ARCH2NAME(uint32_t arch) { |
| 398 | switch (arch) { | 401 | switch (arch) { |
| @@ -692,16 +695,20 @@ typedef union { | |||
| 692 | // Defined number of GRCEs for a GPU | 695 | // Defined number of GRCEs for a GPU |
| 693 | # define NV_GRCE_NUM 2 | 696 | # define NV_GRCE_NUM 2 |
| 694 | // Defined GRCE->CE mapping offsets from nvgpu | 697 | // Defined GRCE->CE mapping offsets from nvgpu |
| 695 | #define NV_GRCE_FOR_CE(i) (0x00104034+(i)*4) | 698 | #define NV_GRCE_FOR_CE_GP100(i) (0x00104034+(i)*4) |
| 699 | #define NV_GRCE_FOR_CE_GA100(i) (0x001041c0+(i)*4) | ||
| 696 | // Defined LCE->PCE mapping offset from nvgpu (same as ce_pce2lce_config_r(i) in nvgpu) | 700 | // Defined LCE->PCE mapping offset from nvgpu (same as ce_pce2lce_config_r(i) in nvgpu) |
| 701 | #define NV_LCE_FOR_PCE_GP100(i) (0x0010402c+(i)/2) | ||
| 697 | #define NV_LCE_FOR_PCE_GV100(i) (0x00104040+(i)*4) | 702 | #define NV_LCE_FOR_PCE_GV100(i) (0x00104040+(i)*4) |
| 698 | #define NV_LCE_FOR_PCE_GA100(i) (0x00104100+(i)*4) | 703 | #define NV_LCE_FOR_PCE_GA100(i) (0x00104100+(i)*4) |
| 699 | #define NV_LCE_FOR_PCE_GP100(i) (0x0010402c+(i)/2) | 704 | // Struct for use with nvdebug_reg_range_read() |
| 700 | #define NV_LCE_FOR_PCE_TU104(i) (0x00104040+(i)*4) | 705 | union reg_range { |
| 701 | // Defined struct for storing PCE index and offset for proc_create | 706 | struct { |
| 702 | struct combo { | 707 | uint32_t offset; |
| 703 | uint32_t offset:32; | 708 | uint8_t start_bit; |
| 704 | uint32_t index:32; | 709 | uint8_t stop_bit; |
| 710 | }; | ||
| 711 | uint64_t raw; | ||
| 705 | }; | 712 | }; |
| 706 | 713 | ||
| 707 | /* Physical Copy Engine (PCE) information | 714 | /* Physical Copy Engine (PCE) information |
