From 3aab3c220f3f0bcc3d3d58d0daf6fd6acf1819e2 Mon Sep 17 00:00:00 2001 From: Joshua J Bakita Date: Wed, 8 Nov 2023 14:41:47 -0500 Subject: Expand support for printing LCE<->PCE and GRCE->LCE configuration Tested working on Pascal, Volta, Volta Integrated, Turing, Ampere, and Ada. Also clean up minor spacing issues, an errantly added file (nvdebug.mod), and fix some inconsistencies with upstream. --- nvdebug.h | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) (limited to 'nvdebug.h') diff --git a/nvdebug.h b/nvdebug.h index b0e6bb8..a9366e0 100644 --- a/nvdebug.h +++ b/nvdebug.h @@ -391,8 +391,11 @@ typedef union { #define NV_CHIP_ID_KEPLER 0x0E0 #define NV_CHIP_ID_PASCAL 0x130 #define NV_CHIP_ID_VOLTA 0x140 +#define NV_CHIP_ID_VOLTA_INTEGRATED 0x150 #define NV_CHIP_ID_TURING 0x160 #define NV_CHIP_ID_AMPERE 0x170 +#define NV_CHIP_ID_HOPPER 0x180 +#define NV_CHIP_ID_ADA 0x190 inline static const char* ARCH2NAME(uint32_t arch) { switch (arch) { @@ -692,16 +695,20 @@ typedef union { // Defined number of GRCEs for a GPU # define NV_GRCE_NUM 2 // Defined GRCE->CE mapping offsets from nvgpu -#define NV_GRCE_FOR_CE(i) (0x00104034+(i)*4) +#define NV_GRCE_FOR_CE_GP100(i) (0x00104034+(i)*4) +#define NV_GRCE_FOR_CE_GA100(i) (0x001041c0+(i)*4) // Defined LCE->PCE mapping offset from nvgpu (same as ce_pce2lce_config_r(i) in nvgpu) +#define NV_LCE_FOR_PCE_GP100(i) (0x0010402c+(i)/2) #define NV_LCE_FOR_PCE_GV100(i) (0x00104040+(i)*4) #define NV_LCE_FOR_PCE_GA100(i) (0x00104100+(i)*4) -#define NV_LCE_FOR_PCE_GP100(i) (0x0010402c+(i)/2) -#define NV_LCE_FOR_PCE_TU104(i) (0x00104040+(i)*4) -// Defined struct for storing PCE index and offset for proc_create -struct combo { - uint32_t offset:32; - uint32_t index:32; +// Struct for use with nvdebug_reg_range_read() +union reg_range { + struct { + uint32_t offset; + uint8_t start_bit; + uint8_t stop_bit; + }; + uint64_t raw; }; /* Physical Copy Engine (PCE) information -- cgit v1.2.2