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authorJoshua Bakita <bakitajoshua@gmail.com>2024-09-25 16:09:09 -0400
committerJoshua Bakita <bakitajoshua@gmail.com>2024-09-25 16:09:09 -0400
commitf347fde22f1297e4f022600d201780d5ead78114 (patch)
tree76be305d6187003a1e0486ff6e91efb1062ae118 /include/therm
parent8340d234d78a7d0f46c11a584de538148b78b7cb (diff)
Delete no-longer-needed nvgpu headers
The dependency on these was removed in commit 8340d234.
Diffstat (limited to 'include/therm')
-rw-r--r--include/therm/thrm.c55
-rw-r--r--include/therm/thrm.h38
-rw-r--r--include/therm/thrmchannel.c256
-rw-r--r--include/therm/thrmchannel.h51
-rw-r--r--include/therm/thrmdev.c370
-rw-r--r--include/therm/thrmdev.h58
-rw-r--r--include/therm/thrmpmu.c271
-rw-r--r--include/therm/thrmpmu.h31
8 files changed, 0 insertions, 1130 deletions
diff --git a/include/therm/thrm.c b/include/therm/thrm.c
deleted file mode 100644
index c4e2731..0000000
--- a/include/therm/thrm.c
+++ /dev/null
@@ -1,55 +0,0 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#include <nvgpu/gk20a.h>
24
25#include "thrm.h"
26#include "thrmpmu.h"
27
28u32 therm_domain_sw_setup(struct gk20a *g)
29{
30 u32 status;
31
32 status = therm_device_sw_setup(g);
33 if (status) {
34 nvgpu_err(g,
35 "error creating boardobjgrp for therm devices, status - 0x%x",
36 status);
37 goto exit;
38 }
39
40 status = therm_channel_sw_setup(g);
41 if (status) {
42 nvgpu_err(g,
43 "error creating boardobjgrp for therm channel, status - 0x%x",
44 status);
45 goto exit;
46 }
47
48exit:
49 return status;
50}
51
52u32 therm_domain_pmu_setup(struct gk20a *g)
53{
54 return therm_send_pmgr_tables_to_pmu(g);
55}
diff --git a/include/therm/thrm.h b/include/therm/thrm.h
deleted file mode 100644
index d9d73b7..0000000
--- a/include/therm/thrm.h
+++ /dev/null
@@ -1,38 +0,0 @@
1/*
2 * general thermal table structures & definitions
3 *
4 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24#ifndef NVGPU_THERM_THRM_H
25#define NVGPU_THERM_THRM_H
26
27#include "thrmdev.h"
28#include "thrmchannel.h"
29
30struct therm_pmupstate {
31 struct therm_devices therm_deviceobjs;
32 struct therm_channels therm_channelobjs;
33};
34
35u32 therm_domain_sw_setup(struct gk20a *g);
36u32 therm_domain_pmu_setup(struct gk20a *g);
37
38#endif /* NVGPU_THERM_THRM_H */
diff --git a/include/therm/thrmchannel.c b/include/therm/thrmchannel.c
deleted file mode 100644
index 419ce0b..0000000
--- a/include/therm/thrmchannel.c
+++ /dev/null
@@ -1,256 +0,0 @@
1/*
2 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#include <nvgpu/bios.h>
24#include <nvgpu/gk20a.h>
25#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
26
27#include "thrmchannel.h"
28#include "boardobj/boardobjgrp.h"
29#include "boardobj/boardobjgrp_e32.h"
30#include "gp106/bios_gp106.h"
31
32static int _therm_channel_pmudatainit_device(struct gk20a *g,
33 struct boardobj *board_obj_ptr,
34 struct nv_pmu_boardobj *ppmudata)
35{
36 int status = 0;
37 struct therm_channel *pchannel;
38 struct therm_channel_device *ptherm_channel;
39 struct nv_pmu_therm_therm_channel_device_boardobj_set *pset;
40
41 status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata);
42 if (status) {
43 nvgpu_err(g,
44 "error updating pmu boardobjgrp for therm channel 0x%x",
45 status);
46 status = -ENOMEM;
47 goto done;
48 }
49
50 pchannel = (struct therm_channel *)board_obj_ptr;
51 pset = (struct nv_pmu_therm_therm_channel_device_boardobj_set *)ppmudata;
52 ptherm_channel = (struct therm_channel_device *)board_obj_ptr;
53
54 pset->super.scaling = pchannel->scaling;
55 pset->super.offset = pchannel->offset;
56 pset->super.temp_min = pchannel->temp_min;
57 pset->super.temp_max = pchannel->temp_max;
58
59 pset->therm_dev_idx = ptherm_channel->therm_dev_idx;
60 pset->therm_dev_prov_idx = ptherm_channel->therm_dev_prov_idx;
61
62done:
63 return status;
64}
65static struct boardobj *construct_channel_device(struct gk20a *g,
66 void *pargs, u16 pargs_size, u8 type)
67{
68 struct boardobj *board_obj_ptr = NULL;
69 struct therm_channel *pchannel;
70 struct therm_channel_device *pchannel_device;
71 int status;
72 struct therm_channel_device *therm_device = (struct therm_channel_device*)pargs;
73
74 status = boardobj_construct_super(g, &board_obj_ptr,
75 pargs_size, pargs);
76 if (status) {
77 return NULL;
78 }
79
80 /* Set Super class interfaces */
81 board_obj_ptr->pmudatainit = _therm_channel_pmudatainit_device;
82
83 pchannel = (struct therm_channel *)board_obj_ptr;
84 pchannel_device = (struct therm_channel_device *)board_obj_ptr;
85
86 g->ops.therm.get_internal_sensor_limits(&pchannel->temp_max,
87 &pchannel->temp_min);
88 pchannel->scaling = (1 << 8);
89 pchannel->offset = 0;
90
91 pchannel_device->therm_dev_idx = therm_device->therm_dev_idx;
92 pchannel_device->therm_dev_prov_idx = therm_device->therm_dev_prov_idx;
93
94 nvgpu_log_info(g, " Done");
95
96 return board_obj_ptr;
97}
98
99static int _therm_channel_pmudata_instget(struct gk20a *g,
100 struct nv_pmu_boardobjgrp *pmuboardobjgrp,
101 struct nv_pmu_boardobj **ppboardobjpmudata,
102 u8 idx)
103{
104 struct nv_pmu_therm_therm_channel_boardobj_grp_set *pgrp_set =
105 (struct nv_pmu_therm_therm_channel_boardobj_grp_set *)
106 pmuboardobjgrp;
107
108 nvgpu_log_info(g, " ");
109
110 /*check whether pmuboardobjgrp has a valid boardobj in index*/
111 if (((u32)BIT(idx) &
112 pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0) {
113 return -EINVAL;
114 }
115
116 *ppboardobjpmudata = (struct nv_pmu_boardobj *)
117 &pgrp_set->objects[idx].data.board_obj;
118
119 nvgpu_log_info(g, " Done");
120
121 return 0;
122}
123
124static int devinit_get_therm_channel_table(struct gk20a *g,
125 struct therm_channels *pthermchannelobjs)
126{
127 int status = 0;
128 u8 *therm_channel_table_ptr = NULL;
129 u8 *curr_therm_channel_table_ptr = NULL;
130 struct boardobj *boardobj;
131 struct therm_channel_1x_header therm_channel_table_header = { 0 };
132 struct therm_channel_1x_entry *therm_channel_table_entry = NULL;
133 u32 index;
134 u32 obj_index = 0;
135 u16 therm_channel_size = 0;
136 union {
137 struct boardobj boardobj;
138 struct therm_channel therm_channel;
139 struct therm_channel_device device;
140 } therm_channel_data;
141
142 nvgpu_log_info(g, " ");
143
144 therm_channel_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
145 g->bios.perf_token, THERMAL_CHANNEL_TABLE);
146 if (therm_channel_table_ptr == NULL) {
147 status = -EINVAL;
148 goto done;
149 }
150
151 memcpy(&therm_channel_table_header, therm_channel_table_ptr,
152 VBIOS_THERM_CHANNEL_1X_HEADER_SIZE_09);
153
154 if (therm_channel_table_header.version !=
155 VBIOS_THERM_CHANNEL_VERSION_1X) {
156 status = -EINVAL;
157 goto done;
158 }
159
160 if (therm_channel_table_header.header_size <
161 VBIOS_THERM_CHANNEL_1X_HEADER_SIZE_09) {
162 status = -EINVAL;
163 goto done;
164 }
165
166 curr_therm_channel_table_ptr = (therm_channel_table_ptr +
167 VBIOS_THERM_CHANNEL_1X_HEADER_SIZE_09);
168
169 for (index = 0; index < therm_channel_table_header.num_table_entries;
170 index++) {
171 therm_channel_table_entry = (struct therm_channel_1x_entry *)
172 (curr_therm_channel_table_ptr +
173 (therm_channel_table_header.table_entry_size * index));
174
175 if (therm_channel_table_entry->class_id !=
176 NV_VBIOS_THERM_CHANNEL_1X_ENTRY_CLASS_DEVICE) {
177 continue;
178 }
179
180 therm_channel_data.device.therm_dev_idx = therm_channel_table_entry->param0;
181 therm_channel_data.device.therm_dev_prov_idx = therm_channel_table_entry->param1;
182
183 therm_channel_size = sizeof(struct therm_channel_device);
184 therm_channel_data.boardobj.type = CTRL_THERMAL_THERM_CHANNEL_CLASS_DEVICE;
185
186 boardobj = construct_channel_device(g, &therm_channel_data,
187 therm_channel_size, therm_channel_data.boardobj.type);
188
189 if (!boardobj) {
190 nvgpu_err(g,
191 "unable to create thermal device for %d type %d",
192 index, therm_channel_data.boardobj.type);
193 status = -EINVAL;
194 goto done;
195 }
196
197 status = boardobjgrp_objinsert(&pthermchannelobjs->super.super,
198 boardobj, obj_index);
199
200 if (status) {
201 nvgpu_err(g,
202 "unable to insert thermal device boardobj for %d", index);
203 status = -EINVAL;
204 goto done;
205 }
206
207 ++obj_index;
208 }
209
210done:
211 nvgpu_log_info(g, " done status %x", status);
212 return status;
213}
214
215int therm_channel_sw_setup(struct gk20a *g)
216{
217 int status;
218 struct boardobjgrp *pboardobjgrp = NULL;
219 struct therm_channels *pthermchannelobjs;
220
221 /* Construct the Super Class and override the Interfaces */
222 status = boardobjgrpconstruct_e32(g,
223 &g->therm_pmu.therm_channelobjs.super);
224 if (status) {
225 nvgpu_err(g,
226 "error creating boardobjgrp for therm devices, status - 0x%x",
227 status);
228 goto done;
229 }
230
231 pboardobjgrp = &g->therm_pmu.therm_channelobjs.super.super;
232 pthermchannelobjs = &(g->therm_pmu.therm_channelobjs);
233
234 /* Override the Interfaces */
235 pboardobjgrp->pmudatainstget = _therm_channel_pmudata_instget;
236
237 status = devinit_get_therm_channel_table(g, pthermchannelobjs);
238 if (status) {
239 goto done;
240 }
241
242 BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, THERM, THERM_CHANNEL);
243
244 status = BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp,
245 therm, THERM, therm_channel, THERM_CHANNEL);
246 if (status) {
247 nvgpu_err(g,
248 "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x",
249 status);
250 goto done;
251 }
252
253done:
254 nvgpu_log_info(g, " done status %x", status);
255 return status;
256}
diff --git a/include/therm/thrmchannel.h b/include/therm/thrmchannel.h
deleted file mode 100644
index 89be673..0000000
--- a/include/therm/thrmchannel.h
+++ /dev/null
@@ -1,51 +0,0 @@
1/*
2 * general thermal device structures & definitions
3 *
4 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24#ifndef NVGPU_THERM_THRMCHANNEL_H
25#define NVGPU_THERM_THRMCHANNEL_H
26
27#include "boardobj/boardobj.h"
28#include "boardobj/boardobjgrp.h"
29#include "ctrl/ctrltherm.h"
30
31struct therm_channel {
32 struct boardobj super;
33 s16 scaling;
34 s16 offset;
35 s32 temp_min;
36 s32 temp_max;
37};
38
39struct therm_channels {
40 struct boardobjgrp_e32 super;
41};
42
43struct therm_channel_device {
44 struct therm_channel super;
45 u8 therm_dev_idx;
46 u8 therm_dev_prov_idx;
47};
48
49int therm_channel_sw_setup(struct gk20a *g);
50
51#endif /* NVGPU_THERM_THRMCHANNEL_H */
diff --git a/include/therm/thrmdev.c b/include/therm/thrmdev.c
deleted file mode 100644
index 63e1033..0000000
--- a/include/therm/thrmdev.c
+++ /dev/null
@@ -1,370 +0,0 @@
1/*
2 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#include <nvgpu/bios.h>
24#include <nvgpu/gk20a.h>
25#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
26
27#include "thrmdev.h"
28#include "boardobj/boardobjgrp.h"
29#include "boardobj/boardobjgrp_e32.h"
30#include "gp106/bios_gp106.h"
31#include "ctrl/ctrltherm.h"
32
33static int _therm_device_pmudata_instget(struct gk20a *g,
34 struct nv_pmu_boardobjgrp *pmuboardobjgrp,
35 struct nv_pmu_boardobj **ppboardobjpmudata,
36 u8 idx)
37{
38 struct nv_pmu_therm_therm_device_boardobj_grp_set *pgrp_set =
39 (struct nv_pmu_therm_therm_device_boardobj_grp_set *)
40 pmuboardobjgrp;
41
42 nvgpu_log_info(g, " ");
43
44 /*check whether pmuboardobjgrp has a valid boardobj in index*/
45 if (((u32)BIT(idx) &
46 pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0) {
47 return -EINVAL;
48 }
49
50 *ppboardobjpmudata = (struct nv_pmu_boardobj *)
51 &pgrp_set->objects[idx].data;
52
53 nvgpu_log_info(g, " Done");
54
55 return 0;
56}
57
58static int construct_therm_device(struct gk20a *g,
59 struct boardobj **ppboardobj, u16 size, void *pargs)
60{
61 return boardobj_construct_super(g, ppboardobj, size, pargs);
62}
63
64static int construct_therm_device_gpu(struct gk20a *g,
65 struct boardobj **ppboardobj, u16 size, void *pargs)
66{
67 return construct_therm_device(g, ppboardobj, size, pargs);
68}
69
70static int construct_therm_device_gpu_sci(struct gk20a *g,
71 struct boardobj **ppboardobj, u16 size, void *pargs)
72{
73 return construct_therm_device(g, ppboardobj, size, pargs);
74}
75
76
77static int therm_device_pmu_data_init_gpu_gpc_tsosc(struct gk20a *g,
78 struct boardobj *pboard_obj, struct nv_pmu_boardobj *ppmudata)
79{
80 int status = 0;
81 struct therm_device_gpu_gpc_tsosc *pdev = NULL;
82 struct nv_pmu_therm_therm_device_gpu_gpc_tsosc_boardobj_set *pset;
83
84 status = boardobj_pmudatainit_super(g, pboard_obj, ppmudata);
85 if (status != 0) {
86 goto exit;
87 }
88
89 pdev = (struct therm_device_gpu_gpc_tsosc *)(void *)pboard_obj;
90 pset = (struct nv_pmu_therm_therm_device_gpu_gpc_tsosc_boardobj_set *)
91 (void*) ppmudata;
92
93 pset->gpc_tsosc_idx = pdev->gpc_tsosc_idx;
94
95exit:
96 return status;
97}
98
99static int construct_therm_device_gpu_tsosc(struct gk20a *g,
100 struct boardobj **ppboardobj, u16 size, void *pargs)
101{
102 struct therm_device_gpu_gpc_tsosc *pdev = NULL;
103 struct therm_device_gpu_gpc_tsosc *ptmp_dev =
104 (struct therm_device_gpu_gpc_tsosc *)pargs;
105 int status = 0;
106
107 status = construct_therm_device(g, ppboardobj, size, pargs);
108 if (status != 0) {
109 return status;
110 }
111
112 pdev = (struct therm_device_gpu_gpc_tsosc *)(void *)*ppboardobj;
113
114 pdev->super.super.pmudatainit =
115 therm_device_pmu_data_init_gpu_gpc_tsosc;
116
117 pdev->gpc_tsosc_idx = ptmp_dev->gpc_tsosc_idx;
118
119 return status;
120}
121
122static int therm_device_pmu_data_init_hbm2_site(struct gk20a *g,
123 struct boardobj *pboard_obj, struct nv_pmu_boardobj *ppmudata)
124{
125 int status = 0;
126 struct therm_device_hbm2_site *pdev = NULL;
127 struct nv_pmu_therm_therm_device_hbm2_site_boardobj_set *pset;
128
129 status = boardobj_pmudatainit_super(g, pboard_obj, ppmudata);
130 if (status != 0) {
131 goto exit;
132 }
133
134 pdev = (struct therm_device_hbm2_site *)(void *)pboard_obj;
135 pset = (struct nv_pmu_therm_therm_device_hbm2_site_boardobj_set *)
136 (void *)ppmudata;
137
138 pset->site_idx = pdev->site_idx;
139
140exit:
141 return status;
142}
143
144static int construct_therm_device_hbm2_site(struct gk20a *g,
145 struct boardobj **ppboardobj, u16 size, void *pargs)
146{
147 struct therm_device_hbm2_site *pdev = NULL;
148 struct therm_device_hbm2_site *ptmp_dev =
149 (struct therm_device_hbm2_site *)pargs;
150 int status = 0;
151
152 status = construct_therm_device(g, ppboardobj, size, pargs);
153 if (status != 0) {
154 return status;
155 }
156
157 pdev = (struct therm_device_hbm2_site *)(void *)*ppboardobj;
158
159 pdev->super.super.pmudatainit =
160 therm_device_pmu_data_init_hbm2_site;
161
162 pdev->site_idx = ptmp_dev->site_idx;
163
164 return status;
165}
166
167static int construct_therm_device_hbm2_combined(struct gk20a *g,
168 struct boardobj **ppboardobj, u16 size, void *pargs)
169{
170 return construct_therm_device(g, ppboardobj, size, pargs);
171}
172
173
174static struct boardobj *therm_device_construct(struct gk20a *g,
175 void *pargs)
176{
177 struct boardobj *board_obj_ptr = NULL;
178 int status = 0;
179
180 switch (BOARDOBJ_GET_TYPE(pargs)) {
181 case NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_GPU:
182 status = construct_therm_device_gpu(g, &board_obj_ptr,
183 sizeof(struct therm_device), pargs);
184 break;
185 case NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_GPU_GPC_SCI:
186 status = construct_therm_device_gpu_sci(g, &board_obj_ptr,
187 sizeof(struct therm_device_gpu_sci), pargs);
188 break;
189 case NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_GPU_GPC_TSOSC:
190 status = construct_therm_device_gpu_tsosc(g, &board_obj_ptr,
191 sizeof(struct therm_device_gpu_gpc_tsosc), pargs);
192 break;
193 case NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_HBM2_SITE:
194 status = construct_therm_device_hbm2_site(g, &board_obj_ptr,
195 sizeof(struct therm_device_hbm2_site), pargs);
196 break;
197 case NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_HBM2_COMBINED:
198 status = construct_therm_device_hbm2_combined(g, &board_obj_ptr,
199 sizeof(struct therm_device_hbm2_combined), pargs);
200 break;
201 default:
202 nvgpu_err(g,
203 "unsupported therm_device class - 0x%x",
204 BOARDOBJ_GET_TYPE(pargs));
205 break;
206 }
207
208 if(status) {
209 board_obj_ptr = NULL;
210 nvgpu_err(g,
211 "could not allocate memory for therm_device");
212 if (board_obj_ptr != NULL) {
213 nvgpu_kfree(g, board_obj_ptr);
214 }
215 }
216
217
218 return board_obj_ptr;
219}
220
221static int devinit_get_therm_device_table(struct gk20a *g,
222 struct therm_devices *pthermdeviceobjs)
223{
224 int status = 0;
225 u8 *therm_device_table_ptr = NULL;
226 u8 *curr_therm_device_table_ptr = NULL;
227 struct boardobj *boardobj;
228 struct therm_device_1x_header therm_device_table_header = { 0 };
229 struct therm_device_1x_entry *therm_device_table_entry = NULL;
230 u32 index;
231 u32 obj_index = 0;
232 u8 class_id = 0;
233 union {
234 struct boardobj boardobj;
235 struct therm_device therm_device;
236 struct therm_device_gpu_sci gpu_sci;
237 struct therm_device_gpu_gpc_tsosc gpu_gpc_tsosc;
238 struct therm_device_hbm2_site hbm2_site;
239 struct therm_device_hbm2_combined hbm2_combined;
240 } therm_device_data;
241
242 nvgpu_log_info(g, " ");
243
244 therm_device_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
245 g->bios.perf_token, THERMAL_DEVICE_TABLE);
246 if (therm_device_table_ptr == NULL) {
247 status = -EINVAL;
248 goto done;
249 }
250
251 memcpy(&therm_device_table_header, therm_device_table_ptr,
252 VBIOS_THERM_DEVICE_1X_HEADER_SIZE_04);
253
254 if (therm_device_table_header.version !=
255 VBIOS_THERM_DEVICE_VERSION_1X) {
256 status = -EINVAL;
257 goto done;
258 }
259
260 if (therm_device_table_header.header_size <
261 VBIOS_THERM_DEVICE_1X_HEADER_SIZE_04) {
262 status = -EINVAL;
263 goto done;
264 }
265
266 curr_therm_device_table_ptr = (therm_device_table_ptr +
267 VBIOS_THERM_DEVICE_1X_HEADER_SIZE_04);
268
269 for (index = 0; index < therm_device_table_header.num_table_entries;
270 index++) {
271 therm_device_table_entry = (struct therm_device_1x_entry *)
272 (curr_therm_device_table_ptr +
273 (therm_device_table_header.table_entry_size * index));
274
275 class_id = therm_device_table_entry->class_id;
276
277 switch (class_id) {
278 case NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_INVALID:
279 continue;
280 break;
281 case NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_GPU:
282 case NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_GPU_GPC_SCI:
283 break;
284 case NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_GPU_GPC_TSOSC:
285 therm_device_data.gpu_gpc_tsosc.gpc_tsosc_idx =
286 therm_device_table_entry->param0;
287 break;
288 case NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_HBM2_SITE:
289 therm_device_data.hbm2_site.site_idx =
290 therm_device_table_entry->param0;
291 break;
292 case NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_HBM2_COMBINED:
293 break;
294 default:
295 nvgpu_err(g,
296 "Unknown thermal device class i - %x, class - %x",
297 index, class_id);
298 goto done;
299 }
300
301 therm_device_data.boardobj.type = class_id;
302 boardobj = therm_device_construct(g, &therm_device_data);
303 if (!boardobj) {
304 nvgpu_err(g,
305 "unable to create thermal device for %d type %d",
306 index, therm_device_data.boardobj.type);
307 status = -EINVAL;
308 goto done;
309 }
310
311 status = boardobjgrp_objinsert(&pthermdeviceobjs->super.super,
312 boardobj, obj_index);
313
314 if (status) {
315 nvgpu_err(g,
316 "unable to insert thermal device boardobj for %d", index);
317 status = -EINVAL;
318 goto done;
319 }
320
321 ++obj_index;
322 }
323
324done:
325 nvgpu_log_info(g, " done status %x", status);
326 return status;
327}
328
329int therm_device_sw_setup(struct gk20a *g)
330{
331 int status;
332 struct boardobjgrp *pboardobjgrp = NULL;
333 struct therm_devices *pthermdeviceobjs;
334
335 /* Construct the Super Class and override the Interfaces */
336 status = boardobjgrpconstruct_e32(g,
337 &g->therm_pmu.therm_deviceobjs.super);
338 if (status) {
339 nvgpu_err(g,
340 "error creating boardobjgrp for therm devices, status - 0x%x",
341 status);
342 goto done;
343 }
344
345 pboardobjgrp = &g->therm_pmu.therm_deviceobjs.super.super;
346 pthermdeviceobjs = &(g->therm_pmu.therm_deviceobjs);
347
348 /* Override the Interfaces */
349 pboardobjgrp->pmudatainstget = _therm_device_pmudata_instget;
350
351 status = devinit_get_therm_device_table(g, pthermdeviceobjs);
352 if (status) {
353 goto done;
354 }
355
356 BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, THERM, THERM_DEVICE);
357
358 status = BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp,
359 therm, THERM, therm_device, THERM_DEVICE);
360 if (status) {
361 nvgpu_err(g,
362 "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x",
363 status);
364 goto done;
365 }
366
367done:
368 nvgpu_log_info(g, " done status %x", status);
369 return status;
370}
diff --git a/include/therm/thrmdev.h b/include/therm/thrmdev.h
deleted file mode 100644
index 151e96f..0000000
--- a/include/therm/thrmdev.h
+++ /dev/null
@@ -1,58 +0,0 @@
1/*
2 * general thermal device structures & definitions
3 *
4 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24#ifndef NVGPU_THERM_THRMDEV_H
25#define NVGPU_THERM_THRMDEV_H
26
27#include "boardobj/boardobj.h"
28#include "boardobj/boardobjgrp.h"
29
30struct therm_devices {
31 struct boardobjgrp_e32 super;
32};
33
34struct therm_device {
35 struct boardobj super;
36};
37
38struct therm_device_gpu_sci {
39 struct therm_device super;
40};
41
42struct therm_device_gpu_gpc_tsosc {
43 struct therm_device super;
44 u8 gpc_tsosc_idx;
45};
46
47struct therm_device_hbm2_site {
48 struct therm_device super;
49 u8 site_idx;
50};
51
52struct therm_device_hbm2_combined {
53 struct therm_device super;
54};
55
56int therm_device_sw_setup(struct gk20a *g);
57
58#endif /* NVGPU_THERM_THRMDEV_H */
diff --git a/include/therm/thrmpmu.c b/include/therm/thrmpmu.c
deleted file mode 100644
index 65587ab..0000000
--- a/include/therm/thrmpmu.c
+++ /dev/null
@@ -1,271 +0,0 @@
1/*
2 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22#include <nvgpu/gk20a.h>
23
24#include "boardobj/boardobjgrp.h"
25#include "boardobj/boardobjgrp_e32.h"
26#include "thrmpmu.h"
27#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
28
29struct therm_pmucmdhandler_params {
30 struct nv_pmu_therm_rpc *prpccall;
31 u32 success;
32};
33
34static void therm_pmucmdhandler(struct gk20a *g, struct pmu_msg *msg,
35 void *param, u32 handle, u32 status)
36{
37 struct therm_pmucmdhandler_params *phandlerparams =
38 (struct therm_pmucmdhandler_params *)param;
39
40 if (msg->msg.therm.msg_type != NV_PMU_THERM_MSG_ID_RPC) {
41 nvgpu_err(g, "unknow msg %x",
42 msg->msg.pmgr.msg_type);
43 return;
44 }
45
46 if (!phandlerparams->prpccall->b_supported) {
47 nvgpu_err(g, "RPC msg %x failed",
48 msg->msg.pmgr.msg_type);
49 } else {
50 phandlerparams->success = 1;
51 }
52}
53
54int therm_send_pmgr_tables_to_pmu(struct gk20a *g)
55{
56 int status = 0;
57 struct boardobjgrp *pboardobjgrp = NULL;
58
59 if (!BOARDOBJGRP_IS_EMPTY(&g->therm_pmu.therm_deviceobjs.super.super)) {
60 pboardobjgrp = &g->therm_pmu.therm_deviceobjs.super.super;
61 status = pboardobjgrp->pmuinithandle(g, pboardobjgrp);
62 if (status) {
63 nvgpu_err(g,
64 "therm_send_pmgr_tables_to_pmu - therm_device failed %x",
65 status);
66 goto exit;
67 }
68 }
69
70 if (!BOARDOBJGRP_IS_EMPTY(
71 &g->therm_pmu.therm_channelobjs.super.super)) {
72 pboardobjgrp = &g->therm_pmu.therm_channelobjs.super.super;
73 status = pboardobjgrp->pmuinithandle(g, pboardobjgrp);
74 if (status) {
75 nvgpu_err(g,
76 "therm_send_pmgr_tables_to_pmu - therm_channel failed %x",
77 status);
78 goto exit;
79 }
80 }
81
82exit:
83 return status;
84}
85
86static u32 therm_pmu_cmd_post(struct gk20a *g, struct pmu_cmd *cmd,
87 struct pmu_msg *msg, struct pmu_payload *payload,
88 u32 queue_id, pmu_callback callback, void* cb_param,
89 u32 *seq_desc, unsigned long timeout)
90{
91 u32 status;
92 struct therm_pmucmdhandler_params *handlerparams = NULL;
93
94 status = nvgpu_pmu_cmd_post(g, cmd, msg, payload,
95 queue_id,
96 callback,
97 cb_param,
98 seq_desc,
99 timeout);
100 if (status) {
101 nvgpu_err(g,
102 "unable to post therm cmd for unit %x cmd id %x size %x",
103 cmd->hdr.unit_id, cmd->cmd.therm.cmd_type, cmd->hdr.size);
104 goto exit;
105 }
106
107 if (cb_param) {
108 handlerparams = (struct therm_pmucmdhandler_params*)cb_param;
109
110 pmu_wait_message_cond(&g->pmu,
111 gk20a_get_gr_idle_timeout(g),
112 &handlerparams->success, 1);
113
114 if (handlerparams->success == 0) {
115 nvgpu_err(g, "could not process cmd");
116 status = -ETIMEDOUT;
117 goto exit;
118 }
119 }
120
121exit:
122 return status;
123}
124
125static u32 therm_set_warn_temp_limit(struct gk20a *g)
126{
127 u32 seqdesc = 0;
128 struct pmu_cmd cmd;
129 struct pmu_msg msg;
130 struct pmu_payload payload;
131 struct nv_pmu_therm_rpc rpccall;
132 struct therm_pmucmdhandler_params handlerparams;
133
134 memset(&payload, 0, sizeof(struct pmu_payload));
135 memset(&cmd, 0, sizeof(struct pmu_cmd));
136 memset(&msg, 0, sizeof(struct pmu_msg));
137 memset(&rpccall, 0, sizeof(struct nv_pmu_therm_rpc));
138 memset(&handlerparams, 0, sizeof(struct therm_pmucmdhandler_params));
139
140 rpccall.function = NV_PMU_THERM_RPC_ID_SLCT_EVENT_TEMP_TH_SET;
141 rpccall.params.slct_event_temp_th_set.event_id =
142 NV_PMU_THERM_EVENT_THERMAL_1;
143 rpccall.params.slct_event_temp_th_set.temp_threshold = g->curr_warn_temp;
144 rpccall.b_supported = 0;
145
146 cmd.hdr.unit_id = PMU_UNIT_THERM;
147 cmd.hdr.size = ((u32)sizeof(struct nv_pmu_therm_cmd_rpc) +
148 (u32)sizeof(struct pmu_hdr));
149 cmd.cmd.therm.cmd_type = NV_PMU_THERM_CMD_ID_RPC;
150
151 msg.hdr.size = sizeof(struct pmu_msg);
152
153 payload.in.buf = (u8 *)&rpccall;
154 payload.in.size = (u32)sizeof(struct nv_pmu_therm_rpc);
155 payload.in.fb_size = PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED;
156 payload.in.offset = NV_PMU_THERM_CMD_RPC_ALLOC_OFFSET;
157
158 payload.out.buf = (u8 *)&rpccall;
159 payload.out.size = (u32)sizeof(struct nv_pmu_therm_rpc);
160 payload.out.fb_size = PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED;
161 payload.out.offset = NV_PMU_CLK_MSG_RPC_ALLOC_OFFSET;
162
163 /* Setup the handler params to communicate back results.*/
164 handlerparams.success = 0;
165 handlerparams.prpccall = &rpccall;
166
167 return therm_pmu_cmd_post(g, &cmd, NULL, &payload,
168 PMU_COMMAND_QUEUE_LPQ,
169 therm_pmucmdhandler,
170 (void *)&handlerparams,
171 &seqdesc, ~0);
172}
173
174static u32 therm_enable_slct_notification_request(struct gk20a *g)
175{
176 u32 seqdesc = 0;
177 struct pmu_cmd cmd = { {0} };
178
179 cmd.hdr.unit_id = PMU_UNIT_THERM;
180 cmd.hdr.size = ((u32)sizeof(struct nv_pmu_therm_cmd_hw_slowdown_notification) +
181 (u32)sizeof(struct pmu_hdr));
182
183 cmd.cmd.therm.cmd_type = NV_PMU_THERM_CMD_ID_HW_SLOWDOWN_NOTIFICATION;
184 cmd.cmd.therm.hw_slct_notification.request =
185 NV_RM_PMU_THERM_HW_SLOWDOWN_NOTIFICATION_REQUEST_ENABLE;
186
187 return therm_pmu_cmd_post(g, &cmd, NULL, NULL,
188 PMU_COMMAND_QUEUE_LPQ,
189 NULL,
190 NULL,
191 &seqdesc, ~0);
192}
193
194static u32 therm_send_slct_configuration_to_pmu(struct gk20a *g)
195{
196 u32 seqdesc = 0;
197 struct pmu_cmd cmd;
198 struct pmu_msg msg;
199 struct pmu_payload payload;
200 struct nv_pmu_therm_rpc rpccall;
201 struct therm_pmucmdhandler_params handlerparams;
202
203 memset(&payload, 0, sizeof(struct pmu_payload));
204 memset(&cmd, 0, sizeof(struct pmu_cmd));
205 memset(&msg, 0, sizeof(struct pmu_msg));
206 memset(&rpccall, 0, sizeof(struct nv_pmu_therm_rpc));
207 memset(&handlerparams, 0, sizeof(struct therm_pmucmdhandler_params));
208
209 rpccall.function = NV_PMU_THERM_RPC_ID_SLCT;
210 rpccall.params.slct.mask_enabled =
211 (1 << NV_PMU_THERM_EVENT_THERMAL_1);
212 rpccall.b_supported = 0;
213
214 cmd.hdr.unit_id = PMU_UNIT_THERM;
215 cmd.hdr.size = ((u32)sizeof(struct nv_pmu_therm_cmd_rpc) +
216 (u32)sizeof(struct pmu_hdr));
217 cmd.cmd.therm.cmd_type = NV_PMU_THERM_CMD_ID_RPC;
218
219 msg.hdr.size = sizeof(struct pmu_msg);
220
221 payload.in.buf = (u8 *)&rpccall;
222 payload.in.size = (u32)sizeof(struct nv_pmu_therm_rpc);
223 payload.in.fb_size = PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED;
224 payload.in.offset = NV_PMU_THERM_CMD_RPC_ALLOC_OFFSET;
225
226 payload.out.buf = (u8 *)&rpccall;
227 payload.out.size = (u32)sizeof(struct nv_pmu_therm_rpc);
228 payload.out.fb_size = PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED;
229 payload.out.offset = NV_PMU_CLK_MSG_RPC_ALLOC_OFFSET;
230
231 /* Setup the handler params to communicate back results.*/
232 handlerparams.success = 0;
233 handlerparams.prpccall = &rpccall;
234
235 return therm_pmu_cmd_post(g, &cmd, NULL, &payload,
236 PMU_COMMAND_QUEUE_LPQ,
237 therm_pmucmdhandler,
238 (void *)&handlerparams,
239 &seqdesc, ~0);
240}
241
242u32 therm_configure_therm_alert(struct gk20a *g)
243{
244 u32 status;
245
246 status = therm_enable_slct_notification_request(g);
247 if (status) {
248 nvgpu_err(g,
249 "therm_enable_slct_notification_request-failed %d",
250 status);
251 goto exit;
252 }
253
254 status = therm_send_slct_configuration_to_pmu(g);
255 if (status) {
256 nvgpu_err(g,
257 "therm_send_slct_configuration_to_pmu-failed %d",
258 status);
259 goto exit;
260 }
261
262 status = therm_set_warn_temp_limit(g);
263 if (status) {
264 nvgpu_err(g,
265 "therm_set_warn_temp_limit-failed %d",
266 status);
267 goto exit;
268 }
269exit:
270 return status;
271}
diff --git a/include/therm/thrmpmu.h b/include/therm/thrmpmu.h
deleted file mode 100644
index 42d5caa..0000000
--- a/include/therm/thrmpmu.h
+++ /dev/null
@@ -1,31 +0,0 @@
1/*
2 * general thermal pmu control structures & definitions
3 *
4 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24#ifndef NVGPU_THERM_THRMPMU_H
25#define NVGPU_THERM_THRMPMU_H
26
27int therm_send_pmgr_tables_to_pmu(struct gk20a *g);
28
29u32 therm_configure_therm_alert(struct gk20a *g);
30
31#endif /* NVGPU_THERM_THRMPMU_H */
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-14 16:54:15 -0500